CN117293095A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN117293095A CN117293095A CN202210690424.XA CN202210690424A CN117293095A CN 117293095 A CN117293095 A CN 117293095A CN 202210690424 A CN202210690424 A CN 202210690424A CN 117293095 A CN117293095 A CN 117293095A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000013078 crystal Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 267
- 239000011810 insulating material Substances 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 4
- 238000004378 air conditioning Methods 0.000 claims 4
- 239000007769 metal material Substances 0.000 abstract description 7
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip packaging structure and a manufacturing method thereof, wherein an insulating protection layer is correspondingly arranged at the circumferential edge position of a surface of a seed layer; the insulating protection layer is arranged on the seed crystal layer of a plurality of rectangular chips on a wafer and corresponds to the positions of a plurality of dividing channels, and then the insulating protection layer is divided along with the dividing channels, so that the insulating protection layer is formed on the chip packaging structure, rather than dividing the thick metal layer as in the prior chip packaging field, the problem that the thick metal layer is difficult to divide due to the metal material and thickness of the thick metal layer is effectively solved, and the cost of a manufacturing end is increased, so that the manufacturing end is beneficial to saving the cost.
Description
Technical Field
The present invention relates to a chip package structure and a method for manufacturing the same, and more particularly, to a chip package structure and a method for manufacturing the same, which effectively solve the problem that the thick metal layer is not easily divided due to the metal material and thickness of the thick metal layer, and the cost of the manufacturing end is increased.
Background
In the field of chip packaging, a plurality of related chip packaging devices are generally disposed on a wafer, and then the wafer is subjected to a dicing operation to separate the related chip packaging devices into individual chip packaging structures. However, in the chip package structure having the thick metal layer, the thick metal layer is not easily divided due to the metal material and thickness of the thick metal layer, which increases the cost of the manufacturing end.
Therefore, a chip package structure having a thick metal layer and a method for manufacturing the same, which can be easily divided when dividing the chip package structure from a wafer, are highly desired in the related industry.
Disclosure of Invention
The present invention provides a chip package structure and a method for fabricating the same, wherein an insulating protection layer is correspondingly disposed at a peripheral edge position on a surface of a seed layer; the insulating protection layer is arranged on the seed crystal layer of a plurality of rectangular chips on a wafer and corresponds to the positions of a plurality of dividing channels, and then the insulating protection layer is divided along with the dividing channels, so that the insulating protection layer is formed on the chip packaging structure, rather than dividing a thick metal layer as in the prior chip packaging field, and the problem that the thick metal layer is difficult to divide due to the metal material and thickness of the thick metal layer is effectively solved, and the cost of a manufacturing end is increased.
In order to achieve the above-mentioned objective, the present invention provides a chip package structure, which comprises a rectangular chip, a seed layer (seed layer), an insulating protection layer and a thick metal layer; the rectangular chip is provided with a first surface and a second surface opposite to the first surface, at least one Die Pad (Die Pad) and at least one protection layer are arranged on the first surface, each Die Pad is correspondingly provided with a bump with proper height, and each protection layer is provided with an opening for the corresponding bump so as to enable the bump to be exposed outwards; the rectangular chip is formed by dividing a wafer, a plurality of rectangular chips and a plurality of dividing channels which are arranged in an array are formed on a first surface of the wafer, and each dividing channel is respectively arranged between two adjacent rectangular chips; the seed crystal layer is correspondingly arranged on the second surface of the rectangular chip in a covering way, and a surface is formed on the seed crystal layer; wherein the insulating protection layer is correspondingly arranged at the circumferential edge position of the surface of the seed crystal layer; the insulating protection layer is arranged on the seed crystal layer of each rectangular chip on the wafer in a plurality of modes, corresponds to the position of each dividing channel, and is divided along with each dividing channel so that the insulating protection layer is formed on the chip packaging structure; the thick metal layer is plated on the surface of the seed crystal layer and is positioned at the inner side of the insulating protection layer, so that the outer side edges of the thick metal layer are all surrounded by the insulating protection layer to obtain the protection of the insulating protection layer, thereby being beneficial to saving the manufacturing cost.
In a preferred embodiment of the present invention, the insulating protective layer is made of a resin material.
In a preferred embodiment of the present invention, the thick metal layer is comprised of copper material.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps: step 1: providing a wafer, wherein a plurality of rectangular chips which are arranged in an array are arranged on the wafer, each rectangular chip is provided with a first surface and a second surface opposite to the first surface, at least one Die Pad (Die Pad) and at least one protection layer are arranged on the first surface, and each Die Pad is correspondingly provided with a bump with proper height; wherein, a plurality of grooves are arranged on a first surface of the wafer, so that each groove is arranged between two adjacent rectangular chips, wherein each groove is used for defining each dividing channel, so that each dividing channel can be formed between two adjacent rectangular chips; wherein the wafer has a second surface opposite to the first surface; step 2: grinding the second surface of the wafer to form a third surface, so that the second surface of each rectangular chip can be exposed on the third surface of the wafer; step 3: a seed layer is arranged on the third surface of the wafer in a covering way, so that the seed layer can be correspondingly arranged on the second surface of each rectangular chip in a covering way; wherein the seed layer is formed with a surface; step 4: a plurality of insulating protection layers are correspondingly arranged on the surface of the seed crystal layer, and each insulating protection layer corresponds to each dividing channel; wherein the width of each insulating protection layer is larger than the width of each dividing channel; step 5: plating a plurality of thick metal layers on the seed crystal layer respectively, wherein each thick metal layer is positioned on the inner side of each insulating protection layer; and step 6: and performing a dividing operation from each dividing channel to divide a plurality of rectangular chips arranged in an array from the wafer into independent chip packaging structures, and surrounding the outer side edge of the thick metal layer of each chip packaging structure with the insulating protection layer to obtain the protection of the insulating protection layer.
The invention also provides a chip packaging structure, which comprises a rectangular chip, a seed layer (seed layer), an insulating protection layer and a thick metal layer; the rectangular chip is provided with a first surface, a second surface opposite to the first surface and four side surfaces which are respectively arranged on four sides of the rectangular chip in a surrounding mode, and the four side surfaces of the rectangular chip are respectively arranged between the first surface and the second surface in an extending mode; wherein the first surface is provided with at least one Die Pad (Die Pad), and each Die Pad is correspondingly provided with a bump with proper height; wherein, at least one protection layer is arranged on the first surface, and each protection layer is provided with an opening for the corresponding bump so as to expose the bump outwards; wherein, a side protection layer is respectively arranged on the four side surfaces of the rectangular chip; the rectangular chip is formed by dividing a wafer, a plurality of rectangular chips and a plurality of dividing channels which are arranged in an array are formed on a first surface of the wafer, each dividing channel is respectively arranged between two adjacent rectangular chips, each dividing channel is filled with each insulating material, each insulating material is divided along with each dividing channel, so that each insulating material is formed on the chip packaging structure to form each side protection layer on four side surfaces of the rectangular chip; the seed crystal layer is correspondingly arranged on the second surface of the rectangular chip in a covering way, and a surface is formed on the seed crystal layer; wherein the insulating protection layer is correspondingly arranged at the circumferential edge position of the surface of the seed crystal layer; the insulating protection layer is arranged on the seed crystal layer of each rectangular chip on the wafer in a plurality of modes, corresponds to the position of each dividing channel, and is divided along with each dividing channel so that the insulating protection layer is formed on the chip packaging structure; the thick metal layer is plated on the surface of the seed crystal layer and is positioned at the inner side of the insulating protection layer, so that the outer side edges of the thick metal layer are all surrounded by the insulating protection layer to obtain the protection of the insulating protection layer; the thick metal layer is provided with a surface, and a protective layer is correspondingly covered on the surface of the thick metal layer, so that the manufacturing end can be manufactured conveniently and cost is saved.
In another preferred embodiment of the present invention, the insulating protective layer is made of a resin material.
In another preferred embodiment of the present invention, the thick metal layer is comprised of a copper material.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps: step 1: providing a wafer, wherein a plurality of rectangular chips which are arranged in an array are arranged on the wafer, each rectangular chip is provided with a first surface, a second surface opposite to the first surface and four side surfaces which are respectively arranged on four sides of the rectangular chip in a surrounding mode, the four side surfaces of the rectangular chip are respectively arranged between the first surface and the second surface in an extending mode, at least one protection layer is arranged on the first surface of the rectangular chip, and each protection layer is provided with an opening for the corresponding bump so that the bump is exposed outwards; wherein the first surface is provided with at least one Die Pad (Die Pad), and each Die Pad is correspondingly provided with a bump with proper height; wherein a plurality of grooves are arranged on a first surface of the wafer so that each groove is arranged between two adjacent rectangular chips, wherein each groove is used for defining each dividing channel, each dividing channel can be formed between two adjacent rectangular chips, the width of each dividing channel is smaller than the width of each groove, and insulating materials are filled in each groove; wherein the wafer has a second surface opposite to the first surface; step 2: grinding the second surface of the wafer to form a third surface, so that the second surface of each rectangular chip can be exposed on the third surface of the wafer; step 3: a plurality of seed layers are arranged on the third surface of the wafer in a covering way, so that each seed layer can be correspondingly arranged on the second surface of each rectangular chip in a covering way; wherein each seed layer is formed with a surface; step 4: a plurality of insulating protection layers are correspondingly arranged on the surface of each seed crystal layer, and each insulating protection layer corresponds to each dividing channel; wherein the width of each insulating protection layer is larger than the width of each dividing channel; step 5: plating a plurality of thick metal layers on each seed crystal layer respectively, wherein each thick metal layer is positioned on the inner side of each insulating protection layer; wherein each thick metal layer has a surface; step 6: a protective layer is respectively and correspondingly arranged on each surface of each thick metal; step 7: dividing the rectangular chips arranged in an array from the wafer into independent chip packaging structures, and surrounding the outer side edge of the thick metal layer on each chip packaging structure with the insulating protection layer to obtain the protection of the insulating protection layer; the insulating materials in each groove are divided along with each dividing channel, so that each insulating material is formed on each chip packaging structure to form side protection layers on four side surfaces of each rectangular chip.
Drawings
Fig. 1 is a schematic cross-sectional side view illustrating formation of bumps on pads on a wafer according to a first embodiment of the present invention.
Fig. 2 is a schematic side cross-sectional view of the wafer of fig. 1 after polishing to expose a third surface of the wafer.
Fig. 3 is a schematic side cross-sectional view of the third surface of the wafer of fig. 2 with a seed layer overlying the third surface.
Fig. 4 is a schematic side cross-sectional view of the wafer of fig. 3 with a plurality of insulating protection layers disposed on a surface of a seed layer.
Fig. 5 is a schematic side cross-sectional view of the wafer of fig. 4 with a plurality of thick metal layers disposed on a surface of a seed layer.
Fig. 6 is a schematic side cross-sectional view of the wafer of fig. 5 undergoing a dicing operation.
Fig. 7 is a schematic side sectional view of a first embodiment of the present invention.
Fig. 8 is a schematic side cross-sectional view illustrating the formation of bumps on pads on a wafer according to a second embodiment of the present invention.
Fig. 9 is a schematic side cross-sectional view of the wafer of fig. 8 after polishing to expose a third surface of the wafer.
Fig. 10 is a schematic side cross-sectional view of the wafer of fig. 9 with a plurality of insulating protective layers disposed on the surface thereof.
Fig. 11 is a schematic side cross-sectional view of the wafer of fig. 10 with a plurality of seed layers disposed on a surface thereof.
Fig. 12 is a schematic side cross-sectional view of the wafer of fig. 11 with a plurality of thick metal layers disposed on the surface of each seed layer.
Fig. 13 is a schematic side cross-sectional view of the wafer of fig. 12 with multiple protective layers disposed on the surface of each thick metal layer.
Fig. 14 is a schematic side cross-sectional view of the wafer of fig. 13 undergoing a dicing operation.
Fig. 15 is a schematic side cross-sectional view of a second embodiment of the present invention.
Reference numerals illustrate: 1-a chip packaging structure; 10-rectangular chips; 11-a first surface; 12-a second surface; 13-a die pad; 14-bump; 15-a side protective layer; 20-a seed layer; 21-surface; 30-an insulating protective layer; 40-thick metal layer; 50-a protective layer; 2-wafer; 2 a-a first surface; 2 b-dividing the tracks; 2 c-a second surface; 2 d-a third surface; 2 e-grooves.
Detailed Description
The following detailed description of the structure and technical features of the present invention is provided with reference to the drawings, wherein each drawing is only for illustrating the structural relationship and related functions of the present invention, and thus the dimensions of each element in each drawing are not drawn to actual scale and are not intended to limit the present invention.
Referring to fig. 1 and 15, the present invention provides a chip package structure 1, and the chip package structure 1 includes a rectangular chip 10, a seed layer 20, an insulating protection layer 30 and a thick metal layer 40, and is further divided into a first embodiment (as shown in fig. 1 to 7) and a second embodiment (as shown in fig. 8 to 15) according to the number of the protection layers of the chip package structure 1, but not limited thereto, and the first embodiment (as shown in fig. 1 to 7) and the second embodiment (as shown in fig. 8 to 15) will be described below, respectively.
The embodiment shown in fig. 1 to 7 is a first embodiment of the chip package structure 1 of the present invention.
The rectangular chip 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, wherein the first surface 11 is provided with at least one Die Pad (Die Pad) 13 and at least one protection layer, each Die Pad 13 is respectively and correspondingly provided with a bump 14 with a proper height as shown in fig. 7, and each protection layer is provided with an opening for the corresponding bump 14 so that the bump 14 is exposed outwards as shown in fig. 7; the rectangular chip 10 is formed by dividing a wafer 2, wherein a first surface 2a of the wafer 2 is formed with a plurality of rectangular chips 10 and a plurality of dividing channels 2b arranged in an array, and each dividing channel 2b is respectively disposed between two adjacent rectangular chips 10 as shown in fig. 5.
The seed layer 20 is correspondingly disposed on the second surface 12 of the rectangular chip 10, and the seed layer 20 is formed with a surface 21 as shown in fig. 7; the seed layer 20 can control the size, shape or thickness of the thick metal layer 40 more accurately, thereby improving the yield of the product and reducing the cost of manufacturing.
The insulating protection layer 30 is correspondingly disposed at the circumferential position of the surface 21 of the seed layer 20 as shown in fig. 7; the insulating protection layer 30 is formed on the seed layer 20 of each rectangular chip 10 on the wafer 2 by a plurality of insulating protection layers 30, and the positions corresponding to each dividing channel 2b are shown in fig. 5, and then divided along with each dividing channel 2b into fig. 6, so that the insulating protection layer 30 is formed on the chip package structure 1 as shown in fig. 7.
The insulating protection layer 30 is made of a resin material, but is not limited thereto, so that the insulating protection layer can be easily divided in the wafer dividing operation than the metal material.
The thick metal layer 40 is plated on the surface 21 of the seed layer 20 and is located inside the insulating protection layer 30, so that the outer side edges of the thick metal layer 40 are all surrounded by the insulating protection layer 30 to obtain the protection of the insulating protection layer 30 as shown in fig. 7.
Wherein the thick metal layer 40 is composed of a copper material but is not limited thereto; wherein the thick metal layer 40 can increase the heat dissipation or resistance of the chip package structure 1.
Referring to fig. 1 to 6, the method for manufacturing the first embodiment of the chip package structure 1 of the present invention includes the following steps:
step 1: providing a wafer 2, wherein a plurality of rectangular chips 10 arranged in an array are disposed on the wafer 2, each rectangular chip 10 has a first surface 11 and a second surface 12 opposite to the first surface 11, at least one Die Pad (Die Pad) 13 and at least one protection layer are disposed on the first surface 11, and each Die Pad 13 is correspondingly provided with a bump 14 having a proper height as shown in fig. 1; wherein a plurality of grooves 2e are formed on a first surface 2a of the wafer 2, such that each groove 2e is disposed between two adjacent rectangular chips 10, wherein each groove 2e is used to define each dividing channel 2b, such that each dividing channel 2b can be formed between two adjacent rectangular chips 10 as shown in fig. 1; wherein the wafer 2 has a second surface 2c opposite to the first surface 2a as shown in fig. 1.
Step 2: the second surface 2c of the wafer 2 is polished to form a third surface 2d as shown in fig. 1 and 2, so that the second surface 12 of each rectangular chip 10 is exposed on the third surface 2d of the wafer 2 as shown in fig. 2.
Step 3: a seed layer 20 is disposed on the third surface 2d of the wafer 2 in a covering manner, so that the second surface 12 of each rectangular chip 10 can be correspondingly disposed with the seed layer 20 as shown in fig. 3; wherein the seed layer 20 is formed with a surface 21 as shown in fig. 3.
Step 4: a plurality of insulating protection layers 30 are correspondingly disposed on the surface 21 of the seed layer 20, and each insulating protection layer 30 corresponds to each of the dividing channels 2b as shown in fig. 4; the width of each insulating protection layer 30 is larger than the width of each dividing channel 2b as shown in fig. 4.
Step 5: a plurality of thick metal layers 40 are respectively plated on the seed layer 20, and each thick metal layer 40 is located inside each insulating protection layer 30 as shown in fig. 5.
Step 6: the dividing operation is performed from each dividing channel 2b to divide the rectangular chips 10 arranged in an array from the wafer 2 into the individual chip packages 1 as shown in fig. 6, and the outer side of the thick metal layer 40 of each chip package 1 is surrounded by the insulating protection layer 30 to obtain the protection of the insulating protection layer 30 as shown in fig. 6 and 7.
The embodiment shown in fig. 8 to 15 is a second embodiment of the chip package structure 1 of the present invention.
The rectangular chip 10 has a first surface 11, a second surface 12 opposite to the first surface 11, and four side surfaces respectively surrounding the four sides of the rectangular chip 10, and the four side surfaces of the rectangular chip 10 are respectively located between the first surface 11 and the second surface 12; wherein the first surface 11 is provided with at least one Die Pad (Die Pad) 13, and each Die Pad 13 is provided with a bump 14 with a proper height correspondingly as shown in fig. 15; wherein at least one protection layer is disposed on the first surface 11, and each protection layer has an opening for the corresponding bump 14 to expose the bump 14 to the outside as shown in fig. 15; wherein a side protection layer 15 is provided on each of four side surfaces of the rectangular chip 10 as shown in fig. 15; the rectangular chip 10 is formed by dividing a wafer 2, wherein a first surface 2a of the wafer 2 is formed with a plurality of rectangular chips 10 and a plurality of dividing channels 2b arranged in an array, and each dividing channel 2b is respectively disposed between two adjacent rectangular chips 10, each dividing channel 2b is filled with each insulating material as shown in fig. 13, and each insulating material is divided along with each dividing channel 2b, so that each insulating material is formed on the chip package structure 1 to form each side protection layer 15 on four side surfaces of the rectangular chip 10 as shown in fig. 15, so as to facilitate enhanced protection.
The seed layer 20 is correspondingly disposed on the second surface 12 of the rectangular chip 10, and the seed layer 20 is formed with a surface 21 as shown in fig. 15; the seed layer 20 can control the size, shape or thickness of the thick metal layer 40 more accurately, thereby improving the yield of the product and reducing the cost of manufacturing.
The insulating protection layer 30 is correspondingly disposed at the circumferential position of the surface 21 of the seed layer 20 as shown in fig. 15; the insulating protection layer 30 is formed on the seed layer 20 of each rectangular chip 10 on the wafer 2 by a plurality of insulating protection layers 30, and the positions corresponding to the dividing channels 2b are shown in fig. 12, and then divided along with each dividing channel 2b into fig. 13, so that the insulating protection layer 30 is formed on the chip package structure 1 as shown in fig. 15.
The insulating protection layer 30 is made of a resin material, but is not limited thereto, so that the insulating protection layer can be easily divided in the wafer dividing operation than the metal material.
The thick metal layer 40 is plated on the surface 21 of the seed layer 20 and is located inside the insulating protection layer 30, so that the outer side edges of the thick metal layer 40 are all surrounded by the insulating protection layer 30 to obtain the protection of the insulating protection layer 30 as shown in fig. 15; the thick metal layer 40 has a surface 41, and a protection layer 50 is correspondingly disposed on the surface 41 of the thick metal layer 40 as shown in fig. 15 for protection.
Wherein the thick metal layer 40 is composed of a copper material but is not limited thereto; wherein the thick metal layer 40 can increase the heat dissipation or resistance of the chip package structure 1.
Referring to fig. 8 to 14, the method for manufacturing the second embodiment of the chip package structure 1 of the present invention includes the following steps:
step 1: providing a wafer 2, wherein a plurality of rectangular chips 10 arranged in an array are disposed on the wafer 2, each rectangular chip 10 has a first surface 11, a second surface 12 opposite to the first surface 11, and four side surfaces respectively surrounding the four sides of the rectangular chip 10, and the four side surfaces of the rectangular chip 10 are respectively extended between the first surface 11 and the second surface 12, at least one protection layer is disposed on the first surface 11 of the rectangular chip 10, and each protection layer has an opening for the corresponding bump 14 to expose the bump 14 outwards as shown in fig. 8; wherein the first surface 11 is provided with at least one Die Pad (Die Pad) 13, and each Die Pad 13 is correspondingly provided with a bump 14 with a proper height as shown in fig. 8; wherein a plurality of grooves 2e are formed on a first surface 2a of the wafer 2 such that each groove 2e is disposed between two adjacent rectangular chips 10, wherein each groove 2e is used for defining a respective dividing channel 2b, such that each dividing channel 2b can be formed between two adjacent rectangular chips 10, and a width of each dividing channel 2b is smaller than a width of each groove 2e, wherein each groove 2e is filled with an insulating material as shown in fig. 8; wherein the wafer 2 has a second surface 2c opposite to the first surface 2a as shown in fig. 8.
Step 2: the second surface 2c of the wafer 2 is polished to form a third surface 2d as shown in fig. 8 and 9, so that the second surface 12 of each rectangular chip 10 can be exposed on the third surface 2d of the wafer 2 as shown in fig. 9.
Step 3: a plurality of seed layers 20 are provided on the third surface 2d of the wafer 2 in a covering manner, so that each seed layer 20 can be provided on the second surface 12 of each rectangular chip 10 in a corresponding covering manner as shown in fig. 10; wherein each of the seed layers 20 is formed with a surface 21 as shown in fig. 10.
Step 4: a plurality of insulating protection layers 30 are correspondingly disposed on the surface 21 of each seed layer 20, and each insulating protection layer 30 corresponds to each partition 2b as shown in fig. 11; the width of each insulating protection layer 30 is larger than the width of each dividing channel 2b as shown in fig. 11.
Step 5: a plurality of thick metal layers 40 are respectively plated on each seed layer 20, and each thick metal layer 40 is located inside each insulating protection layer 30 as shown in fig. 12; wherein each of the thick metal layers 40 has a surface 41 as shown in fig. 12.
Step 6: a protective layer 50 is provided over each of the surfaces 41 of each of the thick metals 40 as shown in fig. 13.
Step 7: dividing the rectangular chips 10 arranged in an array from the wafer 2 into individual chip packages 1 by performing a dividing operation on each dividing street 2b, and surrounding the outer side of the thick metal layer 40 on each chip package 1 with the insulating protection layer 30 to obtain protection of the insulating protection layer 30 as shown in fig. 14; wherein the insulating materials in each of the grooves 2e are divided together with the dividing lines 2b so that each of the insulating materials is formed on the chip package structure 1 to constitute the side protection layers 15 on the four side surfaces of the rectangular chips 10 as shown in fig. 14.
Compared with the existing chip packaging structure, the chip packaging structure 1 has the following advantages:
the insulating protection layer 30 of the present invention is correspondingly disposed at the circumferential edge of the surface 21 of the seed layer 20, wherein the insulating protection layer 30 is disposed on the seed layer 20 of each rectangular chip 10 on the wafer 2 by a plurality of insulating protection layers 30 and corresponds to the position of each dividing channel 2b, and then is divided along with each dividing channel 2b, so that the insulating protection layer 30 is formed on the chip package structure 1, instead of dividing the thick metal layer as in the conventional chip package field, the problem that the thick metal layer is not easily divided due to the metal material and thickness of the thick metal layer itself, and the cost of the manufacturing end is increased is effectively solved, thereby facilitating the cost saving of the manufacturing end.
The foregoing is merely a preferred embodiment of the present invention, which is intended to be illustrative and not limiting; it will be appreciated by those skilled in the art that many variations, modifications and even equivalent changes may be made thereto within the spirit and scope of the invention as defined in the appended claims, but are still within the scope of the invention.
Claims (8)
1. A chip package structure, comprising:
the rectangular chip is provided with a first surface and a second surface opposite to the first surface, the first surface is provided with at least one crystal pad and at least one protection layer, each crystal pad is correspondingly provided with a bump with proper height, and each protection layer is provided with an opening for the corresponding bump so as to expose the bump outwards; the rectangular chip is formed by dividing a wafer, a plurality of rectangular chips and a plurality of dividing channels which are arranged in an array are formed on a first surface of the wafer, and each dividing channel is respectively arranged between two adjacent rectangular chips;
a seed crystal layer correspondingly arranged on the second surface of the rectangular chip in a covering way, wherein the seed crystal layer is provided with a surface;
an insulating protection layer correspondingly arranged at the circumferential edge of the surface of the seed crystal layer; the insulating protection layer is arranged on the seed crystal layer of each rectangular chip on the wafer in a plurality of modes, corresponds to the position of each dividing channel, and is divided along with each dividing channel so that the insulating protection layer is formed on the chip packaging structure; a kind of electronic device with high-pressure air-conditioning system
The thick metal layer is plated on the surface of the seed crystal layer and is positioned on the inner side of the insulating protection layer, so that the outer side edges of the thick metal layer are all surrounded by the insulating protection layer to obtain the protection of the insulating protection layer.
2. The chip package structure of claim 1, wherein the insulating protective layer is made of a resin material.
3. The chip package structure of claim 1, wherein the thick metal layer is comprised of a copper material.
4. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
step 1: providing a wafer, wherein a plurality of rectangular chips which are arranged in an array are arranged on the wafer, each rectangular chip is provided with a first surface and a second surface opposite to the first surface, at least one crystal pad and at least one protection layer are arranged on the first surface, and each crystal pad is correspondingly provided with a bump with proper height; wherein, a plurality of grooves are arranged on a first surface of the wafer, so that each groove is arranged between two adjacent rectangular chips, wherein each groove is used for defining each dividing channel, so that each dividing channel can be formed between two adjacent rectangular chips; wherein the wafer has a second surface opposite to the first surface;
step 2: grinding the second surface of the wafer to form a third surface, so that the second surface of each rectangular chip can be exposed on the third surface of the wafer;
step 3: a seed crystal layer is arranged on the third surface of the wafer in a covering way, so that the seed crystal layer can be correspondingly arranged on the second surface of each rectangular chip in a covering way; wherein the seed layer is formed with a surface;
step 4: a plurality of insulating protection layers are correspondingly arranged on the surface of the seed crystal layer, and each insulating protection layer corresponds to each dividing channel; wherein the width of each insulating protection layer is larger than the width of each dividing channel;
step 5: plating a plurality of thick metal layers on the seed crystal layer respectively, wherein each thick metal layer is positioned on the inner side of each insulating protection layer; a kind of electronic device with high-pressure air-conditioning system
Step 6: and performing a dividing operation from each dividing channel to divide a plurality of rectangular chips arranged in an array from the wafer into independent chip packaging structures, and surrounding the outer side edge of the thick metal layer of each chip packaging structure with the insulating protection layer to obtain the protection of the insulating protection layer.
5. A chip package structure, comprising:
the rectangular chip is provided with a first surface, a second surface opposite to the first surface and four side surfaces, wherein the four side surfaces of the rectangular chip are respectively arranged on four sides of the rectangular chip in a surrounding mode, and the four side surfaces of the rectangular chip are respectively arranged between the first surface and the second surface in an extending mode; wherein the first surface is provided with at least one die pad, and each die pad is correspondingly provided with a bump with proper height; wherein, at least one protection layer is arranged on the first surface, and each protection layer is provided with an opening for the corresponding bump so as to expose the bump outwards; wherein, a side protection layer is respectively arranged on the four side surfaces of the rectangular chip; the rectangular chip is formed by dividing a wafer, a plurality of rectangular chips and a plurality of dividing channels which are arranged in an array are formed on a first surface of the wafer, each dividing channel is respectively arranged between two adjacent rectangular chips, each dividing channel is filled with insulating materials, each insulating material can be divided along with each dividing channel, so that each insulating material is formed on the chip packaging structure to form each side protection layer on four side surfaces of the rectangular chip;
a seed crystal layer correspondingly arranged on the second surface of the rectangular chip in a covering way, wherein the seed crystal layer is provided with a surface;
an insulating protection layer correspondingly arranged at the circumferential edge of the surface of the seed crystal layer; the insulating protection layer is arranged on the seed crystal layer of each rectangular chip on the wafer in a plurality of modes, corresponds to the position of each dividing channel, and is divided along with each dividing channel so that the insulating protection layer is formed on the chip packaging structure; a kind of electronic device with high-pressure air-conditioning system
A thick metal layer plated on the surface of the seed layer and located at the inner side of the insulating protection layer, so that the outer side edges of the thick metal layer are all surrounded by the insulating protection layer to obtain the protection of the insulating protection layer;
the thick metal layer is provided with a surface, and a protective layer is correspondingly covered on the surface of the thick metal layer.
6. The chip package structure of claim 5, wherein the insulating protective layer is made of a resin material.
7. The chip package structure of claim 5, wherein the thick metal layer is made of copper material.
8. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
step 1: providing a wafer, wherein a plurality of rectangular chips which are arranged in an array are arranged on the wafer, each rectangular chip is provided with a first surface, a second surface opposite to the first surface and four side surfaces which are respectively arranged on four sides of the rectangular chip in a surrounding mode, the four side surfaces of the rectangular chip are respectively arranged between the first surface and the second surface in an extending mode, at least one protection layer is arranged on the first surface of the rectangular chip, and each protection layer is provided with an opening for the corresponding bump so that the bump is exposed outwards; wherein the first surface is provided with at least one die pad, and each die pad is correspondingly provided with a bump with proper height; wherein a plurality of grooves are arranged on a first surface of the wafer so that each groove is arranged between two adjacent rectangular chips, wherein each groove is used for defining each dividing channel, each dividing channel can be formed between two adjacent rectangular chips, the width of each dividing channel is smaller than the width of each groove, and insulating materials are filled in each groove; wherein the wafer has a second surface opposite to the first surface;
step 2: grinding the second surface of the wafer to form a third surface, so that the second surface of each rectangular chip can be exposed on the third surface of the wafer;
step 3: a plurality of seed crystal layers are arranged on the third surface of the wafer in a covering manner, so that each seed crystal layer can be correspondingly arranged on the second surface of each rectangular chip in a covering manner; wherein each seed layer is formed with a surface;
step 4: a plurality of insulating protection layers are correspondingly arranged on the surface of each seed crystal layer, and each insulating protection layer corresponds to each dividing channel; wherein the width of each insulating protection layer is larger than the width of each dividing channel;
step 5: plating a plurality of thick metal layers on each seed crystal layer respectively, wherein each thick metal layer is positioned on the inner side of each insulating protection layer; wherein each thick metal layer has a surface;
step 6: a protective layer is respectively and correspondingly arranged on each surface of each thick metal; a kind of electronic device with high-pressure air-conditioning system
Step 7: dividing the rectangular chips arranged in an array from the wafer into independent chip packaging structures, and surrounding the outer side edge of the thick metal layer on each chip packaging structure with the insulating protection layer to obtain the protection of the insulating protection layer; the insulating materials in each groove can be divided along with each dividing channel, so that each insulating material is formed on each chip packaging structure to form side protection layers on four side surfaces of each rectangular chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210690424.XA CN117293095A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210690424.XA CN117293095A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN117293095A true CN117293095A (en) | 2023-12-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210690424.XA Pending CN117293095A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN117293095A (en) |
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- 2022-06-17 CN CN202210690424.XA patent/CN117293095A/en active Pending
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