CN117290119A - Method and device for detecting kernel deadlock, electronic equipment and storage medium - Google Patents

Method and device for detecting kernel deadlock, electronic equipment and storage medium Download PDF

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Publication number
CN117290119A
CN117290119A CN202311483921.3A CN202311483921A CN117290119A CN 117290119 A CN117290119 A CN 117290119A CN 202311483921 A CN202311483921 A CN 202311483921A CN 117290119 A CN117290119 A CN 117290119A
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China
Prior art keywords
deadlock
kernel
interrupt
hard
core
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周芸生
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Ecarx Hubei Tech Co Ltd
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Ecarx Hubei Tech Co Ltd
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Priority to CN202311483921.3A priority Critical patent/CN117290119A/en
Publication of CN117290119A publication Critical patent/CN117290119A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The embodiment of the application provides a method, a device, an electronic device and a storage medium for detecting a kernel deadlock, wherein the method is applied to the electronic device, and the electronic device comprises an ARM chip and a plurality of central processing units, and comprises the following steps: when detecting that a first central processor in the plurality of central processors has a kernel hard deadlock, sending a pre-registered target inter-core interrupt to the first central processor through a second central processor, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the kernel hard deadlock; carrying out stack backtracking through the first central processing unit to obtain a stack backtracking result; and determining the reason for causing the hard deadlock of the kernel according to the stack backtracking result. In this way, the central processor stack backtracking with the kernel hard deadlock can be triggered through the preregistered inter-kernel interrupt, so that the reason causing the kernel hard deadlock is positioned.

Description

Method and device for detecting kernel deadlock, electronic equipment and storage medium
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for detecting a kernel deadlock, an electronic device, and a storage medium.
Background
In the running process of the electronic equipment, the situation that the kernel of the electronic equipment is deadlocked can be caused due to the fact that 2 or more processes running on the electronic equipment compete for needle resources and the like. The kernel deadlock of the electronic device includes a kernel hard deadlock, and when the electronic device is in the kernel hard deadlock, a situation that a central processing unit (Central Processing Unit, abbreviated as a CPU) cannot be scheduled and an interrupt cannot be received may occur.
Currently, the combination of an ARM chip and a Linux operating system can be applied to more fields, such as automobile equipment in the automobile field, and the like. During the operation of the ARM chip, the condition of hard deadlock of the kernel can also occur. Therefore, detection of ARM chip kernel hard deadlock is a problem to be solved.
Disclosure of Invention
The embodiment of the application provides a method, a device, electronic equipment and a storage medium for detecting kernel deadlock, which can realize detection of ARM chip kernel hard deadlock.
In a first aspect, an embodiment of the present application provides detection of a kernel deadlock, which is applied to an electronic device, where the electronic device includes an ARM chip and a plurality of central processors, and includes:
when detecting that a first central processor in the plurality of central processors has a kernel hard deadlock, sending a pre-registered target inter-core interrupt to the first central processor through a second central processor, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the kernel hard deadlock;
receiving the target inter-core interrupt by the first central processing unit, and performing stack backtracking to obtain a stack backtracking result;
and determining the reason for causing the kernel hard deadlock according to the stack backtracking result.
In a possible implementation manner, the stack trace result includes a plurality of function call information of the first central processor before the occurrence of the ARM kernel hard deadlock;
the determining the reason of the ARM core hard deadlock according to the stack backtracking result comprises the following steps:
and determining target function call information causing the kernel hard deadlock from the plurality of function call information.
In a possible implementation manner, the electronic device includes an ARM interrupt controller, and the method further includes:
when the electronic equipment is started, according to the interrupt priority of the ARM interrupt controller, registering the target inter-core interrupt with the highest priority through a preset kernel function.
In one possible implementation, the target inter-core interrupt is an emulated unmasked interrupt.
In a possible implementation manner, the method further includes:
detecting whether the scheduling state and the interrupt receiving state of each central processing unit in the plurality of central processing units are abnormal or not by using a kernel deadlock detection mechanism;
and when detecting that the scheduling state and the interrupt receiving state of the first central processing unit are abnormal, determining that the first central processing unit has kernel hard deadlock.
In a possible implementation manner, when determining a cause of the kernel hard deadlock, the method further includes:
detecting the value of the panic identifier;
when the value of the panic identifier is a first value, controlling an operating system of the electronic equipment to enter a panic state;
and when the value of the panic identifier is a second value, controlling an operating system of the electronic equipment to enter a panic state.
In a possible implementation manner, the method further includes:
receiving a preset value input by a user through a target interface, wherein the preset value comprises a first value or a second value;
and setting the value of the panic identifier as the preset value.
In a second aspect, an embodiment of the present application provides a device for detecting a kernel deadlock, including:
the sending module is used for sending a pre-registered target inter-core interrupt to a first central processor through a second central processor when detecting that the first central processor in the plurality of central processors has a core hard deadlock, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the core hard deadlock;
the processing module is used for receiving the inter-target-core interrupt through the first central processing unit and carrying out stack backtracking to obtain a stack backtracking result; and determining the reason for causing the kernel hard deadlock according to the stack backtracking result.
In a possible implementation manner, the stack trace result includes a plurality of function call information of the first central processor before the occurrence of the ARM kernel hard deadlock; the processing module is specifically configured to determine, from the plurality of function call information, target function call information that causes the kernel hard deadlock.
In a possible implementation manner, the electronic device includes an ARM interrupt controller, and the apparatus further includes a registration module, where the registration module is configured to register, when the electronic device is started, the target inter-core interrupt with the highest priority through a preset kernel function according to the interrupt priority of the ARM interrupt controller.
In one possible implementation, the target inter-core interrupt is an emulated unmasked interrupt.
In a possible implementation manner, the processing module is further configured to detect, using a kernel deadlock detection mechanism, whether a scheduling state and an interrupt receiving state of each of the plurality of central processing units are abnormal; and when detecting that the scheduling state and the interrupt receiving state of the first central processing unit are abnormal, determining that the first central processing unit has kernel hard deadlock.
In a possible implementation manner, the processing module is further configured to detect a value of the panic identifier; when the value of the panic identifier is a first value, controlling an operating system of the electronic equipment to enter a panic state; and when the value of the panic identifier is a second value, controlling an operating system of the electronic equipment to enter a panic state.
In a possible implementation manner, the processing module is further configured to receive a preset value input by a user through the target interface, where the preset value includes a first value or a second value; and setting the value of the panic identifier as the preset value.
In a third aspect, embodiments of the present application further provide an electronic device, including: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method as described in any one of the possible implementations of the first aspect.
In a fourth aspect, embodiments of the present application further provide a computer readable storage medium, where computer executable instructions are stored, and when executed by a processor, implement the method described in any one of the possible implementation manners of the first aspect.
It can be seen that the embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for detecting a kernel deadlock, where the method is applied to an electronic device, and the electronic device includes an ARM chip and a plurality of central processors, and includes: when detecting that a first central processor in the plurality of central processors has a kernel hard deadlock, sending a pre-registered target inter-core interrupt to the first central processor through a second central processor, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the kernel hard deadlock; receiving the inter-target-core interrupt through the first central processing unit, and carrying out stack backtracking to obtain a stack backtracking result; and determining the reason for causing the hard deadlock of the kernel according to the stack backtracking result. In this way, through preregistering the inter-core interrupt with higher priority, when the core hard deadlock exists in the central processing unit, the preregistered inter-core interrupt can be sent to the core hard deadlock-existing central processing unit through the normal processor, so that the core hard deadlock-existing central processing unit can trigger stack backtracking, and the reason for causing the core hard deadlock is positioned.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flow chart of a method for detecting a kernel deadlock according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating another method for detecting a kernel deadlock according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a device for detecting a kernel deadlock according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and provide corresponding operation entries for the user to select authorization or rejection.
In embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. In the text description of the present application, the character "/" generally indicates that the front-rear association object is an or relationship.
With the development of technology, the combination of an ARM chip and a Linux operating system is applied to more and more fields, for example, automobile equipment in the automobile field, and the like.
At present, for the electronic equipment combined by the ARM chip and the Linux operating system, in the running process, the situation of hard deadlock of the kernel of the CPU can be caused by the problems of unreasonable process scheduling in the CPU and the like. However, the kernel hard deadlock may cause various problems in the operation of the Linux operating system, and may even cause that the Linux operating system cannot operate normally. Therefore, detecting the hard deadlock of the kernel occurring in the electronic device is a problem to be solved.
Based on this, the embodiment of the application provides a method for detecting a kernel hard deadlock, which considers that when a central processing unit is in the kernel hard deadlock, the central processing unit cannot receive an interrupt, so that the inter-kernel interrupt can be received by the central processing unit with the kernel hard deadlock by registering the inter-kernel interrupt with higher priority in advance. In this way, when the central processor in the electronic device has the kernel hard deadlock, the pre-registered inter-kernel interrupt can be sent to the central processor through other normal processors, so that the central processor can trigger stack backtracking when receiving the inter-kernel interrupt, and the reason of the kernel hard deadlock is positioned through the stack backtracking.
The method for detecting the kernel deadlock provided by the application will be described in detail through a specific embodiment. It is to be understood that the following embodiments may be combined with each other and that some embodiments may not be repeated for the same or similar concepts or processes.
The method for detecting the kernel deadlock provided by the embodiment of the application is explained below. Fig. 1 is a flow chart of a method for detecting a kernel deadlock according to an embodiment of the present application. The method for detecting the kernel deadlock can be executed by software and/or hardware devices, for example, the hardware devices can be kernel deadlock detection devices, and the kernel deadlock detection devices can be electronic devices or processing chips in the electronic devices.
In the embodiment of the application, the processing chip in the electronic device is an ARM chip, and the electronic device may include a plurality of central processing units. The number of the central processing units is not limited in the embodiment of the application.
For example, as shown in fig. 1, the method for detecting the kernel deadlock may include:
s101, when detecting that a first central processor in the plurality of central processors has a kernel hard deadlock, sending a pre-registered target inter-core interrupt to the first central processor through a second central processor.
The priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processing unit during normal operation, and the second central processing unit is any one of the central processing units without the hard deadlock of the core.
For example, when detecting whether a core hard deadlock occurs in a plurality of central processing units, a core deadlock detection mechanism may be used to detect whether a scheduling state and an interrupt receiving state of each of the plurality of central processing units are abnormal; and when detecting that the scheduling state and the interrupt receiving state of the first central processing unit are abnormal, determining that the first central processing unit has kernel hard deadlock.
Illustratively, whether a central processor scheduling state occurs, i.e., whether the central processor is able to schedule normally. Whether the interrupt receiving state of the central processing unit occurs, that is, whether the central processing unit can receive the interrupt.
It should be noted that, when the central processing unit does not have a kernel hard deadlock, the central processing unit can normally schedule and/or can receive an interrupt. Thus, when a central processor is unable to schedule and receive interrupts, it may be determined that the central processor has a core hard deadlock.
By way of example, the kernel deadlock detection mechanism may be RCU ARM CPU stall detection, which is not limited by the embodiments of the present application.
In this way, by detecting the scheduling state and the interrupt receiving state of the central processing unit, whether the central processing unit is in the hard deadlock of the kernel is determined, so that the accuracy of determining the hard deadlock of the kernel is higher.
S102, receiving the inter-core interrupt through the first central processing unit, and carrying out stack backtracking to obtain a stack backtracking result.
The electronic device may receive the target inter-core interrupt through the first central processor, and when the first central processor receives the target inter-core interrupt, may trigger stack trace back, so as to obtain a stack trace back result.
It should be noted that, the stack trace may call the stack behavior of the first central processing unit with the kernel hard deadlock, and the obtained stack trace result may include a call relationship, a call sequence, and the like before each stack in the first central processing unit.
S103, determining the reason for causing the hard deadlock of the kernel according to the stack backtracking result.
In an embodiment of the present application, the stack trace-back result may include a plurality of function call information of the first central processor before the occurrence of the ARM core hard deadlock. The function call message may include a call relation, a called relation, a call sequence, etc. of the function, and the embodiment of the application does not limit the call information of the call function.
For example, when determining the reason of the ARM kernel hard deadlock according to the stack backtracking result, the target function call information causing the kernel hard deadlock can be determined from a plurality of function call information.
Therefore, according to the kernel hard deadlock detection method provided by the embodiment of the application, by registering the inter-kernel interrupt with higher priority in advance, when the kernel hard deadlock exists in the central processing unit, the pre-registered inter-kernel interrupt can be sent to the central processing unit with the kernel hard deadlock through the normal processor, so that the central processing unit with the kernel hard deadlock can trigger a stack to trace back, and therefore the reason causing the kernel hard deadlock is located.
In the embodiment of the application, the electronic equipment comprises an ARM interrupt controller (generic interrupt controller, abbreviated as GIC). When the electronic equipment is started, according to the interrupt priority of the ARM interrupt controller, registering the target inter-core interrupt with the highest priority through a preset kernel function.
For example, the electronic device may register the target inter-core interrupt through a request_pseudo_nmi kernel function.
In the embodiment of the application, when the electronic device is started, the kernel enables config_arm 64_pseudodo_nmi configuration and irqchip.gicv3_pseudo_nmi=1 is input in cmdline, so that the electronic device can register the target inter-core interrupt according to the interrupt priority of the ARM interrupt controller.
The embodiment of the present application is only described by taking the above method for registering the inter-core interrupt as an example, and is not limited in any way.
In this way, the registration of the target inter-core interrupt is performed when the electronic device is started, so that when the central processing unit is in the hard deadlock of the core, the target inter-core interrupt can be quickly sent to the central processing unit in the hard deadlock of the core through the normal central processing unit
For example, the target inter-core interrupt may be a simulated non-maskable interrupt, which may be referred to as a pseudo MNI type inter-core interrupt.
For an ARM chip, there may be situations where an unmasked interrupt cannot be implemented. In the embodiment of the application, the interrupt priority of the ARM controller simulates the unmasked interrupt, so that the simulated unmasked interrupt can be sent to the central processing unit with the occurrence of the kernel hard deadlock and received by the central processing unit with the occurrence of the kernel hard deadlock, and the reason of the kernel hard deadlock can be conveniently and subsequently positioned.
In the embodiment of the application, when the electronic equipment determines the reason causing the hard deadlock of the kernel, the value of the panic identifier can be detected; when the value of the panic identifier is a first value, controlling an operating system of the electronic equipment to enter a panic state; and when the value of the panic identifier is the second value, controlling the operating system of the electronic equipment to enter a panic state.
Illustratively, the first value may be 1 and the second value may be 0. Therefore, when the electronic device detects that the value of the panic identifier is 1, the operating system of the electronic device is controlled to enter the panic state, and when the electronic device detects that the value of the panic identifier is 0, the operating system of the electronic device is controlled not to enter the panic state.
Therefore, whether the operating system of the electronic equipment needs to enter the panic state or not is controlled through the value of the panic identifier, and when the operating system of the electronic equipment is controlled to enter the panic state, the influence of kernel hard deadlock on the operation of the operating system can be reduced.
The value of the panic identifier may be preset by a user, and when the user sets the value of the panic identifier, the electronic device may receive a preset value input by the user through the target interface, where the preset value includes a first value or a second value; and setting the value of the panic identifier to be a preset value.
The target interface may be a/proc/sys/kernel/arm_hardlock_panic interface, or may be another interface that may set a value of a panic identifier, which is not limited in the embodiments of the present application.
Therefore, the user can set the value of the panic identifier according to the actual situation of the electronic equipment used by the user, and the flexibility of whether the operating system enters the panic state or not when the kernel is hard deadlocked is improved.
In order to facilitate understanding of the method for detecting a kernel hard deadlock provided in the embodiment of the present application, a detailed description is given below, by way of a specific example, of the method for detecting a kernel hard deadlock listened to in the embodiment of the present application. Referring specifically to fig. 2, fig. 2 is a flow chart of another method for detecting a kernel hard deadlock according to an embodiment of the present application.
As shown in fig. 2, the method for detecting the kernel hard deadlock may include the following steps:
s201, starting an operating system.
In the embodiment of the present application, the config_arm64_pseudo_nmi configuration is enabled in the kernel of the electronic device, and irqchip. In this way, a function of simulating NMI interrupt by using GIC interrupt priority can be implemented.
For example, when the operating system is started, the kernel may also be started normally.
S202, registering inter-core interrupt of the pseudo NMI through a kernel function.
Illustratively, the inter-core interrupt of the pseudo NMI may be registered by a request_per_nmi kernel function.
S203, kernel hard deadlock detection.
For example, the electronic device may perform RCU ARM CPU stall detection to detect a kernel hard deadlock for a central processor in the electronic device.
The specific method for detecting the kernel hard deadlock can be referred to the above embodiments, and will not be described herein.
S204, judging whether the kernel hard deadlock is triggered or not.
When the kernel hard deadlock is not triggered, step S203 may be performed. When the core hard deadlock is triggered, it may be determined that there is a central processor for the core hard deadlock, and the following step S205 is performed,
s205, sending inter-core interrupt to the abnormal central processing unit through the normal central processing unit.
The exception central processor may be a central processor that has a core hard deadlock, and the normal processor may be a central processor that does not have a core hard deadlock. The inter-core interrupt may be an inter-core interrupt of a pseudo NMI registered through a kernel function.
S206, the abnormal central processing unit receives inter-core interrupt of the GIC pseudo NMI with high priority, backtracks the stack and positions the reasons of the hard deadlock of the kernel.
For example, the method for performing stack trace by the abnormal central processing unit and locating the cause of the kernel hard deadlock may be described in the above embodiment, which is not described herein.
S207, judging whether a user presets a value of the panic identifier.
By way of example, determining whether the value of the panic identifier is preset by the user may determine whether the value of the panic identifier is set by the user through the/proc/sys/kernel/arm_hardlock_panic interface, if so, the following step S208 may be executed, and if not, the step S203 may be executed.
It should be noted that, if the user sets the value of the panic identifier, the value of the panic identifier may be the first value described in the foregoing embodiment, and if the user does not set the value of the panic identifier, the value of the panic identifier may be the second value described in the foregoing embodiment.
S208, triggering the operating system to enter a panic state.
In summary, the embodiment of the present application uses the pseudo NMI interrupt function of the ARM chip to detect, by using the kernel hard deadlock detection mechanism, whether the central processor is in a kernel hard deadlock. When the kernel hard deadlock occurs, a pseudo NMI inter-kernel interrupt based on the high priority of the GIC can be sent to the abnormal central processor through the normal central processor, and stack backtracking can be carried out after the abnormal central processor receives the interrupt, so that the cause of the kernel hard deadlock can be rapidly positioned.
Fig. 3 is a schematic structural diagram of a device 30 for detecting a kernel deadlock according to an embodiment of the present application, for example, referring to fig. 3, the device 30 for detecting a kernel deadlock may include:
the sending module 301 is configured to send, when detecting that a first central processor of the plurality of central processors has a core hard deadlock, a pre-registered target inter-core interrupt to the first central processor through a second central processor, where the priority of the inter-core interrupt is higher than the priority of the inter-core interrupt received by the first central processor when the first central processor is operating normally, and the second central processor is any one of the central processors that does not have a core hard deadlock.
The processing module 302 is configured to receive, by using the first central processing unit, the target inter-core interrupt, and perform stack backtracking to obtain a stack backtracking result; and determining the reason for causing the hard deadlock of the kernel according to the stack backtracking result.
In one possible implementation, the stack trace result includes a plurality of function call information of the first central processor before the ARM core hard deadlock occurs; the processing module 302 is specifically configured to determine, from among the plurality of function call information, target function call information that causes a kernel hard deadlock.
In a possible implementation manner, the electronic device includes an ARM interrupt controller, and the apparatus further includes a registration module 303, where the registration module 303 is configured to register, when the electronic device is started, a target inter-core interrupt with a highest priority through a preset kernel function according to an interrupt priority of the ARM interrupt controller.
In one possible implementation, the target inter-core interrupt is a simulated unmasked interrupt.
In a possible implementation manner, the processing module 302 is further configured to detect, using a kernel deadlock detection mechanism, whether an exception occurs in a scheduling state and an interrupt receiving state of each of the plurality of central processing units; and when detecting that the scheduling state and the interrupt receiving state of the first central processing unit are abnormal, determining that the first central processing unit has kernel hard deadlock.
In a possible implementation manner, the processing module 302 is further configured to detect a value of the panic identifier; when the value of the panic identifier is a first value, controlling an operating system of the electronic equipment to enter a panic state; and when the value of the panic identifier is the second value, controlling the operating system of the electronic equipment to enter a panic state.
In a possible implementation manner, the processing module 302 is further configured to receive a preset value input by a user through the target interface, where the preset value includes a first value or a second value; and setting the value of the panic identifier to be a preset value.
The detection device for kernel deadlock provided by the embodiment of the application can execute the technical scheme of the detection method for kernel deadlock in any embodiment, and the implementation principle and beneficial effects of the detection device for kernel deadlock are similar to those of the detection method for kernel deadlock, and can be seen from the implementation principle and beneficial effects of the detection method for kernel deadlock, and are not repeated here.
Fig. 4 is a schematic structural diagram of an electronic device provided in the present application. As shown in fig. 4, the electronic device 400 may include: at least one processor 401 and a memory 402.
A memory 402 for storing a program. In particular, the program may include program code including computer-operating instructions.
Memory 402 may comprise high-speed RAM memory or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
The processor 401 is configured to execute computer-executable instructions stored in the memory 402, so as to implement the method for detecting a kernel deadlock described in the foregoing method embodiment. The processor 401 may be a central processing unit (Central Processing Unit, abbreviated as CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more integrated circuits configured to implement embodiments of the present application. Specifically, when the method for detecting the kernel deadlock described in the foregoing method embodiment is implemented, the electronic device may be, for example, an electronic device having a processing function, such as a terminal, a server, or the like. In implementing the method for detecting a kernel deadlock described in the foregoing method embodiment, the electronic device may be, for example, an electronic control unit on a vehicle.
Optionally, the electronic device 400 may also include a communication interface 403. In a specific implementation, if the communication interface 403, the memory 402, and the processor 401 are implemented independently, the communication interface 403, the memory 402, and the processor 401 may be connected to each other by a bus and perform communication with each other. The bus may be an industry standard architecture (Industry Standard Architecture, abbreviated ISA) bus, an external device interconnect (Peripheral Component, abbreviated PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated EISA) bus, among others. Buses may be divided into address buses, data buses, control buses, etc., but do not represent only one bus or one type of bus.
Alternatively, in a specific implementation, if the communication interface 403, the memory 402, and the processor 401 are integrated on a chip, the communication interface 403, the memory 402, and the processor 401 may complete communication through internal interfaces.
The present application also provides a computer-readable storage medium, which may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, etc., in which program codes may be stored, and in particular, the computer-readable storage medium stores program instructions for the methods in the above embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. The method for detecting the kernel deadlock is applied to electronic equipment, and the electronic equipment comprises an ARM chip and a plurality of central processing units, and is characterized by comprising the following steps:
when detecting that a first central processor in the plurality of central processors has a kernel hard deadlock, sending a pre-registered target inter-core interrupt to the first central processor through a second central processor, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the kernel hard deadlock;
receiving the target inter-core interrupt by the first central processing unit, and performing stack backtracking to obtain a stack backtracking result;
and determining the reason for causing the kernel hard deadlock according to the stack backtracking result.
2. The method of claim 1, wherein the stack trace result includes a plurality of function call information for the first central processor prior to occurrence of an ARM core hard deadlock;
the determining the reason of the ARM core hard deadlock according to the stack backtracking result comprises the following steps:
and determining target function call information causing the kernel hard deadlock from the plurality of function call information.
3. The method of claim 1, wherein the electronic device includes an ARM interrupt controller therein, the method further comprising:
when the electronic equipment is started, according to the interrupt priority of the ARM interrupt controller, registering the target inter-core interrupt with the highest priority through a preset kernel function.
4. A method according to claim 3, wherein the target inter-core interrupt is a simulated non-maskable interrupt.
5. The method according to claim 1, wherein the method further comprises:
detecting whether the scheduling state and the interrupt receiving state of each central processing unit in the plurality of central processing units are abnormal or not by using a kernel deadlock detection mechanism;
and when detecting that the scheduling state and the interrupt receiving state of the first central processing unit are abnormal, determining that the first central processing unit has kernel hard deadlock.
6. The method of any of claims 1-5, wherein in determining a cause of the kernel hard deadlock, the method further comprises:
detecting the value of the panic identifier;
when the value of the panic identifier is a first value, controlling an operating system of the electronic equipment to enter a panic state;
and when the value of the panic identifier is a second value, controlling an operating system of the electronic equipment to enter a panic state.
7. The method of claim 6, wherein the method further comprises:
receiving a preset value input by a user through a target interface, wherein the preset value comprises a first value or a second value;
and setting the value of the panic identifier as the preset value.
8. A device for detecting a core deadlock, comprising:
the sending module is used for sending a pre-registered target inter-core interrupt to a first central processor through a second central processor when detecting that the first central processor in the plurality of central processors has a core hard deadlock, wherein the priority of the inter-core interrupt is higher than that of the inter-core interrupt received by the first central processor when the first central processor works normally, and the second central processor is any one of the central processors which do not have the core hard deadlock;
the processing module is used for receiving the inter-target-core interrupt through the first central processing unit and carrying out stack backtracking to obtain a stack backtracking result; and determining the reason for causing the kernel hard deadlock according to the stack backtracking result.
9. An electronic device comprising a memory and a processor; wherein,
the memory is used for storing a computer program;
the processor is configured to read a computer program stored in the memory, and execute a method for detecting a kernel deadlock according to any of the preceding claims 1-7 according to the computer program in the memory.
10. A computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, which when executed by a processor, implement a method for detecting a kernel deadlock according to any of the preceding claims 1-7.
CN202311483921.3A 2023-11-07 2023-11-07 Method and device for detecting kernel deadlock, electronic equipment and storage medium Pending CN117290119A (en)

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CN202311483921.3A CN117290119A (en) 2023-11-07 2023-11-07 Method and device for detecting kernel deadlock, electronic equipment and storage medium

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