CN117289781A - Main control module, chip low-power consumption control method, intelligent device and storage medium - Google Patents

Main control module, chip low-power consumption control method, intelligent device and storage medium Download PDF

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Publication number
CN117289781A
CN117289781A CN202210680728.8A CN202210680728A CN117289781A CN 117289781 A CN117289781 A CN 117289781A CN 202210680728 A CN202210680728 A CN 202210680728A CN 117289781 A CN117289781 A CN 117289781A
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CN
China
Prior art keywords
main control
pin
chip
universal asynchronous
asynchronous receiver
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CN202210680728.8A
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Chinese (zh)
Inventor
杨建�
张武军
刘胜利
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GD Midea Air Conditioning Equipment Co Ltd
Foshan Shunde Midea Electric Science and Technology Co Ltd
Original Assignee
GD Midea Air Conditioning Equipment Co Ltd
Foshan Shunde Midea Electric Science and Technology Co Ltd
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Application filed by GD Midea Air Conditioning Equipment Co Ltd, Foshan Shunde Midea Electric Science and Technology Co Ltd filed Critical GD Midea Air Conditioning Equipment Co Ltd
Priority to CN202210680728.8A priority Critical patent/CN117289781A/en
Publication of CN117289781A publication Critical patent/CN117289781A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3265—Power saving in display device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU

Abstract

The invention discloses a main control module, a chip low-power consumption control method, intelligent equipment and a storage medium, wherein the main control module comprises the following components: a main control chip; the main control chip comprises a first universal asynchronous receiver/transmitter receiving pin, a first universal asynchronous receiver/transmitter transmitting pin and an external interrupt receiving pin; the first universal asynchronous receiver receiving pin and the first universal asynchronous receiver transmitting pin are respectively and electrically connected with a second universal asynchronous receiver transmitting pin and a second universal asynchronous receiver receiving pin of the display chip matched with the main control module, and the external interrupt receiving pin is connected between the first universal asynchronous receiver receiving pin and the second universal asynchronous receiver transmitting pin. By the master control module and the chip low-power consumption control method, the low-power consumption of the master control chip can be realized at extremely low cost, and compared with the existing low-power consumption scheme, the method is more energy-saving.

Description

Main control module, chip low-power consumption control method, intelligent device and storage medium
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a main control module, a chip low power consumption control method, an intelligent device, and a computer readable storage medium.
Background
With the development of the age and the progress of technology, more and more intelligent devices are becoming more popular in daily life of people, and smart phones, tablet computers, smart televisions, smart refrigerators, smart air conditioners and other devices become necessities of daily life, and power consumption (energy consumption) is a most concerned problem except performance and size of the intelligent devices.
In the prior art, besides the fact that the display bright screen has a very large influence on the power consumption of the intelligent device, after the display is turned off, the main control chip is often a hardware link with very high energy consumption ratio due to the fact that some system tasks are executed, the existing low-power-consumption scheme of the chip is high in implementation cost, support of devices such as a relay is often needed, and the actual requirement of a user on the low power consumption of the chip cannot be met.
Disclosure of Invention
The invention mainly aims to provide a main control module, a chip low-power consumption control method, intelligent equipment and a computer readable storage medium, and aims to solve the technical problem that the existing chip low-power consumption implementation cost is high.
In order to achieve the above object, the present invention provides a main control module, including:
a main control chip; the main control chip comprises a first universal asynchronous receiver/transmitter receiving pin, a first universal asynchronous receiver/transmitter transmitting pin and an external interrupt receiving pin; the first universal asynchronous receiver receiving pin and the first universal asynchronous receiver transmitting pin are respectively and electrically connected with a second universal asynchronous receiver transmitting pin and a second universal asynchronous receiver receiving pin of the display chip matched with the main control module, and the external interrupt receiving pin is connected between the first universal asynchronous receiver receiving pin and the second universal asynchronous receiver transmitting pin.
The main control module comprises a main control signal receiving wire and a main control signal transmitting wire; the first universal asynchronous receiver transceiver receiving pin is electrically connected with the second universal asynchronous receiver transceiver transmitting pin through the main control signal receiving lead; the first universal asynchronous receiver transmitter pin is electrically connected with the second universal asynchronous receiver transmitter receiver pin through the main control signal transmitting wire.
Optionally, the main control module comprises a signal shunt wire; one end of the signal shunt wire is electrically connected with the main control signal receiving wire, and the other end of the signal shunt wire is electrically connected with the external interrupt receiving pin; the external interrupt receiving pin and the first universal asynchronous receiver-transmitter receiving pin are adjacently arranged in the main control chip.
Optionally, the main control chip further includes a third universal asynchronous receiver/transmitter receiving pin and a third universal asynchronous receiver/transmitter transmitting pin, wherein the main control chip has a function of pin function conversion, and the third universal asynchronous receiver/transmitter receiving pin and the third universal asynchronous receiver/transmitter transmitting pin both belong to an INT pin.
In addition, in order to achieve the above purpose, the present invention also provides a chip low power consumption control method, where the chip low power consumption control method is applied to any one of the above main control modules; the chip low-power consumption control method comprises the following steps:
when receiving an input signal based on the receiving pin of the first universal asynchronous receiver-transmitter, judging whether the input signal belongs to a low-power-consumption instruction or not;
and if the input signal belongs to a low-power-consumption instruction, the main control chip enters a preset minimum power consumption mode.
Optionally, when receiving an input signal based on the first UART receiving pin, determining whether the input signal belongs to a low power instruction comprises
When receiving an input signal sent by a display connected with the main control module based on the receiving pin of the first universal asynchronous receiver/transmitter, detecting whether the input signal is a display shutdown signal;
when the input signal is a display shutdown signal, judging that the input signal belongs to a low-power consumption instruction; or (b)
And when the input signal is not the display shutdown signal, judging that the input signal does not belong to a low-power consumption instruction.
Optionally, after the step of the main control chip entering the preset minimum power consumption mode, the method further includes:
and receiving preset wake-up data based on the external interrupt receiving pin, and exiting the preset lowest power consumption mode by the main control chip.
Optionally, the step of the main control chip exiting the preset lowest power consumption mode includes:
and receiving preset wake-up data through the external interrupt receiving pin, and waking up the first universal asynchronous receiver-transmitter receiving pin and the first universal asynchronous receiver-transmitter transmitting pin of the main control chip so as to enable the main control chip to exit from a preset minimum power consumption mode.
In addition, in order to achieve the above object, the present invention also provides an intelligent device, which includes a processor, a memory, and a chip low power consumption control program stored on the memory and executable by the processor, wherein the chip low power consumption control program, when executed by the processor, implements the steps of the chip low power consumption control method as described above.
The invention also provides a computer readable storage medium, on which a chip low power consumption control program is stored, wherein the chip low power consumption control program, when executed by a processor, implements the steps of the chip low power consumption control method as described above.
The main control module in the technical scheme comprises a main control chip, an external interrupt receiving pin is independently arranged in the main control chip, and the external interrupt receiving pin is connected between the first universal asynchronous receiver-transmitter receiving pin and the second universal asynchronous receiver-transmitter transmitting pin, so that the main control chip can enter a preset lowest power consumption mode hardware condition and can wake up the main control chip timely and efficiently as required when a display or other external devices connected with the main control chip are shut down or dormant.
Drawings
Fig. 1 is a schematic diagram of a terminal structure of a hardware operating environment of an intelligent device according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a second embodiment of the main control module of the present invention;
FIG. 3 is a flowchart of a first embodiment of a chip low power consumption control method according to the present invention;
FIG. 4 is a flowchart of a second embodiment of a chip low power consumption control method according to the present invention;
FIG. 5 is a schematic diagram of an overall application flow of a display and a main control module according to the chip low power consumption control method of the present invention;
fig. 6 is a schematic diagram of a connection structure between a main control module and a display according to a first embodiment of the present invention;
fig. 7 is a schematic diagram of signal loss prevention effect related to the chip low power consumption control method of the present invention.
Figure 6 reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The technical scheme of the invention is as follows:
considering the traditional scheme of enabling the main control chip to enter low power consumption, one is to conduct power-off processing on the main control chip after a display or other equipment enters a power-off state in a mode of adding a relay, so that the main control chip is free of power supply support, and power is saved naturally. However, this relay solution involves significantly higher hardware costs. In addition, partial functions of the main control chip, such as a function of timing dormancy and awakening, are reserved, but the power consumption mode level which the main control chip can enter is low, and the main control chip repeatedly performs dormancy and awakening, so that the energy-saving effect of the main control chip under low power consumption is quite unsatisfactory. Moreover, both schemes have the condition of losing data signals during wake-up, which brings great loss and trouble to clients.
The method does not need to install a relay, has low hardware cost, can keep enough low power consumption (experimental data is 0.05W and is equivalent to power saving without electricity) when the main control chip enters low power consumption, and can avoid losing data when the main control chip is in low power consumption and is awakened. The main technical scheme adopted by the method is that an independent external interrupt receiving pin (external interrupt port) is arranged in a main control chip, and the external interrupt receiving pin is mounted on a main control signal receiving wire used for receiving signals of the main control chip and arranged between the main control chip and chips of other devices such as a display through an independent wire (signal shunt wire), so that the main control chip can enter a preset minimum power consumption mode and can be awakened from a low power consumption state, preset awakening data (specific data containing no useful information) is sent to the main control chip through other devices such as the display, and the main control chip is subjected to normal communication with the other devices such as the display after being awakened, and useful data information cannot be lost.
The embodiment of the invention provides intelligent equipment. The intelligent device may be any type of intelligent device such as an intelligent air conditioner, an intelligent refrigerator, an intelligent electric cooker, an intelligent television, an intelligent mobile phone, a tablet computer, a personal computer, etc., and is not limited herein.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a hardware running environment of an intelligent device according to an embodiment of the present invention.
As shown in fig. 1, the smart device may include: a processor 1001, such as a CPU, MCU (Microcontroller Unit, micro control unit), network interface 1004, user interface 1003, memory 1005, communication bus 1002. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display (Display), an input unit such as a control panel, and the optional user interface 1003 may also include a standard wired interface, a wireless interface. Network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., a WIFI interface). The memory 1005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above. A chip low power consumption control program may be included in the memory 1005 as a kind of computer storage medium.
Those skilled in the art will appreciate that the hardware configuration shown in fig. 1 does not constitute a limitation of the apparatus, and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.
With continued reference to fig. 1, the memory 1005 in fig. 1, which is a computer-readable storage medium, may include an operating system, a user interface module, a network communication module, and a chip low power consumption control program.
In fig. 1, the network communication module is mainly used for connecting with a server and performing data communication with the server; and the processor 1001 may call a chip low power consumption control program stored in the memory 1005 and perform the steps in the following respective embodiments.
In addition, it should be noted that the processor 1001 in the smart device may be a main control chip in the following embodiments.
Based on the hardware structure of the controller, various embodiments of the chip low-power consumption control method are provided.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a connection structure between a main control module and a display according to a first embodiment of the present invention.
The embodiment of the invention provides a main control module 1, wherein the main control module 1 comprises:
a main control chip 11; the main control chip 11 comprises a first universal asynchronous receiver/transmitter receiving pin 13, a first universal asynchronous receiver/transmitter pin 12 and an external interrupt receiving pin 14; the first universal asynchronous receiver pin 13 and the first universal asynchronous receiver pin 12 are electrically connected with a second universal asynchronous receiver pin 23 and a second universal asynchronous receiver pin 22 of the display chip 21 paired with the main control module 1, respectively, and the external interrupt receiving pin 14 is connected between the first universal asynchronous receiver pin 13 and the second universal asynchronous receiver pin 23.
In this embodiment, the main control chip 11 may be a chip such as an MCU or a CPU. The main control module 1 can be electrically connected with the display 2 through the communication connection lines 5 to form the intelligent device 100 in the invention, and the uppermost and the lowermost two communication connection lines 5 are shown in fig. 6. The main control chip 11 further comprises a main control communication interface 16, and the display 2 connected with the main control module 1 also comprises a display communication interface 24 corresponding to the main control communication interface 16. That is, specifically, the main control communication interface 16 is electrically connected to the display communication interface 24 through the communication connection line 5. The display 2 therein further comprises a display chip 21.
The main control chip 11 has an independent external interrupt receiving pin 14 (external interrupt port), the external interrupt port has the function of waking up any low power consumption mode of the chip at present, the main control chip 11 can enter the preset minimum power consumption mode in the invention after receiving the low power consumption instruction of the display 2 or other external devices through the external interrupt port, and can be successfully waken up in the mode, thereby not only ensuring that the chip reduces the use of electric energy for saving energy when in low power consumption, but also preventing the situation that the chip cannot be waken up due to the fact that the power and the voltage of the chip are too low in the preset minimum power consumption mode, because the main control chip 11 not only has the independent external interrupt receiving pin 14, but also connects the external interrupt receiving pin 14 between the first universal asynchronous transceiver receiving pin 13 and the second universal asynchronous transceiver transmitting pin 23, so any signal sent by the display 2 can be waken up in time as long as the main control chip 11 receives the signal sent by the display 2 through the external interrupt receiving pin 14.
Specifically, in one embodiment, the master control module 1 includes a master control signal receiving wire 3 and a master control signal transmitting wire 4; the first universal asynchronous receiver pin 13 is electrically connected with the second universal asynchronous receiver pin 23 through the main control signal receiving wire 3; the first universal asynchronous receiver transmitter pin 12 is electrically connected to the second universal asynchronous receiver pin 22 via the master signal transmission conductor 4.
It should be noted that, the main control signal receiving wire 3 and the main control signal transmitting wire 4 are named with the main control module 1 as a reference, that is, named with the signal transmission direction of the main control module 1 (the main control module 1 receives the signal or transmits the signal), and all belong to wires for transmitting the signal, which is not limited specifically herein.
The first universal asynchronous receiver/Transmitter receiving pin 13 is electrically connected with the second universal asynchronous receiver/Transmitter transmitting pin 23 through the main control signal receiving wire 3, and the first universal asynchronous receiver/Transmitter transmitting pin 12 is electrically connected with the second universal asynchronous receiver/Transmitter receiving pin 22 through the main control signal transmitting wire 4, that is, simply speaking, the UART (Universal Asynchronous Receiver/Transmitter) receiving port of the main control chip 11 is connected with the UART receiving port of the corresponding display chip 21, and the UART transmitting port of the main control chip 11 is connected with the UART receiving port of the display chip 21, thereby ensuring normal data interaction and stability of signal transmission between the main control module 1 and the display 2.
In another embodiment, the main control module 1 comprises a signal shunt wire 15; one end of the signal shunt wire 15 is electrically connected with the main control signal receiving wire 3, and the other end of the signal shunt wire 15 is electrically connected with the external interrupt receiving pin 14; the external interrupt receiving pin 14 is disposed in the main control chip 11 adjacent to the first universal asynchronous receiver transmitter receiving pin.
In this embodiment, the external interrupt receiving pin 14 and the universal asynchronous receiver/transmitter pin of the display chip 21 (the second universal asynchronous receiver/transmitter pin 23) can be connected in communication only by one signal shunt wire 15, and when the main control chip 11 is in a low power consumption state, the display 2 can transmit any wake-up signal transmitted by the universal asynchronous receiver/transmitter pin of the display chip 21 to the external interrupt receiving pin 14 sequentially through the main control signal receiving wire 3 and the signal shunt wire, so that the main control chip 11 can be woken up no matter how low the power of the main control chip 11 is, the connection structure is simple and stable, the cost is low, and the power consumption of the main control chip 11 is higher than that of the existing low power consumption mode (0.05 w in the preset minimum power consumption mode) can be realized.
In order to further improve the wake-up efficiency of the main control chip 11, the external interrupt receiving pin 14 is disposed adjacent to the first universal asynchronous receiver/transmitter receiving pin in the main control chip 11, so that the transmission distance from the universal asynchronous receiver/transmitter transmitting pin of the display chip 21 to the external interrupt receiving pin 14 is reduced, the corresponding signal loss is reduced, and the signal transmission speed is faster.
The main control module 1 in the technical scheme of the invention comprises a main control chip 11, and by independently arranging the external interrupt receiving pin 14 in the main control chip 11 and connecting the external interrupt receiving pin 14 with the first universal asynchronous receiver-transmitter receiving pin 13 and the second universal asynchronous receiver-transmitter pin 23, the main control chip 11 can enter a preset lowest power consumption mode hardware condition and can wake up the main control chip 11 timely and efficiently as required when the display 2 or other external devices connected with the main control module 1 are shut down or dormant.
Further, based on the above embodiment, a second embodiment of the present invention of the main control module 1 is proposed based on the above embodiment of the present invention, in this embodiment, the main control chip 11 further includes a third universal asynchronous receiver pin and a third universal asynchronous receiver transmitter pin, where the main control chip 11 has a function of pin function conversion and the third universal asynchronous receiver pin and the third universal asynchronous receiver transmitter pin both belong to an INT (input) pin;
referring to fig. 2, fig. 2 is a schematic flow chart of a second embodiment of the main control module according to the present invention. Wherein, the main control chip 11 is used for:
step S100, when an input low-power-consumption instruction is received, converting the receiving pin of the third universal asynchronous receiver-transmitter into an external interrupt receiving pin;
step S200, receiving preset wake-up data through the external interrupt receiving pin to enable the main control chip to start operation.
In the above embodiments, the method is mainly applicable to a main control chip without a pin function conversion function, that is, whether the main control chip has the pin function conversion function is not required to be considered.
In this embodiment, the corresponding main control chip has a pin function conversion function, so that the receiving pin of the universal asynchronous receiver-transmitter can be converted into an external interrupt pin. The function can be realized by software, and a universal asynchronous receiver-transmitter receiving pin and a universal asynchronous receiver-transmitter transmitting pin in the main control chip both belong to an INT pin.
When the main control chip needs to be awakened, the main control chip is enabled to exit the preset minimum power consumption mode by receiving preset awakening data sent by the display so as to start operation. The preset wake-up data may be strings of 0xff, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, etc.
Through this embodiment, can get into low-power consumption in order to save energy to main control chip with pin function conversion function to prevent through preset awakening data that main control chip loses data at the in-process of awakening, ensured the stability of communication between main control chip and the display.
Further, based on the above embodiment, a first embodiment of a chip low power consumption control method of the present invention is provided, in this embodiment, the chip low power consumption control method is applied to the above chip module, and the chip low power consumption control method includes the following steps:
step S10, when receiving an input signal based on the receiving pin of the first universal asynchronous receiver transmitter, judging whether the input signal belongs to a low-power-consumption instruction or not;
step S20, if the input signal belongs to a low power consumption instruction, the main control chip enters a preset minimum power consumption mode.
In this embodiment, on the basis of the communication connection between the main control module and the display, the main control chip can receive various input signals transmitted from the display chip in real time through the first universal asynchronous receiver/transmitter receiving pin, the main control chip also needs to identify the input signals in real time to perform corresponding processing, when the received input signals transmitted from the display are display shutdown signals, the input signals can be determined to be low-power-consumption instructions, the main control chip enters a preset minimum-power-consumption mode, under the preset minimum-power-consumption mode, the main control chip disconnects all loads and power supplies connected with the main control chip, because the connection with the power supplies is disconnected, the main control chip is in a state of stopping operation, and through a large number of test tests, the preset minimum-power-consumption mode can enable the main control chip to consume only 0.05w of power, so that the main control chip is quite energy-saving.
In one embodiment, the step S10 includes:
step a, when receiving an input signal sent by a display connected with the main control module based on the receiving pin of the first universal asynchronous receiver, detecting whether the input signal is a display shutdown signal;
b, when the input signal is a display shutdown signal, judging that the input signal belongs to a low-power consumption instruction; or (b)
And c, when the input signal is not a display shutdown signal, judging that the input signal does not belong to a low-power consumption instruction.
In this embodiment, the display sends a display shutdown signal to the main control module, the main control chip in the main control module enters the preset minimum power consumption mode, and signals sent by other displays to the main control module do not enable the main control chip to enter the preset minimum power consumption mode, so that false triggering of the preset minimum power consumption mode of the main control chip is prevented.
Further, referring to fig. 4, a second embodiment of the chip low power consumption control method according to the present invention is provided based on the above embodiment of the chip low power consumption control method according to the present invention, and in this embodiment, after the step S20, the method further includes:
step S30, based on the external interrupt receiving pin to receive preset wake-up data, the main control chip exits the preset lowest power consumption mode.
Specifically, the step S30 includes:
and d, receiving preset wake-up data through the external interrupt receiving pin, and waking up the first universal asynchronous receiver-transmitter receiving pin and the first universal asynchronous receiver-transmitter transmitting pin of the main control chip so as to enable the main control chip to exit from a preset minimum power consumption mode.
When the main control module enters a preset minimum power consumption mode, the display can send preset wake-up data to the main control module, and the preset wake-up data sequentially pass through the main control signal receiving lead and the signal shunt lead to an external interrupt pin of the main control chip, so that the main control chip exits the minimum power consumption mode. Wherein the preset wake-up data here includes any one of 0xff, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, and 0x7 f. The wake-up data are not transmitted with any useful information and are only used for waking up the main control chip, after the main control chip receives any wake-up data through the external interrupt receiving pin, the first universal asynchronous receiver-transmitter receiving pin of the main control chip and the first universal asynchronous receiver-transmitter pin start to operate, and then the main control chip is completely waken up, and the main control module starts to normally communicate with the display, so that the communication between the main control chip and the display is ensured not to lose data. In the existing scheme, the main control chip is usually awakened by some data with information content between the main control module and the display, namely, the data with substantial information content is directly transmitted to the main control chip when the display tries to communicate with the main control module, so that the data is naturally used for awakening by the main control chip, and the data is easily discarded by the main control chip, and even the communication between the subsequent display and the main control module is affected.
Referring to fig. 7, fig. 7 is a schematic diagram showing the signal loss preventing effect related to the chip low power consumption control method of the present invention, and as can be seen from fig. 7, the display sends 0xff data first to wake up the main control chip from low power consumption, so that some effective communication data contents generated by the subsequent display are not lost by the main control chip, and the reliability and stability of communication between the display and the main control chip are ensured.
In order to further understand the present invention and the above embodiments, please refer to fig. 5, fig. 5 is a schematic diagram of an overall application flow of a display and a main control module related to the chip low power consumption control method of the present invention;
as shown in the figure, the left side of fig. 5 is a flow step executed by the execution subject using the display (display), and the right side of fig. 5 is a flow step executed by the execution subject using the master (master module or master chip). The main control module can send signals to the display through UART (universal asynchronous receiver transmitter) communication, wherein the signals comprise signals that the main control module has entered into low power consumption. The display can send a signal to the main control module through UART communication, wherein the signal comprises a wake-up signal, the wake-up signal comprises preset wake-up data, in the process of waking up the main control module through the display, one data 0xff is sent first for quickly waking up the main control module, then other data are sent next, the other data are necessary information transmitted between the display and the main control module, and the data 0xff are only used for waking up the main control module and do not transmit any essential information.
The flow steps executed by the display as the execution subject on the left side of fig. 5 are described as follows: firstly judging whether the display (display) is powered off or not, if the display is not powered off, namely, powering on, sending a command of exiting low power consumption to a main control module in a UART communication mode, and simultaneously continuously detecting and judging whether the display is powered off or not in real time; in addition, if the display is shut down at this time, the display is ready for the chip to enter low power consumption, and a command (display shutdown signal) entering the low power consumption is sent to the main control module in a UART communication mode, so as to judge whether a reply (reply signal entering a preset minimum power consumption mode) entering the low power consumption (preset minimum power consumption mode) of the main control is received or not, and if the reply is not received by the display, the low power consumption command can be repeatedly sent to the main control module; if the display receives the reply, stopping sending any command to the main control module, and entering a low power consumption mode corresponding to the main control module (unless the operation is performed manually, the display does not need to send a signal command to the main control module), further judging whether the trigger of the case is received or not, so as to exit the low power consumption, namely, a user touches a key in the display to start the display, and the display sends preset wake-up data to the main control module at the same time of starting.
The flow steps executed by the main control module or the main control chip as the execution body on the right side of fig. 5 are described as follows: firstly, judging whether a main control module receives a low power consumption request (preset wake-up data) sent by a display, and if the main control module does not receive the low power consumption request sent by the display, continuing to judge the main control module; if the low power consumption request sent by the display is received, judging whether the main control module meets the requirement (condition) of entering low power consumption, if yes, entering a preset minimum power consumption mode by the main control module, after the main control module enters the low power consumption mode, judging whether the main control module receives a wake-up low power waveform (signal containing preset wake-up data) of the display, if the main control module receives the preset wake-up data sent by the display, the main control module is awakened by the preset wake-up data through an external interrupt (external interrupt receiving pin) of an IO port and exits the low power consumption mode, and then receiving signals of the display or other devices through an UART (universal asynchronous receiver/transmitter receiving pin, including the first universal asynchronous receiver receiving pin or the third universal asynchronous receiver/transmitter receiving pin) of the first universal asynchronous receiver, and if the signals are the low power consumption request including a shutdown signal of the display, the main control module can enter the preset minimum power consumption mode again.
Furthermore, the invention also provides a computer readable storage medium. The computer readable storage medium of the present invention stores a chip low power consumption control program, wherein the chip low power consumption control program realizes the steps of the chip low power consumption control method described above when executed by a processor.
The method implemented when the chip low power consumption control program is executed may refer to various embodiments of the chip low power consumption control method of the present invention, which will not be described herein.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.

Claims (10)

1. A master control module, characterized in that the master control module comprises:
a main control chip; the main control chip comprises a first universal asynchronous receiver/transmitter receiving pin, a first universal asynchronous receiver/transmitter transmitting pin and an external interrupt receiving pin; the first universal asynchronous receiver receiving pin and the first universal asynchronous receiver transmitting pin are respectively and electrically connected with a second universal asynchronous receiver transmitting pin and a second universal asynchronous receiver receiving pin of the display chip matched with the main control module, and the external interrupt receiving pin is connected between the first universal asynchronous receiver receiving pin and the second universal asynchronous receiver transmitting pin.
2. The master control module of claim 1, wherein the master control module comprises a master control signal receiving conductor and a master control signal transmitting conductor; the first universal asynchronous receiver transceiver receiving pin is electrically connected with the second universal asynchronous receiver transceiver transmitting pin through the main control signal receiving lead; the first universal asynchronous receiver transmitter pin is electrically connected with the second universal asynchronous receiver transmitter receiver pin through the main control signal transmitting wire.
3. The master control module of claim 2, wherein the master control module comprises a signal shunt wire; one end of the signal shunt wire is electrically connected with the main control signal receiving wire, and the other end of the signal shunt wire is electrically connected with the external interrupt receiving pin; the external interrupt receiving pin and the first universal asynchronous receiver-transmitter receiving pin are adjacently arranged in the main control chip.
4. The master control module of claim 1, wherein the master control chip further comprises a third universal asynchronous receiver pin and a third universal asynchronous receiver transmit pin, wherein the master control chip has a function of pin function conversion and the third universal asynchronous receiver receive pin and the third universal asynchronous receiver transmit pin both belong to an INT pin.
5. A chip low power consumption control method, wherein the chip low power consumption control method is applied to the main control module according to any one of claims 1 to 4; the chip low-power consumption control method comprises the following steps:
when receiving an input signal based on the receiving pin of the first universal asynchronous receiver-transmitter, judging whether the input signal belongs to a low-power-consumption instruction or not;
and if the input signal belongs to a low-power-consumption instruction, the main control chip enters a preset minimum power consumption mode.
6. The method of claim 5, wherein the step of determining whether the input signal belongs to a low power instruction when the input signal is received based on the first UART receiving pin comprises
When receiving an input signal sent by a display connected with the main control module based on the receiving pin of the first universal asynchronous receiver/transmitter, detecting whether the input signal is a display shutdown signal;
when the input signal is a display shutdown signal, judging that the input signal belongs to a low-power consumption instruction; or (b)
And when the input signal is not the display shutdown signal, judging that the input signal does not belong to a low-power consumption instruction.
7. The method for controlling low power consumption of a chip as claimed in claim 5, wherein after the step of the main control chip entering the preset minimum power consumption mode, the method further comprises:
and receiving preset wake-up data based on the external interrupt receiving pin, and exiting the preset lowest power consumption mode by the main control chip.
8. The chip low power consumption control method as claimed in claim 7, wherein the step of the main control chip exiting the preset minimum power consumption mode includes:
and receiving preset wake-up data through the external interrupt receiving pin, and waking up the first universal asynchronous receiver-transmitter receiving pin and the first universal asynchronous receiver-transmitter transmitting pin of the main control chip so as to enable the main control chip to exit from a preset minimum power consumption mode.
9. A smart device comprising a processor, a memory, and a chip low power control program stored on the memory that is executable by the processor, wherein the chip low power control program, when executed by the processor, implements the steps of the chip low power control method of any of claims 5 to 8.
10. A computer-readable storage medium, wherein a chip low power consumption control program is stored on the computer-readable storage medium, wherein the chip low power consumption control program, when executed by a processor, implements the steps of the chip low power consumption control method according to any one of claims 5 to 8.
CN202210680728.8A 2022-06-16 2022-06-16 Main control module, chip low-power consumption control method, intelligent device and storage medium Pending CN117289781A (en)

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CN202210680728.8A CN117289781A (en) 2022-06-16 2022-06-16 Main control module, chip low-power consumption control method, intelligent device and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210680728.8A CN117289781A (en) 2022-06-16 2022-06-16 Main control module, chip low-power consumption control method, intelligent device and storage medium

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CN117289781A true CN117289781A (en) 2023-12-26

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