CN117280225A

CN117280225A - Scan chain design method, device and chip

Info

Publication number: CN117280225A
Application number: CN202180097844.0A
Authority: CN
Inventors: 魏连志; 李鹏举
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-07-12
Filing date: 2021-07-12
Publication date: 2023-12-22
Also published as: WO2023283774A1

Abstract

A scan chain design method, a device and a chip relate to the field of chips, and can effectively improve the diagnosis precision of a scan chain by adjusting the structure of the scan chain. The specific scheme is as follows: acquiring an initial scan chain structure for indicating a connection relation between a plurality of scan chains and combinational logic, and determining a scan chain in which a first fan-in scan register corresponding to a first scan register in a first scan chain is located based on the initial scan chain structure, wherein the first fan-in scan register is a scan register of the fan-in first scan register; the first fan-in scan register is swapped with a second scan register in the second scan chain if the scan chain in which the first fan-in scan register is located is the same as the scan chain in which the first scan register is located.

Description

Scan chain design method, device and chip

Technical Field

The embodiment of the application relates to the field of chips, in particular to a scan chain design method, a device and a chip.

Background

With the development of semiconductor technology, logic inside a chip is more and more complex, and in order to improve the quality of the chip, the chip is generally tested when the chip leaves a factory. In the field of chip testing, a Scan Chain may be used to detect faults on shift register chains in a chip.

When the chip is tested by adopting the Scan Chain, one or more Scan Chain can be observed through the Scan Chain test vector, and if the observed output value of the Scan Chain is different from the ideal output value, the Scan Chain is determined to be faulty. To improve scan chain diagnostic accuracy (Chain Diagnosis Resolution, CDR) of chip testing, one approach is to increase the CDR by adding logic test vectors so that a scan chain failure can be observed by more logic test vectors. However, this method will increase the test time of the chip and the test cost is high. Another approach is to add more test circuits in the chip, so that the Scan Chain fault has more propagation paths, thereby increasing the CDR. However, this method increases the area of the chip and is costly.

Disclosure of Invention

The embodiment of the application provides a scan chain design method, a device and a chip, which can improve the diagnosis precision of a scan chain by adjusting the structure of the scan chain.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect of an embodiment of the present application, a scan chain design method is provided, including: first, an initial scan chain structure indicating a connection relationship between a plurality of scan chains and combinational logic is acquired, each scan chain may include a plurality of scan registers serially cascaded; secondly, determining a scanning chain where a first fan-in scanning register corresponding to a first scanning register in a first scanning chain is located based on an initial scanning chain structure; the first scan chain is any one of a plurality of scan chains, and the first fan-in scan register is a scan register of the fan-in first scan register; then, under the condition that the scan chain where the first fan-in scan register is located is the same as the scan chain where the first scan register is located, exchanging the first fan-in scan register with a second scan register in the second scan chain; the plurality of scan chains includes a second scan chain.

Based on the scheme, when the first fan-in scanning register and the first scanning register are positioned in the same scanning chain, and the scanning register with a fault exists in the first scanning chain, the fault value of the fault scanning register is likely to influence the observed value of the first fan-in scanning register, so that the diagnosis precision of the scanning chain is lower. Therefore, under the condition that the first scanning register and the first fan-in scanning register corresponding to the first scanning register are located in the same scanning chain, the influence of other fault scanning registers in the first scanning chain on the first fan-in scanning register can be reduced to a certain extent by exchanging the first fan-in scanning register with the second scanning register, different observation values generated by the first fan-in scanning register are facilitated, and therefore the range of the fault scanning register can be reduced, and the diagnosis precision of the scanning chain is improved. And when failure analysis is performed based on the diagnosis result with higher precision, the difficulty of failure analysis can be reduced, the improvement of the chip manufacturing process is facilitated, and the improvement of the chip yield is facilitated. It can be understood that, the scan chain design method provided by the embodiment of the application improves the diagnosis precision of the scan chain by adjusting the scan chain structure, and compared with the prior art that more test circuits are added in the chip, the scheme does not need to additionally increase the test circuits, and can improve the diagnosis precision of the scan chain, so that the scheme can not increase the area of the chip and has lower cost. Compared with the prior art, the method has the advantages that the logic test vector is not required to be added, so that the diagnosis precision of the scanning chain can be improved, the test time can be saved, and the test cost can be reduced.

In one possible implementation, the second scan chain and the first scan chain are different scan chains.

Based on the scheme, when the first fan-in scanning register and the first scanning register are positioned in the same scanning chain, and the scanning register with a fault exists in the first scanning chain, the fault value of the fault scanning register is likely to influence the observed value of the first fan-in scanning register, so that the diagnosis precision of the scanning chain is lower. When the first fan-in scanning register and the first scanning register are located in different scanning chains, the influence of other fault scanning registers in the first scanning chain on the first fan-in scanning register can be reduced, different observation values of the first fan-in scanning register can be generated, the range of the fault scanning register can be reduced, and the diagnosis precision of the scanning chain is improved. Therefore, under the condition that the first scanning register and the first fan-in scanning register corresponding to the first scanning register are located in the same scanning chain, the first scanning register and the first fan-in scanning register corresponding to the first scanning register are respectively located in different scanning chains by exchanging the first fan-in scanning register with the second scanning register in the other scanning chain, so that when a fault scanning unit is detected based on the scanning chain after exchanging the scanning registers, the influence of the fault scanning register in the first scanning chain on the fan-in scanning register can be reduced, and the diagnosis precision of the scanning chain is improved.

In one possible implementation manner, the second scan chain and the first scan chain are the same scan chain; before the first fan-in scan register is exchanged with a second scan register in the second scan chain, the first scan register is closer to the shift input end of the first scan chain than the first fan-in scan register, and the second scan register is a scan register in the first scan chain closer to the shift input end than the first scan register.

Based on the scheme, as the first fan-in scanning register is far away from the shift input end of the first scanning chain, if a scanning register in the first scanning chain, which is closer to the shift input end than the first fan-in scanning register, fails, the failure value of the failure scanning register can influence the observed value of the first fan-in scanning register, so that the diagnosis precision of the scanning chain is lower. When the first fan-in scanning register is closer to the shift input end of the first scanning chain, the influence of other fault scanning registers in the first scanning chain on the first fan-in scanning register can be reduced, different observation values of the first fan-in scanning register can be generated, the range of the fault scanning register can be reduced, and the diagnosis precision of the scanning chain is improved. Therefore, under the condition that the first scanning register and the first fan-in scanning register corresponding to the first scanning register are located in the same scanning chain, and the first scanning register is closer to the shift input end of the first scanning chain than the first fan-in scanning register corresponding to the first scanning register, the first fan-in scanning register is exchanged with the second scanning register which is close to the shift input end of the second scanning chain in the second scanning chain, so that the first fan-in scanning register is closer to the shift input end of the second scanning chain than other scanning registers, and the influence of the fault scanning register in the first scanning chain on the fan-in scanning register can be reduced when the fault scanning unit is detected based on the scanning chain after the exchange of the scanning registers, and the diagnosis precision of the scanning chain is improved.

In one possible implementation manner, the initial scan chain structure includes a plurality of compression channels, and each compression channel includes at least two scan chains with shift output ends for performing logic operation, and the method further includes: in case the compression channel in which the second scan chain is located is the same as the compression channel in which the first scan chain is located, the second scan chain is swapped with a third scan chain in another compression channel.

Based on this scheme, because first fan-in scan register and first scan register are located when the same compression passageway, the couplability between first scan register and the first fan-in scan register is stronger in this compression passageway, and if first fan-in scan register breaks down, the trouble value of this first fan-in scan register probably can influence the numerical value that first scan register caught, and then influences the output value of this compression passageway, leads to unable differentiation trouble scan register, causes the diagnosis precision of scan chain lower. Under the condition that the compression channels where the second scan chain and the first scan chain are located are the same, the first scan register and the first fan-in scan register are arranged in different compression channels, so that when a fault scan unit is detected based on the compression channels after the scan chains are exchanged, the coupling among a plurality of scan chains in the same compression channel can be reduced, and the diagnosis precision of the scan chains is improved.

In one possible implementation, the method further includes: determining a capture probability for each scan register in the first scan chain; the capture probability of each scan register is used to indicate the probability that the scan register captures a 0 or 1; and under the condition that the capturing probabilities of two adjacent scanning registers in the first scanning chain are all larger than a preset threshold value, or the capturing probabilities of two adjacent scanning registers in the first scanning chain are smaller than or equal to the preset threshold value, adjusting the connection relation among a plurality of scanning registers in the first scanning chain so that the capturing probability of one scanning register in the two adjacent scanning registers is larger than the preset threshold value, and the capturing probability of the other scanning register is smaller than or equal to the preset threshold value.

Based on the scheme, when the values captured by the adjacent scan registers in the scan chain are the same, in the scan chain diagnosis stage, the specific scan register fault is not easy to locate. According to the scheme, the capturing probability of each scanning register in the first scanning chain is determined, when the probability that two adjacent scanning registers in the first scanning chain capture the same value is high, the connection relation among the plurality of scanning registers in the first scanning chain is adjusted, so that the probability that the two adjacent scanning registers capture different values is high, and therefore when the fault scanning registers are detected based on the scanning chain after the connection relation is adjusted, the fault scanning registers can be determined more easily, and the diagnosis precision of the scanning chain is improved.

In a second aspect of the embodiments of the present application, a scan chain design method is provided, including: acquiring an initial scan chain structure for indicating a connection relationship between a plurality of scan chains and combinational logic; the initial scan chain structure comprises a plurality of compression channels, each compression channel comprises at least two scan chains, logic operation is carried out between shift output ends of at least two scan chains in each compression channel, and each scan chain comprises a plurality of scan registers; determining a scanning chain where a first fan-in scanning register corresponding to a first scanning register in a first scanning chain is located based on an initial scanning chain structure; the first fan-in scanning register is a scanning register of the fan-in first scanning register, the first scanning chain is any one scanning chain of a plurality of scanning chains, the scanning chain where the first fan-in scanning register is located is a second scanning chain, and the plurality of scanning chains comprise the second scanning chain; in the case where the compression channels in which the first scan chain and the second scan chain are located are the same, the second scan chain is swapped with the third scan chain in the other compression channel.

In one possible implementation manner, the method further includes: determining a capture probability for each scan register in the first scan chain; the capture probability of each scan register is used to indicate the probability that the scan register captures a 0 or 1; and under the condition that the capturing probabilities of two adjacent scanning registers in the first scanning chain are smaller than or equal to a preset threshold value, adjusting the connection relation among a plurality of scanning registers in the first scanning chain so that the capturing probability of one scanning register in the two adjacent scanning registers is larger than the preset threshold value, and the capturing probability of the other scanning register is smaller than or equal to the preset threshold value.

The effect descriptions of the second aspect may refer to the effect descriptions of the first aspect, and are not repeated herein.

In a third aspect of the embodiments, a chip is provided that includes a first scan chain and a second scan chain, the first scan chain and the second scan chain being different scan chains, a first scan register in the first scan chain fanning into a second scan register in the second scan chain.

Based on the scheme, the second scanning register and the corresponding fan-in scanning register (first scanning register) are respectively arranged on different scanning chains, so that the influence of the fault scanning register in the first scanning chain on the fan-in scanning register can be reduced, and the diagnosis precision of the scanning chain can be improved when the fault scanning unit is detected based on the scanning chain structure.

In one possible implementation manner, the first scan chain and the second scan chain are scan chains in different compression channels; the compression channel comprises at least two scan chains, and logic operation is performed between shift output ends of at least two scan chains in the compression channel.

Based on the scheme, the second scanning register and the corresponding fan-in scanning register (first scanning register) are respectively arranged in different compression channels, so that when a fault scanning unit is detected based on the scanning chain structure, the coupling among a plurality of scanning chains in the same compression channel can be reduced, and the diagnosis precision of the scanning chains is improved.

In one possible implementation manner, in two adjacent scan registers in the first scan chain, the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to the preset threshold.

Based on this scheme, through setting up two scan registers that capture different numerical value likelihood is great as adjacent scan register to when detecting the trouble scan register based on this scan chain, can confirm the scan register of trouble more easily, promote the diagnosis precision of scan chain.

In a fourth aspect of embodiments of the present application, a chip is provided that includes a first scan chain, a first scan register in the first scan chain fanned into a second scan register in the first scan chain, the first scan register being closer to a shift input of the first scan chain than the second scan register.

Based on the scheme, the fan-in scanning register (the first scanning register) is arranged at the shift input end which is closer to the first scanning chain than the second scanning register, so that the influence of the fault scanning register in the first scanning chain on the fan-in scanning register can be reduced, and the diagnosis precision of the scanning chain can be improved when the fault scanning unit is detected based on the scanning chain structure.

In a fifth aspect of embodiments of the present application, there is provided a scan chain design apparatus comprising a processor and a memory for storing a computer program; the processor is configured to execute the computer program to cause the electronic device to perform the method of the first aspect or the second aspect.

In a sixth aspect of embodiments of the present application, a chip is provided, where the chip includes a processor and an interface circuit, where the processor is configured to communicate with other devices through the interface circuit to implement the method in the first aspect or the second aspect.

In a seventh aspect of embodiments of the present application, there is provided a computer readable storage medium having stored therein computer program code which, when run on a processor, causes the processor to perform the method of the first or second aspect described above.

An eighth aspect of the embodiments of the present application provides a computer program product storing computer software instructions for execution by the processor described above, the computer software instructions comprising a program for performing the aspects of the first or second aspects described above.

Drawings

Fig. 1 is a schematic structural diagram of a general register and a scan register according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a scan chain according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an initial scan chain structure according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of a scan chain design method according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating an application of a scan chain design method according to an embodiment of the present application;

fig. 7 is a second application schematic diagram of a scan chain design method according to an embodiment of the present application;

fig. 8 is an application diagram III of a scan chain design method according to an embodiment of the present application;

fig. 9 is an application diagram of a scan chain design method according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another initial scan chain structure according to an embodiment of the present application;

FIG. 11 is a flowchart illustrating another scan chain design method according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another initial scan chain structure according to an embodiment of the present application;

fig. 13 is an application diagram of a scan chain design method according to an embodiment of the present application;

FIG. 14 is a flowchart of another scan chain design method according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram of another initial scan chain structure according to an embodiment of the present application;

fig. 16 is a sixth application schematic diagram of a scan chain design method according to an embodiment of the present application;

fig. 17 is a schematic diagram of a scan chain design apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b and c may be single or plural. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", and the like are used to distinguish the same item or similar items having substantially the same function and effect, and those skilled in the art will understand that the terms "first", "second", and the like do not limit the number and execution order. For example, "first" of the first scan registers and "second" of the second scan registers in the embodiments of the present application are used only to distinguish between different scan registers. The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order division is used, nor does it indicate that the number of the devices in the embodiments of the present application is particularly limited, and no limitation on the embodiments of the present application should be construed.

In this application, the terms "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

With the development of semiconductor technology, logic inside a chip is more and more complex, and in order to improve the quality of the chip, the chip is generally tested when the chip leaves the factory. In the field of chip testing, a Scan Chain may be used to detect faults on shift register chains in a chip. The scan chain may be comprised of a plurality of scan registers serially cascaded.

First, the concept of a scan register is explained. Fig. 1 (a) is a schematic diagram of a general register, and as shown in fig. 1 (a), the register includes a data input terminal D, a clock input terminal CLK, a data output terminal Q, and a data output terminal QN. The clock valid edge of the clock input of the register may be a rising edge or a falling edge. Taking the clock active edge of the register as a rising edge as an example, when the clock input terminal changes from low level to high level, the register samples the data input terminal D and sends the sampled value to the data output terminal Q. The data output Q maintains the original sample value until the clock input is changed from low to high for the second time when the clock input is otherwise. The data output terminal QN is the data output terminal Q inverted.

Fig. 1 (b) is a schematic diagram of a scan register, in which a selector (MUX) is added, compared with the normal register shown in fig. 1 (a). As shown in (b) of fig. 1, the scan register includes a logic data input D, a scan data input (SI), a Scan Enable (SE), a clock input CLK, a data output Q, and a data output QN. The selector MUX selects the input of the scan register as the logic data input D or the scan data input SI through the scan enable terminal SE. The output value of the scan register is related to the value of the scan enable SE when the clock active edge of the scan register arrives.

Alternatively, the scan register may have a value of the logic data input D when the scan enable SE is 0, and a value of the scan data input SI when the scan enable SE is 1. Alternatively, the scan register may have a value of the logic data input D when the scan enable SE is 1, and a value of the scan data input SI when the scan enable SE is 0. The present application is not limited thereto, and the following embodiments will be described by taking the example in which the input of the scan register is the value of the logic data input terminal D when the scan enable terminal SE is 0, and the input of the scan register is the value of the scan data input terminal SI when the scan enable terminal SE is 1.

For example, taking the clock active edge of the scan register as a rising edge, when the scan enable terminal SE is 0, the scan register samples the logic data input terminal D and sends the sampled value to the data output terminal Q when the clock input terminal changes from low level to high level. In the case where the scan enable terminal SE is 1, when the clock input terminal is changed from a low level to a high level, the scan register samples the scan data input terminal SI and supplies the sampled value to the data output terminal Q.

Optionally, the logic data input D of any one of the scan registers (e.g., scan register 1) in the scan chain is adapted to be coupled to the output of the combinational logic, which is coupled to the outputs of the other scan registers (e.g., scan register 2 and scan register 3). The scan register 2 and the scan register 3 may be referred to as fan-in scan registers corresponding to the scan register 1, and the combinational logic may be referred to as fan-in combinational logic corresponding to the scan register 1. The specific number of fan-in scan registers and the specific operation manner of the fan-in combinational logic corresponding to each scan register are not limited in the embodiments of the present application.

Next, the concept of scan chain will be described. Fig. 2 is a schematic diagram of a scan chain, taking a scan chain including 3 scan registers as an example, as shown in fig. 2, a data output terminal Q of a previous scan register of two adjacent scan registers is coupled to a scan data input terminal SI of a next scan register, and when a scan enable terminal SE of each scan register is 1, the 3 scan registers shown in fig. 2 are connected end to form a scan chain.

The scan chain may be tested by automated test equipment (automatic test equipment, ATE) in testing whether the scan chain is malfunctioning. The ATE equipment controls a scanning enabling end SE of each scanning register in the scanning chain to be 1 according to the scanning chain test vector, so that a plurality of scanning registers in the scanning chain form a shift register. The ATE device observes the output value of the scan chain by inputting a scan chain test vector to the scan data input SI of the first scan register in the scan chain. And if the observed output value of the scan chain is different from the scan chain test vector, determining that the scan chain fails. The ATE equipment may also detect faulty scan cells (e.g., scan registers) in the scan chain based on the logic test vectors. In the diagnostic stage, the EDA tool or engineer diagnoses a faulty scan chain, and faulty scan cells in the scan chain, based on the detection results of the ATE equipment. Scan chain diagnostic accuracy (Chain Diagnosis Resolution, CDR) may generally be used to represent the diagnostic accuracy of a scan chain, with smaller CDRs representing higher diagnostic accuracy. For example, a minimum CDR value of 1 may be 1, which means that the diagnostic accuracy of the scan chain may be accurate to a unique scan register.

The following describes a method for detecting a faulty scan cell in a scan chain by ATE equipment according to a logical test vector in three stages.

Moving into a load stage: the ATE equipment controls a scanning enabling end SE of each scanning register in the scanning chain to be 1 according to the logic test vector, and a plurality of scanning registers in the scanning chain form a shift register. The ATE device inputs a logic test vector to the SI terminal of the first scan register in the scan chain, the value of which may be shifted into each scan register in the scan chain (i.e., the load phase may set an initial value for each scan register in the scan chain).

Capture phase: typically, the scan enable SE of each scan register in the capture stage scan chain is 0, the scan register is switched to a non-scan enable state (i.e., normal digital circuitry), and the logical data input D of each scan register captures a value from the fan-in combinational logic of that scan register. The capture stage may be considered as loading the value of the fault point into the scan registers, where the value captured by each scan register in the capture stage is the result of the load value and the fan-in combination logic operation of the fan-in scan register corresponding to the scan register in the load stage.

Shifting out the unloading stage: the scan enable end SE of each scan register in the scan chain is 1, a plurality of scan registers in the scan chain form a shift register, the value captured by each scan register in the capture stage is output in series, and the ATE equipment compares the output value with an ideal output value.

However, when the fault scan unit is tested according to the above three stages, the scan chain diagnostic accuracy CDR may be low because the coupling between the observation logic of the fault scan register and other scan registers on the fault scan chain is strong.

For example, taking a chip including two scan chains, namely, scan chain 1 and scan chain 2, scan chain 1 being a fault-free scan chain, scan registers C6 to C4 in scan chain 2 having ideal values {1 1} as an example, as shown in fig. 3, scan chain 1 includes scan registers Ca to Cg, and scan chain 2 includes scan registers C0 to C6. The scan registers corresponding to the scan register C4 in the scan chain 2 are the scan register C1 and the scan register C2 (i.e., the scan registers fanning into the scan register C4 are the scan register C1 and the scan register C2), and the scan registers corresponding to the scan register C5 are the scan register C2 and the scan register C3 (i.e., the scan registers fanning into the scan register C5 are the scan register C2 and the scan register C3). If only scan register C6 in scan chain 2 fails and a fixed fault 0 (stuck at 0, SA 0) occurs, the ATE equipment may detect the failed scan register in three stages (load stage, capture stage and unlock stage), taking the logic test vector input by scan chain 2 in load stage as {1 0 1 1 1 1 1}, the values of scan registers C6 to C0 are all 0 because scan register C6 exhibits SA 0. In the capture phase, the value captured by the scan register C4 is the value obtained by performing an exclusive or operation on the value 0 of the scan register C1 and the value 0 of the scan register C2, that is, the value captured by the scan register C4 is 0. The value captured by the scan register C5 is the value obtained by performing an and operation on the value 0 of the scan register C2 and the value 0 of the scan register C3, that is, the value captured by the scan register C5 is 0. Since the scan register C6 exhibits SA0, the output values of the scan registers C6, C5, C4 are {0 0} in the unloading phase. In the diagnostic phase, it is determined that the scan registers C6, C5, C4 may all fail by comparing the test results of the ATE equipment with ideal values, such as comparing the output values of the scan registers C6, C5, C4 to {0 0} and the ideal values of the scan registers C6, C5, C4 {1 }. However, in practice, the scan registers C5 and C4 do not fail, and the output value errors of the scan registers C5 and C4 are caused by the SA0 occurring in the scan register C6, so the scan chain structure shown in fig. 3 will result in lower accuracy of the scan chain diagnosis.

It will be appreciated that, since the SA0 occurring in the scan register C6 affects the values of the scan registers C1 to C3 in the load phase, which results in errors in the values captured by the scan registers C5 and C4 in the capture phase, and thus, the output values of the scan registers C5 and C4 are different from the ideal values, the coupling between the scan register C6 and the scan registers C1 to C3 in the scan chain 2 will result in lower scan chain diagnosis accuracy CDR when performing the fault diagnosis based on the scan chain shown in fig. 3.

One way to increase the CDR is to increase the CDR by adding logic test vectors so that a scan chain failure can be observed by more logic test vectors. However, this method will increase the test time of the chip and the test cost is high. Another approach is to add more test circuits in the chip so that the scan chain failure has more propagation paths, thereby increasing the CDR. However, this method increases the area of the chip and is costly.

In order to solve the problems of long test time, high test cost, large chip area and the like when the diagnosis precision of the scanning chain is improved in the prior art, the embodiment of the application provides a scanning chain design method, and the scanning chain structure designed based on the design method can effectively improve the diagnosis precision of the scanning chain when fault diagnosis is carried out, so that the difficulty of failure analysis can be reduced when failure analysis is carried out based on the diagnosis result, the improvement of a chip manufacturing process is facilitated, and the chip yield is improved. In addition, the scan chain design method provided by the embodiment of the application improves the diagnosis precision of the scan chain by adjusting the scan chain structure, and compared with the prior art, by adding more test circuits in the chip, the scan chain design method can improve the diagnosis precision of the scan chain without additionally adding the test circuits, so that the application does not increase the area of the chip and has lower cost. Compared with the prior art, the method has the advantages that the logic test vector is not required to be added, so that the diagnosis precision of the scanning chain can be improved, the test time can be saved, and the test cost can be reduced.

The scan chain design method provided in the embodiments of the present application may be performed by the electronic device shown in fig. 4, on which a design tool such as electronic design automation (electronic design automation, EDA) may be run, and the scan chain design method in the embodiments described below may be run in the EDA tool. As shown in fig. 4, the electronic device 400 includes at least one processor 401, memory 402, transceiver 403, and communication bus 404.

The following describes the components of the electronic device in detail with reference to fig. 4:

the processor 401 is a control center of the electronic device, and may be one processor or a collective term of a plurality of processing elements. For example, processor 401 is a central processing unit (central processing unit, CPU), but may also be an integrated circuit (application specific integrated circuit, ASIC), or one or more integrated circuits configured to implement embodiments of the present application, such as: one or more microprocessors (digital signal processor, DSPs), or one or more field programmable gate arrays (field programmable gate array, FPGAs).

Among other things, the processor 401 may perform various functions of the electronic device by running or executing software programs stored in the memory 402 and invoking data stored in the memory 402.

In a particular implementation, processor 401 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 4, as an embodiment.

In a particular implementation, as one embodiment, an electronic device may include multiple processors, such as processor 401 and processor 405 shown in FIG. 4. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more detection devices, circuitry, and/or processing cores for processing data (e.g., computer program instructions).

The memory 402 may be, but is not limited to, read-only memory (ROM) or other type of static storage device that can store static information and instructions, random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, but may also be electrically erasable programmable read-only memory (EEPROM), compact disc-read only memory (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 402 may be separate and coupled to the processor 401 via a communication bus 404. Memory 402 may also be integrated with processor 401.

The memory 402 is used for storing a software program for executing the scheme of the application, and the processor 401 controls the execution.

A transceiver 403 for communicating with other communication devices. Of course, the transceiver 403 may also be used to communicate with a communication network, such as ethernet, radio access network (radio access network, RAN), wireless local area network (wireless local area networks, WLAN), etc. The transceiver 403 may include a receiving unit to implement a receiving function and a transmitting unit to implement a transmitting function.

Communication bus 404 may be an industry standard architecture (industry standard architecture, ISA) bus, an external test device interconnect (peripheral component, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 4, but not only one bus or one type of bus.

The configuration of the electronic device shown in fig. 4 does not constitute a limitation of the electronic device, and in practical applications, the electronic device may include more or less components than illustrated, or may combine some components, or may be arranged with different components.

Referring to fig. 4, as shown in fig. 5, a scan chain design method according to an embodiment of the present application is provided, and the method includes the following steps:

s501, acquiring an initial scan chain structure.

The initial scan chain structure is used to indicate a connection relationship between a plurality of scan chains and combinational logic, each scan chain including a plurality of scan registers, the plurality of scan registers in each scan chain being serially cascaded.

Alternatively, the number of scan registers included in different scan chains may be the same or different, which is not limited in this embodiment of the present application.

By way of example, the initial scan chain structure may include: the scan chains include information such as an identification of a plurality of scan registers included in each of the plurality of scan chains, a connection relationship of the plurality of scan registers in each of the plurality of scan chains, an identification of a scan register that fans into each of the plurality of scan registers, and combinational logic that fans into each of the plurality of scan registers.

For example, taking an example in which the initial scan chain structure includes the scan chain structure shown in fig. 3, as shown in fig. 3, the initial scan structure includes the identifications of the scan registers Cg to Ca in the scan chain 1 and the connection relationship between the scan registers Cg to Ca. The identity of the scan registers C6 to C0 in the scan chain 2, and the connection relationship between the scan registers C6 to C0. The scan registers of the fan-in scan register C4 in the scan chain 2 are the scan register C1 and the scan register C2, and the logical operation of the fan-in scan register C4 is an exclusive-or operation, i.e. the input end of the exclusive-or operation is coupled to the output ends of the scan register C1 and the scan register C2, respectively, and the output end of the exclusive-or operation is coupled to the D end of the scan register C4. The scan registers of the fan-in scan register C5 in the scan chain 2 are the scan register C2 and the scan register C3, and the logical operation of the fan-in scan register C5 is an and operation, that is, the input end of the and operation is coupled to the output ends of the scan register C2 and the scan register C3, respectively, and the output end of the and operation is coupled to the D end of the scan register C5.

S502, determining a scan chain where a first fan-in scan register corresponding to a first scan register in a first scan chain is located based on an initial scan chain structure.

The first scan chain may be any one of a plurality of scan chains included in the initial scan chain structure. The first scan register may be any one of a plurality of scan registers included in the first scan chain.

The first fan-in scan register is a scan register that fans in the first scan register. Optionally, the number of the scan registers fanned into the first scan register may be one or more.

The scan chain in which the first fan-in scan register is located and the scan chain in which the first scan register is located may be the same scan chain or may be different scan chains. When the scan chain where the first fan-in scan register is located and the scan chain where the first scan register is located are the same scan chain, the first scan chain includes the first scan register and the first fan-in scan register. When the scan chain where the first fan-in scan register is located and the scan chain where the first scan register is located are different scan chains, the scan chain where the first fan-in scan register is located is a scan chain other than the first scan chain among the plurality of scan chains.

For example, as shown in fig. 3, taking the first scan chain as the scan chain 2, the first scan register as the scan register C4 as an example, the scan registers fanned into the scan register C4 are the scan register C1 and the scan register C2. Since the scan chain in which the scan registers C1 and C2 are located is the scan chain 2, the first scan register (scan register C4) is the same as the scan chain in which its corresponding first fan-in scan register (scan register C1 and scan register C2) is located.

As another example, as shown in fig. 3, taking the first scan chain as the scan chain 2, the first scan register as the scan register C5, and the scan registers fanned into the scan register C5 as the scan registers C2 and C3. Since the scan chain in which the scan registers C2 and C3 are located is the scan chain 2, the first scan register (scan register C5) is the same as the scan chain in which its corresponding first fan-in scan register (scan register C2 and scan register C3) is located.

S503, exchanging the first fan-in scanning register with a second scanning register in the second scanning chain when the scanning chain where the first fan-in scanning register is located is the first scanning chain.

Because the scan chain where the first scan register is located is the first scan chain, when the scan chain where the first fan-in scan register is located is the first scan chain, the scan chain where the first fan-in scan register is located is the same as the scan chain where the first scan register is located. That is, in the step S503, when the first scan register and the first fan-in scan register corresponding to the first scan register are in the same scan chain, the first fan-in scan register is swapped with the second scan register in the second scan chain.

Exchanging the first fan-in scan register with the second scan register in the second scan chain in step S503 may include two implementations, one implementation being to exchange the first fan-in scan register in the first scan chain with the second scan register in the other scan chain (the second scan chain) such that the first scan register and its corresponding first fan-in scan register are located in different scan chains. Another implementation is to swap the first fan-in scan register with a second scan register in the first scan chain that is closer to the shift input of the first scan chain such that the first fan-in scan register is closer to the shift input of the first scan chain. These two implementations are each described in detail below.

In a first implementation, the second scan chain and the first scan chain in step S503 are different scan chains.

For example, as shown in fig. 3, a first scan chain is taken as a scan chain 2, a second scan chain is taken as a scan chain 1, a first scan register is taken as a scan register C4 and a scan register C5 in the scan chain 2, and a second scan register is taken as an example of scan registers Cd, cc and Cb in the scan chain 1. The scan registers of the fan-in scan register C4 are scan registers C1 and C2, the scan registers of the fan-in scan register C5 are scan registers C2 and C3, and according to step S502, it can be determined that the scan chains where the scan registers C1, C2 and C3 are located are both scan chain 2, that is, the scan register C4 is the same as the scan chain where the corresponding fan-in scan registers C1 and C2 are located, and the scan register C5 is the same as the scan chain where the corresponding fan-in scan registers C2 and C3 are located. Therefore, the fan-in scan registers C1, C2 and C3 in the scan chain 2 can be exchanged with the scan registers Cb, cc and Cd in the scan chain 1, so that the scan register C4 and the corresponding fan-in scan registers C1 and C2 are respectively located in different scan chains, and the scan register C5 and the corresponding fan-in scan registers C2 and C3 are respectively located in different scan chains, thereby reducing the influence of the fault scan register in the scan chain 1 on the fan-in scan register and improving the diagnosis precision of the scan chain.

Optionally, in this implementation manner, when the first fan-in scan register and the second scan register are exchanged, only the connection relationship of the scan chains where the first fan-in scan register and the second scan register are located is changed, and the connection relationship of the combinational logic corresponding to the first fan-in scan register and the second scan register is not changed.

For example, when a first fan-in scan register in a first scan chain is exchanged with a second scan register in a second scan chain, an SI end and a Q end of the first fan-in scan register may be disconnected from the first scan chain, an SI end and a Q end of the second scan register may be disconnected from the second scan chain, the SI end and the Q end of the second scan register may be connected to the first scan chain, and the SI end and the Q end of the first fan-in scan register may be connected to the second scan chain, so that the first scan register and the corresponding fan-in scan register may be located in different scan chains.

For example, as shown in fig. 6 and 7, when the fan-in scan registers C1, C2, and C3 in the scan chain 2 (first scan chain) are swapped with the scan registers Cb, cc, and Cd (second scan registers) in the scan chain 1 (second scan chain), the SI end of the fan-in scan register C3 may be disconnected from the Q end of the scan register C4, the Q end of the fan-in scan register C1 may be disconnected from the SI end of the scan register C0, the SI end of the scan register Cd may be disconnected from the Q end of the scan register Ce, and the Q end of the scan register Cb may be disconnected from the SI end of the scan register Ca. The SI end of the fan-in scanning register C3 is connected with the Q end of the scanning register Ce, the Q end of the fan-in scanning register C1 is connected with the SI end of the scanning register Ca, the SI end of the scanning register Cd is connected with the Q end of the scanning register C4, and the Q end of the scanning register Cb is connected with the SI end of the scanning register C0. As shown in fig. 7, after the scan registers of scan chain 1 and scan chain 2 are exchanged, scan registers C6, C5, C4, cd, cc, cb, C0 in scan chain 2 are sequentially connected end to end, and scan registers Cg, cf, ce, C, C2, C1, ca in scan chain 1 are sequentially connected end to end. As can be seen from fig. 3, 6 and 7, when the fan-in scan registers C1, C2 and C3 in the scan chain 2 are exchanged with the scan registers Cb, cc and Cd in the scan chain 1, only the connection relationship of the scan chain is changed, and the connection relationship of the combinational logic corresponding to each scan register is not changed. That is, the logical operations of fanning in each scan register and the scan registers of fanning in each scan register remain unchanged before and after swapping the scan registers.

The reason why the scan chain diagnostic accuracy can be improved after changing the scan chain connection relationship will be described below with reference to fig. 7.

Taking the scan chain structure after exchanging the first fan-in scan register in the first scan chain with the second scan register in the second scan chain as shown in fig. 7, the ideal values of the scan registers C6 to C4 in the scan chain 2 are {1 1} as shown in fig. 7, if only the scan register C6 in the scan chain 2 fails and the scan register C6 has SA0, the ATE device can detect the failed scan register in three stages (load stage, capture stage and unlock stage), taking the logical test vector input by the load stage scan chain 1 as {1 0 1 1 1 1 1} as an example, and the values of the load stage fan-in scan registers C3 to C1 are {1 1 0}. In the capture phase, the value captured by the scan register C4 is the value obtained by performing an exclusive or operation on the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1. The value captured by the scan register C5 is the value obtained by performing an and operation on the value 1 of the scan register C2 and the value 1 of the scan register C3, that is, the value captured by the scan register C5 is 1. Thus, in the unloading phase, the output values of the scan registers C6, C5, C4 are { 0.1 }. In the diagnostic phase, the scan register that may fail may be determined to be scan register C6 by comparing the test results of the ATE equipment with ideal values, such as comparing the output values of scan registers C6, C5, C4 to {0 1 1} and the ideal values of scan registers C6, C5, C4 {1 1}.

It will be appreciated that, compared with the scan chain structure shown in fig. 3, since the scan register C4 and its corresponding fan-in scan registers C1 and C2 are respectively located in different scan chains and the scan register C5 and its corresponding fan-in scan registers C2 and C3 are respectively located in different scan chains in the scan chain structure shown in fig. 7, the load values of the fan-in scan registers C2 and C3 are not affected by SA0 of the scan register C6 in the load phase, so that the values captured by the scan register C4 and the scan register C5 are not affected by SA0 of the scan register C6 in the capture phase, by changing the value of the logic test vector of the scan chain 1, it is possible to more accurately determine that the scan register with the fault is the scan register C6, and the scan chain diagnostic accuracy is higher. In the scan chain structure shown in fig. 3, since the scan register C4 and its corresponding fan-in scan registers C1 and C2 are located in the same scan chain, and the scan register C5 and its corresponding fan-in scan registers C2 and C3 are located in the same scan chain, SA0 occurring in the scan register C6 affects the values of the scan registers C1 to C3 in the load stage, and the values of the scan registers C1 to C3 are all 0 regardless of the logic test vector input in the load stage, so that the values captured by the scan registers C5 and C4 in the capture stage are always 0, and thus the values output by the scan registers C6, C5 and C4 in the unlock stage are also always 0. This is compared with the ideal value {1 1} of the scan registers C6, C5, C4, and only the scan registers C6 to C4 may fail, and the scan register which cannot accurately determine the failure is the scan register C6, so the scan chain diagnosis accuracy is lower.

It should be noted that, when the first fan-in scan register and the first scan register are in the same scan chain (the first scan chain), the fault value of the fault scan register in the first scan chain may affect the observed value of the first fan-in scan register, resulting in lower diagnostic accuracy of the scan chain. When the first fan-in scanning register and the first scanning register are in different scanning chains, the influence of other fault scanning registers in the first scanning chain on the first fan-in scanning register can be reduced, different observation values can be generated by the first fan-in scanning register, the range of the fault scanning register can be reduced, and the diagnosis precision of the scanning chain is improved.

It can be appreciated that, in the method provided in the embodiment of the present application, when the first scan register and the first fan-in scan register corresponding to the first scan register are located in the same scan chain, the first fan-in scan register and the second scan register in another scan chain are exchanged, so that the first scan register and the first fan-in scan register corresponding to the first scan register are respectively located in different scan chains, and therefore, when detecting a fault scan unit based on the scan chain after exchanging the scan registers, the influence of the fault scan register in the first scan chain on the fan-in scan register can be reduced, and the diagnostic accuracy of the scan chain is improved.

In a second implementation, the second scan chain in step S503 is the same scan chain as the first scan chain, where the first scan register is closer to the shift input of the first scan chain than the first fan-in scan register before the first fan-in scan register is swapped with the second scan register, and the second scan register is a scan register in the first scan chain closer to the shift input than the first scan register. In other words, in the implementation manner, when the first scan register and the corresponding first fan-in scan register are located in the same scan chain, and the first scan register is closer to the shift input end of the first scan chain than the corresponding first fan-in scan register, the first fan-in scan register is exchanged with the second scan register in the first scan chain, which is closer to the shift input end of the first scan chain, so that the first fan-in scan register in the exchanged first scan chain is closer to the shift input end of the first scan chain than the first scan register.

Alternatively, the shift Input of the first scan chain may also be referred to as a Primary Input (Primary Input) of the first scan chain, where the shift Input of the first scan chain is a scan Input SI of a first scan register in the first scan chain. The shift output of the first scan chain may also be referred to as the Primary output (Primary on) of the first scan chain, which is the output of the last scan register in the first scan chain.

For example, as shown in fig. 3, taking the first scan chain as scan chain 2 as an example, the shift input of scan chain 2 is the SI end of the first scan register C6 in scan chain 2.

For example, as shown in fig. 3, taking the first scan chain as the scan chain 2, the first scan register is the scan register C4 and the scan register C5 in the scan chain 2, and the second scan register is the scan register C6 in the scan chain 2 as an example. Since scan register C4 is located in the same scan chain as its corresponding fan-in scan registers C1 and C2, scan register C5 is located in the same scan chain as its corresponding fan-in scan registers C2 and C3, and scan register C4 is closer to the shift input of scan chain 2 than its corresponding fan-in scan registers C1 and C2, scan register C5 is closer to the shift input of scan chain 2 than its corresponding fan-in scan registers C2 and C3. Therefore, the fan-in scan registers C1 to C3 in the scan chain 2 can be swapped with the scan register C6 in the scan chain 2 which is closer to the shift input end of the scan chain 2 than the scan register C4 and the scan register C5, so that the fan-in scan registers C1 to C3 in the scan chain 2 are closer to the shift input end of the scan chain 2, the influence of the fault scan register in the scan chain 2 on the fan-in scan register is reduced, and the scan chain diagnosis precision is improved.

Optionally, in this implementation, when the first fan-in scan register is exchanged with the second scan register, only the connection relationship of the plurality of scan registers in the first scan chain is changed, and the logic gate of the fan-in first scan register and the scan register of the fan-in first scan register are not changed.

For example, when the first fan-in scan register in the first scan chain is exchanged with the second scan register in the first scan chain, the SI end of the first fan-in scan register, the Q end of the first fan-in scan register, the SI end of the second scan register, and the Q end of the second scan register may be disconnected and reconnected in the first scan chain, so that the first fan-in scan register in the first scan chain is closer to the shift input end of the first scan chain than the first scan register.

For example, as shown in fig. 8 and 9, when the fan-in scan registers C1, C2, and C3 in the scan chain 2 are swapped with the scan register C6 (second scan register) near the shift input end in the scan chain 2, the SI end of the fan-in scan register C3 may be disconnected from the Q end of the scan register C4, the Q end of the fan-in scan register C1 may be disconnected from the SI end of the scan register C0, and the SI end of the scan register C6 may be disconnected from the input port of the scan chain 2. And the SI end of the fan-in scanning register C3 is connected with the input port of the scanning chain 2, the Q end of the fan-in scanning register C1 is connected with the SI end of the scanning register C6, and the Q end of the scanning register C4 is connected with the SI end of the scanning register C0. As shown in fig. 9, after the connection relations of the scan registers in the scan chain 2 are exchanged, the scan registers C3, C2, C1, C6, C5, C4, and C0 in the scan chain 2 are sequentially connected end to end. As can be seen from fig. 3, 8 and 9, when the fan-in scan registers C1, C2 and C3 in the scan chain 2 are exchanged with the scan register C6 in the scan chain 2, only the connection relationship between the plurality of scan registers in the scan chain 2 is changed, and the connection relationship of the combinational logic corresponding to each scan register is not changed. That is, the logical operations of fanning in each scan register and the scan registers of fanning in each scan register remain unchanged before and after swapping the scan registers.

Next, the reason why the scan chain diagnostic accuracy can be improved after changing the connection relationship between the first fan-in scan register and the second scan register in the first scan chain will be described with reference to fig. 9.

Taking the scan chain structure after exchanging the first fan-in scan register in the first scan chain with the second scan register in the first scan chain as shown in fig. 9, the ideal output values of the scan registers C6 to C4 in the scan chain 2 are {1 1} as shown in fig. 9, if only the scan register C6 in the scan chain 2 fails and the scan register C6 has SA0, the ATE device inputs the scan chain test vector {1 1 1 1 1 1 0} into the scan chain 2, and the output observation value of the scan chain 2 is {0 0 0 0 0 0 0}. The ATE device detects the faulty scan registers in three stages (load stage, capture stage, and unload stage), taking the example of the logical test vector input by the load stage scan chain 2 being {1 1 1 1 0 1 1}, the load stage fan-in scan registers C3 to C1 have a value of {1 0}. In the capture phase, the value captured by the scan register C4 is the value obtained by performing an exclusive or operation on the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1. The value captured by the scan register C5 is the value obtained by performing an and operation on the value 1 of the scan register C2 and the value 1 of the scan register C3, that is, the value captured by the scan register C5 is 1. Thus, in the unloading phase, the output values of the scan registers C6, C5, C4 are { 0.1 }. In the diagnostic phase, the scan register that may fail may be determined to be scan register C6 by comparing the test results of the ATE equipment with ideal values, such as comparing the output values of scan registers C6, C5, C4 to {0 1 1} and the ideal values of scan registers C6, C5, C4 {1 1}.

It will be appreciated that, compared to the scan chain structure shown in fig. 3, since the fan-in scan registers C1 to C3 are closer to the shift input of the scan chain 2 than the other scan registers in the scan chain 2 in the scan chain structure shown in fig. 9, the load values of the fan-in scan registers C1 to C3 are not affected by SA0 of the scan register C6 in the load phase, so that the values captured by the scan registers C4 and C5 are not affected by SA0 of the scan register C6 in the capture phase, and thus by changing the values of the logic test vectors of the scan chain 2, it is possible to more accurately determine that the failed scan register is the scan register C6, and the scan chain diagnostic accuracy is higher. In the scan chain structure shown in fig. 3, since the failed scan register C6 is closer to the shift input of the scan chain 2 than the fan-in scan registers C1 to C3, SA0 appearing in the scan register C6 affects the values of the scan registers C1 to C3 in the load stage, and the values of the scan registers C1 to C3 are 0 regardless of the logic test vectors input in the load stage, so that the values captured by the scan registers C5 and C4 in the capture stage are always 0, and thus the values output by the scan registers C6, C5 and C4 in the unlock stage are also always 0. Compared with the ideal value { 1} of the scan registers C6, C5, C4, the scan chain diagnosis method only can determine that the scan registers C6, C5, C4 are likely to fail, and the scan register which cannot accurately determine the failure is the scan register C6, so that the scan chain diagnosis precision is lower.

Optionally, in the case that the first scan register and the corresponding first fan-in scan register thereof are located in the same scan chain, and the first scan register is closer to the shift input end of the first scan chain than the corresponding first fan-in scan register thereof, if there is no second scan register between the shift input end of the first scan chain and the first scan register (i.e., the shift input end of the first scan chain is the SI end of the first scan register), the first fan-in scan register and the first scan register may be swapped, so that the first fan-in scan register in the swapped first scan chain is closer to the shift input end of the first scan chain than the first scan register.

It should be noted that, the farther the first fan-in scan register is from the shift input end of the first scan chain, if a scan register in the first scan chain that is closer to the shift input end than the first fan-in scan register fails, the failure value of the failure scan register may affect the observed value of the first fan-in scan register, resulting in lower diagnostic accuracy of the scan chain. When the first fan-in scanning register is closer to the shift input end of the first scanning chain, the influence of other fault scanning registers in the first scanning chain on the first fan-in scanning register can be reduced, different observation values of the first fan-in scanning register can be generated, the range of the fault scanning register can be reduced, and the diagnosis precision of the scanning chain is improved.

It can be appreciated that, in the method provided in the embodiment of the present application, when the first scan register and the first fan-in scan register corresponding to the first scan register are located in the same scan chain, and the first scan register is closer to the shift input end of the first scan chain than the first fan-in scan register corresponding to the first scan register, the first fan-in scan register is exchanged with the second scan register in the second scan chain, which is closer to the shift input end of the second scan chain than the other scan registers, so that when the scan chain after exchanging the scan registers detects the fault scan unit, the influence of the fault scan register in the first scan chain on the fan-in scan register can be reduced, and the diagnostic precision of the scan chain is improved.

Optionally, the initial scan chain structure may include a plurality of compression channels, each compression channel includes at least two scan chains, and a logic operation is performed between shift output ends of at least two scan chains in each compression channel.

As shown in fig. 10, the initial scan chain structure includes the compression channel shown in fig. 10, where the compression channel includes scan chain 1 and scan chain 2, where exclusive-or operation is performed between the shift output ends of scan chain 1 and scan chain 2 in the compression channel, the ideal values of scan registers Cg, cf, ce in scan chain 1 are {1 1}, the ideal values of scan registers C6, C5, C4 in scan chain 2 are {1 1}, and the ideal values of scan registers Cg, cf, ce and scan registers C6, C5, C4 after exclusive-or operation are {0 0}, for example. The following describes in detail the problem that occurs in the case of the same compression channel in the first scan register and the first fan-in scan register corresponding thereto, taking the scan registers C6, C5, and C4 as examples of the occurrence of SA0.

Referring to fig. 10, if only scan register C6 fails in scan chain 2, scan register C6 exhibits SA0. The ATE device inputs a logic test vector { 10 1 1 1 1 1} to scan chain 1 and a logic test vector {1 1 1 1 1 1 1} to scan chain 2 in the load phase, and as shown in Table 1 below, the values of scan registers C6, C5, and C4 are all 0 and the values of scan registers C3, C2, and C1 are { 10 } because SA0 occurs in scan register C6. In the capture phase, the value captured by the scan register C4 is the value obtained by exclusive-or operation of the value 0 of the scan register C1 and the value 1 of the scan register C2, that is, the value captured by the scan register C4 is 1. The value captured by the scan register C5 is the value obtained by performing an and operation on the value 1 of the scan register C2 and the value 1 of the scan register C3, that is, the value captured by the scan register C5 is 1. The value captured by the scan register C6 is 0, the value captured by the scan register Cg is 0, the value captured by the scan register Cf is 0, the value captured by the scan register C6 is 0, and the value captured by the scan register Ce is 0, the value captured by the scan register C5 is 0. That is, the captured value of the scan registers C6, C5, C4 is {0 1}, and the captured value of the scan registers Cg, cf, ce is {0 0}. In the unloading phase, since the scan register C6 has SA0, the output values of the scan registers C6, C5, and C4 are {0 1}, the output values of the scan registers Cg, cf, and Ce are {0 0}, and the result of the exclusive-or operation between the output values of the scan registers C6, C5, and C4 and the values of the scan registers Cg, cf, and Ce is {0 1}.

TABLE 1

Scan register	C6	C5	C4	Cg	Cf	Ce
Load phase	0	0	0	1	1	1
capture phase	0	1	1	0	0	0
Unload phase	0	1	1	0	0	0

Referring to fig. 10, if only scan register C5 fails in scan chain 2, scan register C5 exhibits SA0. The ATE device inputs a logic test vector { 10 1 1 1 1 1} to scan chain 1 during the load phase, a logic test vector {1 1 1 1 1 1 1} to scan chain 2, and the values of scan registers C6, C5, and C4 are { 10 } and the values of scan registers C3, C2, and C1 are {1 10 } because of SA0 present in scan register C5, as shown in Table 2 below. In the capture phase, the values captured by the scan registers C6, C5, C4 are {1 1}, the captured values of the scan registers Cg, cf, ce are {0 1}. In the unloading phase, since the scan register C5 has SA0, the output values of the scan registers C6, C5, and C4 are {0 1}, the output values of the scan registers Cg, cf, and Ce are {0 1}, and the result of exclusive-or operation between the output values of the scan registers C6, C5, and C4 and the output values of the scan registers Cg, cf, and Ce is {0 1}.

TABLE 2

Scan register	C6	C5	C4	Cg	Cf	Ce
Load phase	1	0	0	1	1	1
capture phase	1	1	1	0	1	0
Unload phase	0	0	1	0	1	0

Referring to fig. 10, if only scan register C4 fails in scan chain 2, scan register C4 exhibits SA0. The ATE device inputs a logic test vector { 10 1 1 1 1 1} to scan chain 1 during the load phase, a logic test vector {1 1 1 1 1 1 1} to scan chain 2, and as shown in Table 3 below, the values of scan registers C6, C5, and C4 are {1 1} and the values of scan registers C3, C2, and C1 are { 10 } because of SA0 present in scan register C4. In the capture phase, the values captured by the scan registers C6, C5, C4 are {1 1}, the captured values of the scan registers Cg, cf, ce are {0 1}. In the unloading phase, since the scan register C4 has SA0, the output values of the scan registers C6, C5, and C4 are {0 0}, the output values of the scan registers Cg, cf, and Ce are {0 1}, and the result of exclusive-or operation between the output values of the scan registers C6, C5, and C4 and the output values of the scan registers Cg, cf, and Ce is {0 1}.

TABLE 3 Table 3

Scan register

C6

C5

C4

Cg

Cf

Ce

Load phase	1	1	0	1	1	1
capture phase	1	1	1	0	1	1
Unload phase	0	0	0	0	1	1

As is clear from the above, when SA0 appears in each of the scan registers C6, C5, and C4 in the scan chain 2, the exclusive or operation results of the output values of the scan registers C6, C5, and C4 and the output values of the scan registers Cg, cf, and Ce are { 01 } and are different from the ideal value {0 0 0 }. As can be seen from fig. 10, since the values captured by the registers Cg, cf, ce are affected by the fault values of the fan-in registers C4, C6, C5, the output values of the scan registers C6, C5, C4 are xored with the output values of the scan registers Cg, cf, ce, so that when SA0 occurs in each of the scan registers C6, C5, C4, the output observed value is always { 01 }, and the fault scan registers cannot be distinguished from the output observed value in the scan chain diagnosis stage. Namely, under the condition that the compression channel where the scan register is located is the same as the compression channel where the corresponding fan-in scan register is located, stronger coupling exists between scan chains in the same compression channel, and the diagnosis precision of the scan chains is lower.

In order to improve the detection accuracy of the scan chain, the embodiment of the present application further provides a scan chain design method, as shown in fig. 11, which may further include step S504 in addition to the steps S501 to S503. In the implementation shown in fig. 11, the scan chain where the first scan register is located is a first scan chain, the scan chain where the first fan-in scan register is located is a second scan chain, and the first scan chain and the second scan chain may be the same scan chain or different scan chains.

S504, exchanging the second scan chain with a third scan chain in another compression channel under the condition that the compression channel where the second scan chain is located is the same as the compression channel where the first scan chain is located.

For example, taking the compression channel in which the first scan chain is located as the first compression channel as an example, another compression channel in step S504 may be a second compression channel, where the second compression channel is a different compression channel from the first compression channel.

For example, if the compression channel in which the first scan chain is located is the first compression channel and the compression channel in which the second scan chain is located is also the first compression channel, determining that the compression channels in which the first scan chain and the second scan chain are located are the same may exchange the second scan chain with a third scan chain in the second compression channel, so that the second scan chain and the first scan chain are located in different compression channels. That is, in the case that the compression channel in which the first scan register is located is the same as the compression channel in which the first fan-in scan register is located, the compression channel in which the first scan register is located can be made different from the compression channel in which the first fan-in scan register is located by exchanging the second scan chain with the third scan chain, so that the coupling between a plurality of scan chains in the same compression channel is reduced, and the diagnosis precision of the scan chains is improved.

Alternatively, in this embodiment, the scan chain in which the first scan register is located may be the same as or different from the scan chain in which the first fan-in scan register is located. That is, the first scan chain and the second scan chain may be the same scan chain or different scan chains. Fig. 10, 12 and 13 illustrate examples in which the scan chain in which the first scan register is located is different from the scan chain in which the first fan-in scan register is located.

For example, as shown in fig. 12, the first compression lane includes scan chain 1 and scan chain 2, the second compression lane includes scan chain 3 and scan chain 4, the first scan register is scan register C4 in scan chain 2, the first fan-in scan register is scan registers C2 and C1 in scan chain 1, and the third scan lane is scan chain 3 in the second compression lane. Referring to fig. 12, the scan chain where the first scan register C4 is located is the scan chain 2, the compression channel where the scan chain 2 is located is the first compression channel, the scan chain where the first fan-in scan registers C2 and C1 are located is the scan chain 1, and the compression channel where the scan chain 1 is located is also the first compression channel. That is, the compression channel in which the first scan register C4 is located is the same as the compression channel in which the first fan-in scan registers C2 and C1 are located. As shown in fig. 13, the scan chain 1 where the first fan-in scan registers C2 and C1 are located may be swapped with the scan chain 3 in the second compression channel, so that after the scan chain is swapped, the compression channel where the scan chain 2 is located is different from the compression channel where the scan chain 1 is located. That is, after the scan chains are swapped, the compression channel in which the first scan register C4 is located is different from the compression channel in which its corresponding first fan-in scan registers C2 and C1 are located.

Taking the scan chain structure after exchanging the second scan chain with the third scan chain in the second compression channel as shown in fig. 13, the ideal values of the scan registers C6, C5, and C4 in the scan chain 2 are {1 1}, the ideal values of the scan registers Cx, cy, and Cz in the scan chain 3 are { 1}, the ideal values of the scan registers C6, C5, and C4 after exclusive-or operation with the scan registers Cx, cy, and Cz are { 0}, and the scan chain 3 is a normal scan chain (scan chain 3 has no fault) as an example. The reason why the scan chain diagnostic accuracy can be improved after the scan chain is exchanged will be described below by taking the case where the scan registers C6, C5, and C4 have SA0, respectively.

As shown in fig. 13, if only the scan register C6 fails in the scan chain 2, the scan register C6 exhibits SA0. The ATE device inputs a logic test vector {1 1 1 1 1 1 1} to scan chain 3 and a logic test vector {1 1 1 1 1 1 1} to scan chain 2 in the load phase, and as shown in Table 4 below, the values of scan registers C6, C5, and C4 are all 0 and the values of scan registers C3, C2, and C1 are {1 0} because SA0 occurs in scan register C6. In the capture phase, the values captured by scan registers C6, C5, C4 are {0 1}, and the values captured by scan registers Cx, cy, and Cz are {1 1}. In the unloading phase, since the scan register C6 appears SA0, the output values of the scan registers C6, C5, C4 are {0 1}, the output values of the scan registers Cx, cy, and Cz are {1 1}, and the result of the exclusive-or operation of the output values of the scan registers C6, C5, C4 with the values of the scan registers Cx, cy, and Cz is {1 0}.

TABLE 4 Table 4

Scan register	C6	C5	C4	Cx	Cy	Cz
Load phase	0	0	0	1	1	1
capture phase	0	1	1	1	1	1
Unload phase	0	1	1	1	1	1

As shown in fig. 13, if only the scan register C5 fails in the scan chain 2, the scan register C5 has SA0. The ATE device inputs a logic test vector {1 1 1 1 1 1 1} to scan chain 3 and a logic test vector {1 1 1 1 1 1 1} to scan chain 2 in the load phase, and as shown in Table 5 below, the values of scan registers C6, C5, and C4 are {1 0} and the values of scan registers C3, C2, and C1 are {1 0} because of SA0 present in scan register C5. In the capture phase, the values captured by scan registers C6, C5, C4 are {1 1}, and the values captured by scan registers Cx, cy, and Cz are {1 1}. In the unloading phase, since the scan register C5 has SA0, the output values of the scan registers C6, C5, C4 are {0 1}, the output values of the scan registers Cx, cy, and Cz are {1 1}, and the result of the exclusive-or operation of the output values of the scan registers C6, C5, C4 with the values of the scan registers Cx, cy, and Cz is {1 0}.

TABLE 5

Scan register	C6	C5	C4	Cx	Cy	Cz
Load phase	1	0	0	1	1	1
capture phase	1	1	1	1	1	1

Unload phase

0

1

As shown in fig. 13, if only the scan register C4 fails in the scan chain 2, the scan register C4 exhibits SA0. The ATE device inputs a logic test vector {1 1 1 1 1 1 1} to scan chain 3 during the load phase, a logic test vector {1 1 1 1 1 1 1} to scan chain 2, and as shown in Table 6 below, the values of scan registers C6, C5, and C4 are {1 1} and the values of scan registers C3, C2, and C1 are {1 0} because of SA0 present in scan register C4. In the capture phase, the values captured by scan registers C6, C5, C4 are {1 1}, and the values captured by scan registers Cx, cy, and Cz are {1 1}. In the unloading phase, since the scan register C4 appears SA0, the output values of the scan registers C6, C5, C4 are {0 0}, the output values of the scan registers Cx, cy, and Cz are { 1}, and the result of the exclusive-or operation of the output values of the scan registers C6, C5, C4 with the values of the scan registers Cx, cy, and Cz is {1 1}.

TABLE 6

Scan register	C6	C5	C4	Cx	Cy	Cz
Load phase	1	0	0	1	1	1
capture phase	1	1	1	1	1	1
Unload phase	0	0	0	1	1	1

As can be seen from the above, when SA0 appears in the scan register C6 in the scan chain 2, the result of exclusive-or operation between the output values of the scan registers C6, C5, and C4 and the output values of the scan registers Cx, cy, and Cz is {1 0}. When SA0 appears in the scan register C5 in the scan chain 2, the result of exclusive-or operation between the output values of the scan registers C6, C5, C4 and the output values of the scan registers Cx, cy, and Cz is { 1.0 }. When the scan register C4 in the scan chain 2 exhibits SA0, the result of exclusive-or operation between the output values of the scan registers C6, C5, C4 and the output values of the scan registers Cx, cy, and Cz is {1 1}. That is, when SA0 appears in each of the scan registers C6, C5, and C4 in the scan chain 2, the output values of the scan registers C6, C5, and C4 are different from the output values of the scan registers Cx, cy, and Cz as a result of exclusive-or operation. Referring to fig. 13, after the scan chain 1 in the first compression channel is exchanged with the scan chain 3 in the second compression channel, the scan registers C6, C5, C4 and the scan registers Cg, cf, ce are located in different compression channels, so that the output value of the first compression channel is not affected by the scan registers Cg, cf, ce any more, the influence of the strong coupling between the scan registers C6, C5, C4 and the scan registers Cg, cf, ce on the output value of the first compression channel can be eliminated, so that the output values of the first three scan registers in the first compression channel are not necessarily {0 1}, and therefore, by adjusting the values of the logic test vectors, the failed scan register can be determined more accurately in the diagnosis stage, and the diagnosis accuracy of the scan chain is improved.

It can be understood that in the scan chain structure shown in fig. 12, since the values captured by the scan registers Cg, cf, ce are affected by the fault values of the scan registers C4, C6, C5, the output values of the scan registers C6, C5, C4 are xored with the output values of the scan registers Cg, cf, ce, and thus when SA0 occurs in each of the scan registers C6, C5, C4, the output observed value is always {0 1}, and the fault scan registers cannot be distinguished. In the scan chain structure shown in fig. 13, the scan registers C6, C5, C4 and the scan registers Cg, cf, ce are located in different compression channels, so that the output value of the first compression channel is not affected by the scan registers Cg, cf, ce any more, and the influence of the strong coupling between the scan registers C6, C5, C4 and the scan registers Cg, cf, ce on the output value of the first compression channel can be eliminated, so that the output values of the first three scan registers in the first compression channel are not necessarily {0 1}. That is, in the embodiment of the present application, the first scan register and the first fan-in scan register are disposed in different compression channels, so that when detecting a faulty scan unit based on the compression channel after exchanging scan chains, the coupling between multiple scan chains in the same compression channel can be reduced, and the diagnosis precision of the scan chains can be improved.

Note that, in the embodiment of the present application, the order of execution of the step S504 and the step S503 is not limited, and fig. 11 illustrates an example in which the step S504 is executed after the step S503.

Optionally, in order to further improve the diagnostic accuracy of the scan chain, the embodiment of the present application further provides a scan chain design method, as shown in fig. 14, where the method may further include steps S505 to S506 in addition to the steps S501 to S504 described above.

S505, determining the capture probability of each scanning register in the first scanning chain.

The capture probability of each scan register is used to indicate the probability that the scan register captures a 0 or 1. Alternatively, the capture probability of each scan register may be a value between 0 and 1. The closer the capture probability of a scan register is to 0, the greater the probability that the scan register captures 0. The closer the capture probability of a scan register is to 1, the greater the probability that the scan register captures 1.

Illustratively, PC1 (C) represents the probability that scan register C captures 1, PC0 (C) represents the probability that scan register C captures 0, PC0 (C) =1-PC 1 (C).

For example, taking an initial scan chain structure including the scan chain shown in fig. 15 as an example, as shown in fig. 15, the scan chain includes scan registers C1 to C5 serially cascaded, and any two adjacent scan registers C1 to C5 have an output terminal Q of the former scan register connected to an SI terminal of the latter scan register. If the probability of any one fan-in scan register (e.g., ca) capturing 1 is 0.5, then the probability of scan register C1 capturing 1 is the product of the probabilities of all its fan-in scan registers Ca through Ce capturing 1, so PC1 (C1) =pc 1 (Ca) ×pc1 (Cb) ×pc1 (Cc) ×pc1 (Cd) ×pc1 (Ce) =0.5≡5=0.03125. The probability of scan register C2 capturing 1 is the product of the probabilities of its fan-in 4 scan registers capturing 0, so PC1 (C2) =pc 0 (Cl) ×pc0 (Cm) ×pc0 (Cn) ×pc0 (Co) =0.5≡4=0.0625. By analogy, it can be determined that PC1 (C3) =0.5, PC1 (C4) =0.95, and PC1 (C5) =0.55.

S506, under the condition that the capturing probabilities of two adjacent scanning registers in the first scanning chain are all larger than a preset threshold value, or under the condition that the capturing probabilities of two adjacent scanning registers in the first scanning chain are all smaller than or equal to the preset threshold value, the connection relation among a plurality of scanning registers in the first scanning chain is adjusted, so that the capturing probability of one scanning register in the two adjacent scanning registers is larger than the preset threshold value, and the capturing probability of the other scanning register is smaller than or equal to the preset threshold value.

Illustratively, taking a preset threshold of 0.5 as an example, when the capture probability of the scan register is greater than 0.5, the probability of the scan register capturing 1 is greater. When the capture probability of the scan register is less than or equal to 0.5, the probability of the scan register capturing 0 is large.

Optionally, when the capturing probabilities of two adjacent scan registers in the first scan chain are both greater than a preset threshold, the probability of capturing 1 by the two adjacent scan registers is greater. When the capturing probabilities of two adjacent scanning registers in the first scanning chain are smaller than or equal to a preset threshold value, the probability that the two adjacent scanning registers capture 0 is larger.

Since the higher the probability that two or more adjacent scan registers in a scan chain capture the same value, the less likely a failed scan register will be located based on the observed output value of that scan chain. For example, as shown in fig. 15, the capturing probabilities of the scan registers C1, C2 and C3 are all less than or equal to 0.5, so that the scan registers C1, C2 and C3 have a high probability of capturing the same value 0, it is difficult to distinguish the case that the scan registers C1, C2 and C3 have SA0, and in the scan chain diagnosis stage, it is not possible to accurately locate which scan register has failed. That is, if the probability that the adjacent plurality of scan registers captures the same value 0 is high, it is difficult to distinguish which scan register at all has SA0. For another example, the capture probabilities of the scan registers C4 and C5 are both greater than 0.5, so the likelihood of the scan registers C4 and C5 capturing 1 is high, and it is difficult to distinguish between the cases of SA1 occurring in the scan registers C4 and C5, and it is not possible to accurately locate which scan register has failed during the scan chain diagnosis stage. That is, if the probability that the adjacent plurality of scan registers captures the same value 1 is high, it is difficult to distinguish which scan register at all has SA1.

In order to improve data sensitivity and improve detection precision of a scan chain, the connection relation of a plurality of scan registers in the scan chain can be adjusted, so that the probability of capturing 0 in one scan register is larger in any two adjacent scan registers in the scan chain, the probability of capturing 1 in one scan register is larger, and therefore different numerical values can be captured more easily in two adjacent scan registers. That is, in the scan chain after the connection relationship is exchanged, the possibility that any two adjacent scan registers capture different values is high.

For example, as shown in fig. 16, the scan chain structure after the exchange connection relationship is taken as an example, the scan registers C1, C4, C2, C5 and C3 in the scan chain after the exchange connection relationship are serially cascaded, and in any two adjacent scan registers, the probability that one scan register captures 0 is larger, the probability that the other scan register captures 1 is larger, that is, the probability that any two adjacent scan registers capture different values is larger, so that when SA0 or SA1 occurs in any one scan register, the failed scan register can be determined more easily, and the diagnostic accuracy of the scan chain is improved.

It can be appreciated that, according to the scan chain design method provided by the embodiment of the present application, by determining the capture probability of each scan register in the first scan chain, and when the probability that two adjacent scan registers capture the same value in the first scan chain is greater, by adjusting the connection relationship between the plurality of scan registers in the first scan chain, the probability that two adjacent scan registers capture different values is greater, so that when detecting a fault scan register based on the scan chain after adjusting the connection relationship, the fault scan register can be more easily determined, and the diagnosis precision of the scan chain is improved.

The embodiment of the application also provides a chip, which comprises a first scanning chain and a second scanning chain, wherein the first scanning chain and the second scanning chain are different scanning chains, and a second scanning register in the second scanning chain is fanned into a first scanning register in the first scanning chain.

Optionally, the first scan chain and the second scan chain are scan chains in different compression channels.

Optionally, in two adjacent scan registers in the first scan chain, the capture probability of one scan register is greater than a preset threshold, and the capture probability of the other scan register is less than or equal to the preset threshold. That is, there is a greater likelihood that two adjacent scan registers in the first scan chain will capture different values.

The embodiment of the application also provides a chip, which comprises a first scanning chain, wherein a second scanning register in the first scanning chain is fanned into a first scanning register in the first scanning chain, and the second scanning register is closer to a shift input end of the first scanning chain than the first scanning register.

The foregoing description of the solution provided in the embodiments of the present application has been presented mainly from the perspective of method steps. It will be appreciated that the electronic device, in order to achieve the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as a combination of hardware and computer software. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application may divide the functional modules of the electronic device according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

Fig. 17 shows a schematic structural diagram of a scan chain design apparatus 1700, which may be an electronic device in the above embodiment, or may be a chip in the electronic device, and the scan chain design apparatus 1700 may be used to implement the scan chain design method of any of the above embodiments.

The scan chain design apparatus 1700 includes: a processing unit 1701 and a transceiver unit 1702. Illustratively, the transceiving unit 1702 is configured to support the scan chain design apparatus 1700 to transceive information, or to communicate with other devices. The processing unit 1701 is configured to control and manage the operations of the scan chain design apparatus 1700, and is configured to perform the processing performed by the scan chain design apparatus 1700 in the above embodiment, and optionally, if the scan chain design apparatus 1700 includes a storage unit, the processing unit 1701 may further execute a program or instructions stored in the storage unit, so that the scan chain design apparatus 1700 implements the methods and functions related to any of the above embodiments.

For example, the processing unit 1701 described above may be used to perform steps S502-S503 in fig. 5, or steps S502-S504 in fig. 11, or steps S502-S506 in fig. 14, for example, and/or other processes for the techniques described herein. The transceiving unit 1702 may be used to perform, for example, step S501 in fig. 5, and/or other processes for the techniques described herein. All relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

Illustratively, in a hardware implementation, the functions of the processing unit 1701 may be performed by the processor 401, the functions of the transceiver unit 1702 may be performed by the transceiver 403 (transmitter/receiver) and/or the communication interface, where the processing unit 1701 may be embedded in hardware or independent of the processor of the scan chain design apparatus 1700, or may be stored in software in a memory of the scan chain design apparatus 1700, so that the processor invokes operations corresponding to perform the above respective functional units.

When the processing unit 1701 is a processor and the transceiver unit 1702 is a transceiver, the specific structure of the scan chain design apparatus shown in fig. 17 may be the electronic device shown in fig. 4, where the description of all relevant contents of each component related to fig. 4 may be referred to the functional description of the corresponding component in fig. 17, and will not be repeated herein.

The embodiment of the application also provides electronic equipment, which comprises a processor, a transceiver and a memory, wherein the transceiver is used for receiving and transmitting information or communicating with other network elements; a memory for storing computer-executable instructions; a processor for executing computer-executable instructions to support the detection apparatus to implement the scan chain design method shown in any one of fig. 5, 11 or 14.

Embodiments of the present application also provide a computer readable storage medium having computer program code stored therein, which when executed by the above-described processor, causes an electronic device to perform the scan chain design method shown in any one of fig. 5, 11, or 14.

Embodiments of the present application also provide a computer program product which, when run on a computer, causes the computer to perform the scan chain design method shown in any one of fig. 5, 11 or 14.

The embodiment of the application also provides a scan chain design device, which can exist in the form of a chip product, and the structure of the device comprises a processor and an interface circuit, wherein the processor is used for communicating with other devices through the interface circuit, so that the device executes the scan chain design method shown in any one of the figures 5, 11 or 14.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware, or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. In addition, the ASIC may be located in a core network interface device. The processor and the storage medium may reside as discrete components in a core network interface device.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present invention in further detail, and are not to be construed as limiting the scope of the invention, but are merely intended to cover any modifications, equivalents, improvements, etc. based on the teachings of the invention.

Claims

A scan chain design method, the method comprising:

Acquiring an initial scan chain structure, wherein the initial scan chain structure is used for indicating the connection relation between a plurality of scan chains and combinational logic, and each scan chain comprises a plurality of scan registers;

determining a scan chain where a first fan-in scan register corresponding to a first scan register in a first scan chain is located based on the initial scan chain structure; the first scan chain is any one of the plurality of scan chains, and the first fan-in scan register is a scan register that fans in the first scan register;

exchanging the first fan-in scanning register with a second scanning register in a second scanning chain under the condition that the scanning chain where the first fan-in scanning register is located is the first scanning chain; the plurality of scan chains includes the second scan chain.
The method of claim 1, wherein the second scan chain is a different scan chain than the first scan chain.
The method of claim 1, wherein the second scan chain is the same scan chain as the first scan chain; the first scan register is closer to the shift input end of the first scan chain than the first fan-in scan register before the first fan-in scan register is swapped with a second scan register in the second scan chain, and the second scan register is a scan register in the first scan chain closer to the shift input end than the first scan register.
A method according to claim 2 or 3, wherein the initial scan chain structure comprises a plurality of compression channels, each compression channel comprising at least two scan chains, the shift outputs of the at least two scan chains in each compression channel being logically operated upon, the method further comprising:

and exchanging the second scanning chain with a third scanning chain in another compression channel under the condition that the compression channel where the second scanning chain is located is the same as the compression channel where the first scanning chain is located.
The method according to any one of claims 1-4, further comprising:

determining a capture probability for each scan register in the first scan chain; the capture probability of each scan register is used to indicate the probability that the scan register captures a 0 or 1;

and under the condition that the capturing probabilities of two adjacent scanning registers in the first scanning chain are all larger than a preset threshold value, or the capturing probabilities of two adjacent scanning registers in the first scanning chain are smaller than or equal to the preset threshold value, adjusting the connection relation among a plurality of scanning registers in the first scanning chain so that the capturing probability of one scanning register in the two adjacent scanning registers is larger than the preset threshold value, and the capturing probability of the other scanning register is smaller than or equal to the preset threshold value.
A chip comprising a first scan chain and a second scan chain, the first scan chain and the second scan chain being different scan chains, a first scan register in the first scan chain fanning into a second scan register in the second scan chain.
The chip of claim 6, wherein the first scan chain and the second scan chain are scan chains in different compression channels; the compression channel comprises at least two scan chains, and logic operation is performed between shift output ends of the at least two scan chains in the compression channel.
The chip of claim 6 or 7, wherein the probability of capture of one scan register is greater than a predetermined threshold and the probability of capture of the other scan register is less than or equal to the predetermined threshold in two adjacent scan registers in the first scan chain.
A chip comprising a first scan chain, a first scan register in the first scan chain fanning into a second scan register in the first scan chain, the first scan register being closer to a shift input of the first scan chain than the second scan register.
The chip of claim 9, wherein the probability of capture for one scan register is greater than a predetermined threshold and the probability of capture for the other scan register is less than or equal to the predetermined threshold in two adjacent scan registers in the first scan chain.
A scan chain design apparatus, comprising a processor and a memory for storing a computer program; the processor is configured to execute the computer program to cause the electronic device to implement the method of any one of claims 1-5.
An electronic device comprising a processor and interface circuitry, the processor being configured to communicate with other apparatus via the interface circuitry to implement the method of any of claims 1-5.
A computer readable storage medium having computer program code embodied therein, which, when run on a processor, causes the processor to perform the method of any of claims 1-5.