CN117280180A

CN117280180A - State machine motor controller

Info

Publication number: CN117280180A
Application number: CN202280034337.7A
Authority: CN
Inventors: R·帕尼
Original assignee: Microchip Technology Inc
Current assignee: Microchip Technology Inc
Priority date: 2021-10-18
Filing date: 2022-08-09
Publication date: 2023-12-22

Abstract

A State Machine Motor Controller (SMMC) interface includes a plurality of states defining a unique set of energized poles/one or more motor phases. The digital sensor captures the beginning of the rotor pole overlap with the stator pole. A state change occurs when a rotor pole begins to overlap a stator pole. The number of states depends on the number of phases and the design of the motor. The SMMC has up to four inputs to accept rotation information from the digital sensor and can control a motor having up to 16 states. The sequencer is used to track the state changes and provide the next state according to the forward/reverse direction setting and the brake setting. The counter provides a rotational speed based on the number of clock pulses per time period for the state change. The sequencer examines the fault sensor and generates a fault interrupt therefrom.

Description

State machine motor controller

The present application claims priority from commonly owned indian patent application No. 2021/11047190 entitled "state machine motor controller (State Machine Motor Controller)" filed on 10/18 of 2021, which is hereby incorporated by reference for all purposes.

Technical Field

The present disclosure relates to motor controllers, and more particularly to motor controllers including a Position Decoder (PDEC).

Background

Switched Reluctance Motors (SRMs) are currently being considered for applications ranging from low power servo motors to high power traction drives. Motors with power ratings ranging from 4kW to 22kW are currently commercially available for many applications. The SRM is a motor having a stator and a rotor, similar to a conventional motor. The stator is composed of a magnetic material and has conductors (windings) to generate a magnetic field, but the rotor structure is different from a brushed DC motor or a permanent magnet DC motor. In SRM, the rotor is composed of magnetic material, but has no windings or permanent magnets, and the number of poles on its stator and rotor are not equal. The rotor rotates due to reluctance torque generated by a magnetic field generated in the stator winding.

SRM is a double salient machine, meaning that both stator and rotor have salient poles. Fig. 3 shows an energized one-phase winding of a four-phase switched reluctance motor having 8 poles on the stator and 6 poles on the rotor. When the rotor has no windings, each stator pole has concentrated windings around it, and each pair of diametrically opposed coils comprises one phase of the motor. These motors are designed for applications other than those designed for stepper motors. Although various combinations of stator and rotor pole numbers are possible in SRM, the most common are the stator/rotor: 8/6 and 6/4. The stator has concentrated coils and diametrically opposed coils are connected in series or parallel to provide a phase. Thus, motors with pole numbers of 6/4 and 8/6 will have three and four phases, respectively.

In SRM, the number of stator and rotor poles is a multiple of two (2), but they are not equal. This asymmetry means that fewer rotor poles are not aligned with the stator poles. When misaligned stator poles are energized, the generated magnetic field will have a higher reluctance path to flow through adjacent rotor poles. This high reluctance creates torque in the rotor to align the rotor with the stator. Once alignment is complete, the current set of aligned stator poles is de-energized and the next set of misaligned stator poles is energized. This process is repeated to produce nearly continuous torque, thereby causing the rotor to rotate uniformly. Synchronization of the excitation switch with the rotor position can be achieved by simple rotor position feedback. The motor may also provide regenerative braking. If the phases are excited after the rotor crosses the minimum reluctance position, the rotor will experience a torque opposite to its motion, the rotor will slow down, and the mechanical energy drawn from the rotor will be converted to electrical energy and supplied to a power source. In fact, the possibility of operating in all four quadrants of the speed-torque plane and obtaining flexible speed-torque characteristics simply by appropriate switching of the current pulses makes the SRM very versatile. Because there are no windings on the rotor, the SRM is robust and can operate at very high rotational speeds.

As can be appreciated from the operating principles of SRMs, it is important to know when the rotor poles start to overlap a set of stator poles and energize those stator poles to achieve maximum torque and increase motor efficiency. In SRM, pole inversion may not be achieved because the rotor has no electric/permanent magnets and thus an H-bridge may not be achieved. The control circuit of the SRM may be composed of a pair of transistors/MOSFETs to control switching of each phase, see the four-phase SRM of fig. 4. Depending on the rotor position, one or both phases may be excited, e.g. the duty cycles of the two phases may overlap.

In the motor control industry, current QEI/PDEC interfaces provide a solution for identifying rotor position but based on polling. The user cannot know the initial state of the rotor, but must bring the rotor to a known position.

Brushless direct current (BLDC) motors may use a rotor position sensor, such as a hall effect sensor (Hall effect sensor), to determine the current position (state) of the BLDC rotor. The PDEC interface operating in Hall mode will check the state transitions of the Hall sensor and derive the rotation of the motor rotor therefrom. PDEC interfaces operating in hall mode are typically used to control BLDC motors, however, the PDEC interfaces may not be suitable for controlling SRMs that are becoming more and more popular for use.

Disclosure of Invention

Accordingly, the examples herein provide a way to determine when a rotor pole begins to overlap a set of stator poles in an SRM, and to energize those stator poles to achieve maximum torque and improve motor efficiency.

According to one aspect, there is provided a state machine motor controller interface comprising: an edge detector having a plurality of first inputs and a plurality of first outputs, wherein each of the plurality of first inputs is adapted to be coupled to a respective one of a plurality of position sensors, whereby each of the plurality of position sensors indicates a different motor rotor angle range; determining, when a first input receives a sensor output from an associated position sensor, its state based on the sensor output logic values, wherein each state is defined by a logic value stored in a register and is compared to the sensor output logic value after a transition thereof, and wherein one of the plurality of first outputs provides the state and another of the plurality of first outputs provides a state change pulse; a sequencer, the sequencer comprising: a state input coupled to a state output from the edge detector; a state change pulse input coupled to a state change pulse output from the edge detector; an active state change event/interrupt output; and a plurality of definition registers for defining the expected states; comparison logic for verifying the state received from the edge detector with an associated one of the expected states, updating a next expected state if the state received prior to receiving an overflow from the counter is valid and generating a valid state change event/interrupt, and if the received state is not valid until a counter overflow condition, not updating the next expected state and generating a fault interrupt; a counter having a clock input coupled to a clock and a count value output, wherein the counter increments the count value of a received clock pulse until a valid status pulse is received from the sequencer, whereby the count value will be stored in a count register and the count value of the counter will be reset to zero and an overflow output will be generated if the count value exceeds a maximum count.

In another aspect, a state machine motor controller is provided, the state machine motor controller comprising: a processor; a transitory storage medium comprising a plurality of registers for storing user-defined parameters and processed data, the plurality of registers comprising: a plurality of definition registers for defining a desired rotor state; a plurality of definition registers for defining a next rotor state; and a non-transitory storage medium comprising a set of computer readable instructions stored in the non-transitory storage medium and configured, when executed by the processor, to control the controller to: calculating a rotor state based on the user-defined parameters and storing the rotor state in the plurality of definition registers in the transient storage medium for defining an expected rotor state; determining an initial rotor state based on the rotor position input data; storing a next rotor state in the plurality of definition registers for defining the next rotor state; storing the expected rotor state in the plurality of definition registers for defining the expected rotor state; detecting a change in rotor state based on the rotor position input data; verifying the rotor state as the expected rotor state and resetting the counter; determining a next rotor state based on the user-defined parameter and the expected rotor state in the transient storage medium, and loading the next rotor state into one of the plurality of registers for defining the expected rotor state; and updating the expected rotor state with the next rotor state.

According to still another aspect, there is provided a state machine motor controller comprising: a processor; a transitory storage medium comprising a plurality of registers for storing user-defined parameters and processed data, the plurality of registers comprising: a control register having a length field specifying a number of rotor states; a control register having a rotor direction field specifying a direction selected from forward and reverse directions; a control register having a rotor braking condition field specifying a condition selected from braking and non-braking; a plurality of definition registers for defining a desired rotor state; a plurality of definition registers for defining a next rotor state; and a control register having a maximum count value; and a non-transitory storage medium comprising a set of computer readable instructions stored in the non-transitory storage medium and configured, when executed by the processor, to control the controller to: calculating a rotor state based on the user-defined parameters and storing the rotor state in the plurality of definition registers in the transient storage medium for defining an expected rotor state; determining an initial rotor state based on the rotor position input data; storing a next rotor state in the plurality of definition registers for defining the next rotor state; storing the expected rotor state in the plurality of definition registers for defining the expected rotor state; correlating the rotor position input data with rotor status; detecting a change in rotor state based on the rotor position input data; verifying the rotor state as the expected rotor state and resetting the counter; determining a next rotor state based on the user-defined parameter and the expected rotor state in the transient storage medium, and loading the next rotor state into one of the plurality of registers for defining the expected rotor state; updating the expected rotor state with the next rotor state; and counts clock pulses to update a count value, compares the count value to a maximum count value, and generates an overflow when the count value exceeds the maximum count value.

Drawings

A more complete understanding of the present disclosure may be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 depicts a high-level schematic block diagram of a State Machine Motor Controller (SMMC) interface according to the teachings of the present disclosure;

FIG. 2 illustrates a more detailed schematic block diagram of the SMMC interface shown in FIG. 1 in accordance with the teachings of the present disclosure;

FIG. 3 illustrates a schematic cross-sectional view of a four-phase Switched Reluctance Motor (SRM) according to a specific example of the present disclosure;

FIG. 4 illustrates a schematic diagram of a power control circuit for a four-phase Switched Reluctance Motor (SRM) according to a specific example of the present disclosure;

FIG. 5 illustrates a state table of four-phase switched reluctance motor state definitions according to a specific example of the present disclosure;

FIG. 6 illustrates a table of legend definitions for the waveform diagrams shown in FIGS. 7 and 8, according to specific examples of the present disclosure;

fig. 7 illustrates schematic waveforms of an SRM rotating in a forward (counterclockwise) direction according to a specific example of the present disclosure;

fig. 8 illustrates a schematic waveform of an SRM rotated in a reverse (clockwise) direction according to a specific example of the present disclosure;

FIG. 9 illustrates a schematic diagram of a cross section, motor winding connections, and Hall effect sensors for a brushless direct current (BLDC) motor in accordance with the teachings of the present disclosure;

FIG. 10 illustrates a schematic diagram of Hall sensor states and positions for a brushless direct current (BLDC) motor in accordance with the teachings of the present disclosure;

FIG. 11 illustrates a state table of three-phase BLDC motor state definitions according to a specific example of the present disclosure;

FIG. 12 illustrates a table of legend definitions for the waveform diagrams shown in FIGS. 13 and 14, according to specific examples of the present disclosure;

fig. 13 illustrates a schematic waveform of a BLDC motor rotated in a forward (counterclockwise) direction according to a specific example of the present disclosure; and is also provided with

Fig. 14 shows a schematic waveform of a BLDC motor rotated in a reverse (clockwise) direction according to a specific example of the present disclosure.

While the disclosure is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. The description herein of specific examples is not intended to limit the disclosure to the form disclosed herein.

Detailed Description

The proposed State Machine Motor Controller (SMMC) interface may have a state machine like architecture. Here, a state defines a unique set of energized poles/one or more motor phases. Digital sensors may be strategically placed to capture the onset of overlap of rotor poles and stator poles. These digital sensors may provide rotational position as input to the SMMC described below.

It is contemplated and within the scope of this disclosure and not limited thereto that the SMMC interface may have the following functions, features and advantages: (1) There are at most four inputs for accepting rotation information from the digital sensor, such as proximity sensors, infrared transmitters and receivers, hall effect, etc., in particular there may be two inputs or three inputs or four inputs from the sensor. (2) an electric machine having up to 16 states can be controlled. (3) Events/interrupts may be generated for a received valid state change. (4) A sequencer is provided that is operable to track the state changes of the inputs and provide the next state in accordance with the forward/reverse direction settings and the brake settings. (5) The counter may provide a rotational speed based on the number of clock pulses per time period for the state change. (6) If no valid state change is received, the user enters an overflow value for counting by a counter to generate an overflow condition. (7) The sequencer may check for a fault sensor and generate a fault interrupt therefrom. (8) supporting all four-quadrant operation of the motor.

RPM or RPS is defined as the number of revolutions of the motor per minute or second, respectively. The motor RPM/RPS may be calculated from the counter count value of the state change. The calculation formula is as follows:

Referring now to the drawings, details of examples are schematically shown. Like elements in the drawings will be represented by like numbers, and like elements will be represented by like numbers with a different lower case letter suffix.

Referring to fig. 1, there is depicted a high-level schematic block diagram of a State Machine Motor Controller (SMMC) interface 300 in accordance with the teachings of the present disclosure. The SMMC interface may include three sub-parts: (1) an edge detector 302; (2) a counter 304 and (3) a sequencer 306.

Referring to fig. 2, a more detailed schematic block diagram of the SMMC interface shown in fig. 1 is depicted in accordance with the teachings of the present disclosure. Edge detector 302 will check for any edges (change in logic state) on four (4) input lines SMMC1, SMMC2, SMMC3, and SMMC 4. Filtering of its signal may also be added. A register may be provided for the user to define the sensor logic value for each state. Two edges (positive and negative) may be detected by edge detector 302 and each sensor input (SMMCx) is converted to a state, the state is sent to sequencer 306, and a pulse signal is sent to signal an edge indicating a detected change in logic state. If the sensor logic value received by edge detector 302 is not defined in a register, edge detector 302 may not send a pulse signal.

The clock is provided to the counter 304. The counter 304 increments the count of clock pulses until a valid state change pulse is received from the sequencer 306. Upon receipt of a valid state change pulse from sequencer 306, the count value will be stored in a count register (not shown) and then counter 304 will be reset to count again from 0. The motor rotor speed may be calculated from a value read from a count register (not shown) when the state changes. The user may provide a maximum count that the counter 304 may count until a valid status pulse is received. If the counter 304 exceeds this value, the counter 304 will send an overflow condition to the sequencer 306. The clock frequency may be greater than two (2) times the absolute maximum wheel per second (RPS) times the number of states per rotor rotation.

Sequencer 306 is the core of SMMC interface 300. The state will start from state 0, but the user can select the number of states by writing to a length field in a control register (not shown), with OxF as the maximum number of states. For each defined state, there may be a register (not shown) for defining the states for the forward, reverse, forward braking and reverse braking states. Once the sequencer 306 receives the state change pulse from the edge detector 302, the sequencer will verify the received state with the expected state. Sequencer 306 will wait for a valid state change until an overflow signal from counter 304 is received. Upon receipt of a valid state change, the sequencer 306 will update the next state based on the forward/reverse and brake inputs (conditions). For example, if the current state is 0x1, the expected state will be 0x2 if the forward condition is set, or 0x0 if the reverse condition is set. Sequencer 306 will wait until the next expected state is received, or until an overflow from counter 304 is received, and a corresponding event/interrupt is generated. Sequencer 306 will determine the next state by reading the forward/reverse inputs and the brake inputs and then update the next state to a register (not shown). Fig. 5 shows a logic table for determining the next state. Upon receipt of the valid state, sequencer 306 will update the next valid state register (not shown). The user can read this register and send control signals accordingly. When a valid state is received, the user may choose to perform event generation or interrupt generation. There may be a unique event for each state and one interrupt. Fig. 3 to 8 provide examples on how four-quadrant control is achieved with an 8-pole stator and 6-pole rotor SRM having 8 states.

Referring to fig. 5, a state table is depicted of four-phase switched reluctance motor state definitions and relationships between rotor angles and motor phases to be energized according to a specific example of the present disclosure. The table also contains definitions of sensor readings or sensor data in hexadecimal format for each state and the next state for different motor operating modes (e.g., forward, reverse, forward braking, and reverse braking).

Referring to fig. 6, a table of legend definitions for the waveform diagrams shown in fig. 7 and 8 according to a specific example of the present disclosure is depicted.

Referring to fig. 7, a schematic waveform of an SRM rotated in a forward (counterclockwise) direction according to a specific example of the present disclosure is depicted. The sensors are strategically placed on the SRM to capture the position of the rotor relative to the stator. In this example, the motor is arranged to rotate in a forward direction. Initially, the forward/reverse (FR) bit is set low, indicating forward rotation, and the brake bit is set low, indicating no braking. The initial state of the motor sensor data in hexadecimal format is 0x6, which corresponds to state 7 as defined in fig. 5 (current state=0x7). The expected state and the next state (initial expected state=0x0; initial next state=0x7) are updated from the state table of fig. 5 based on the sensor data of the initial state of the rotor position. State 7 is energized and the rotor of the motor begins to rotate in the forward direction. Once the rotor rotates to a certain angle that changes the sensor data to 0x5, the edge detector block detects this change in sensor data and transitions the current state to state 0 (current state=0x0) as defined in fig. 5, and the edge detector block generates a pulse signal to the sequencer block. The sequence block then verifies the state received from the edge detector block by comparing the current state with the expected state (in which case the current state=0x0 and the expected state=0x0) and generates a valid state pulse if the same expected state is received. Then, the sequence block updates the next state (next state=0x0) according to the input conditions of the forward/reverse bit and the brake bit. Later, the active state bit is pulsed low, the sequence block updates the expected state (expected state=0x1) based on the state table of fig. 5, and the Counter (CNT) is reset. The sequence block then waits until sensor data corresponding to the expected state is received or overflows. As shown in fig. 7, the next sensor data=0x7 corresponds to state 1 as defined in fig. 5, so the valid state bit is again triggered high.

In fig. 7, two failure scenarios are shown. In fig. 7, it is shown how the SMMC adjusts for different fault situations and when the counter reaches a maximum value to trigger an overflow OVE, a fault will be generated.

In the first fault condition shown in fig. 7, this first fault condition is referred to as "glitch" (where the sensor data changes to a state that is not the expected state for a short duration and later to the expected state. In this case, a Brake (BR) pulse signal is generated before the rotor rotates to a certain angle where sensor data is changed to be read as 0x2 (corresponding to state 3 (current state=0x3) in fig. 5). In spite of the BR signal, the sequence block verifies the state received from the edge detector block with the expected state (0 x 3) and generates a valid state pulse because both the current state and the expected state are equal to 0x 3. However, the sensor data changes to something other than 0x2 at the "glitch", but since the Counter (CNT) has not yet reached a maximum value, no Overflow (OVE) is triggered. The next reading of sensor data, although "glitch", is 0x1, which corresponds to state 4 in fig. 5 (current state=0x4). The sequence block verifies the state received from the edge detector block because the expected state=0x4 is the same as the current state=0x4 and generates a valid state pulse. Therefore, even if a "glitch" occurs, overflow (OVF) is not triggered because the Counter (CNT) does not reach a maximum value.

In a second fault condition shown in fig. 7, the sensor data is continuously changed to a plurality of unexpected states, triggering an overflow (0 VF). According to the state provided in fig. 5, when the sensor data is expected to change from 0x6 to 0x5 in the forward brake-less operation mode, the sensor data changes from 0x6 to 0x4 in this case. When the sensor data=0x5 is read, the rotor state corresponds to state 0 in fig. 5 (current state=0x0). Because the current state and the expected state are both equal to 0x0, the sequence block will still verify the state received from the edge detector block with the expected state (0 x 0) and generate a valid state pulse. However, when the rotor rotates, the sensor data is next read as 0x0, where the rotor state corresponds to state 5 in fig. 5 (current state=0x5). Because the expected state=0x1 does not match the current state=0x5, the sequence block does not verify the state received from the edge detector block and the Counter (CNT) is not reset. As the rotor continues to rotate, the sensor data is next read as 0x1, where the rotor state corresponds to state 4 in fig. 5 (current state=0x4). Because the expected state=0x1 and the current state=0x4 are not matched again, the sequence block does not verify the state received from the edge detector block and the Counter (CNT) is not reset. The sequencer waits for a valid state change until the Counter (CNT) reaches a maximum value, which triggers an Overflow (OVF).

Referring to fig. 8, a schematic waveform of an SRM rotated in a reverse (clockwise) direction according to a specific example of the present disclosure is depicted. In this example, the SRM motor is configured to rotate in a reverse direction. Initially, the forward/reverse (FR) bit is set high, indicating reverse rotation, and the brake bit is set low, indicating no braking. The initial sensor data is read as 0x5 in hexadecimal format, which corresponds to state 4 in fig. 5 (current state=0x0). The expected state and the next state (initial expected state=0x7; initial next state=0x4) are updated from the state table of fig. 5 based on the sensor data of the initial state of the rotor position. State 4 is energized (current state=0x0) and the rotor of the motor begins to rotate in the reverse direction. Once the rotor rotates to a certain angle that changes the sensor data to 0x6, the edge detector block detects this change in sensor data and converts it to state 3 (current state=0x7) as defined in fig. 5, and generates a pulse signal to the sequence block. The sequence block verifies the state received from the edge detector block by comparing the current state=0x7 with the expected state=0x7 and generates a valid state pulse if the expected state is received. The sequence block loads the next state by checking the states of the forward/reverse bit and the brake bit. Then, the sequence block updates the next state (next state=0x3) according to the input conditions of the forward/reverse bit and the brake bit. Later, the active state bit is pulsed low, the sequence block updates the expected state (expected state=0x6) based on the state table of fig. 5, and the Counter (CNT) is reset. The sequence block then waits until sensor data corresponding to the expected state is received or overflows.

The next sensor data=0x4 corresponds to state 2 (current state=0x6) as defined in fig. 5, so the valid state bit is triggered high again, because the current state=expected state=0x6, state 3 is activated, the next state=0x2, the valid state is pulsed low and the expected state=0x5, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

When the sensor data is read 0x0 and the process is repeated as described, the motor continues in the reverse direction.

With continued reference to fig. 8, the brake bit pulse is high. The next sensor data=0x1 corresponds to state 0 (current state=0x4) as defined in fig. 5, so the valid state bit is triggered high again because the current state=expected state=0x4, state 2 is activated, the next state=0x5 because BR is high, the valid state is pulsed low and the expected state=0x3, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

Since the next sensor data=0x2 corresponds to state 7 (current state=0x3) as defined in fig. 5, the brake bit remains high, so the valid state bit is again triggered high because the current state=expected state=0x3, state 3 is activated, the next state=0x4 because BR is still high, the valid state is pulsed low and the expected state=0x2, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

When the motor continues in the reverse direction, the brake bit pulse is low and the next sensor data=0x3 corresponds to state 6 (current state=0x2) as defined in fig. 5, so the valid state bit is again triggered high because the current state=anticipated state=0x2, state 7 is energized, the next state=0x6 because BR is now low, the valid state is pulsed low and anticipated state=0x1, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the anticipated state is received or overflows.

When the sensor data is read 0x7, 0x5 and 0x2 and the process is repeated as described, the motor continues in the reverse direction.

When the motor continues in the reverse direction, the next sensor data=0x1 corresponds to state 0 (current state=0x4) as defined in fig. 5, but in this case the valid state bit is not triggered high because the current state is not equal to the expected state (0x4, 0x6). No new state is activated and the expected state does not change (0 x 6), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

The motor continues in the reverse direction and the next sensor data=0x0 corresponds to state 1 (current state=0x5) as defined in fig. 5, but the valid state bit is not triggered high again because the current state is not equal to the expected state (0x1, 0x6). No new state is activated and the expected state does not change (0 x 6), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows. The Counter (CNT) continues to increment until it reaches a maximum value and an Overflow (OVF) is triggered.

Referring to fig. 9, a schematic cross-sectional view of a motor winding connection and hall effect sensor for a brushless direct current (BLDC) motor in accordance with the teachings of the present disclosure is shown. Brushless DC (BLDC) motors, also known as electronically commutated motors, have a three-phase stator and a permanent magnet rotor. In BLDC motors, an electronic servo replaces the mechanical commutator contacts. The stator coils are connected in such a way that three wires are drawn from the motor to provide switched DC power. For this BLDC motor, the SMMC interface has six (6) power MOSFET switches (not shown, but similar to fig. 2), two per phase. One for connection to the +ve supply and the other for connection to the return path. At any given point, one phase is stimulated with +ve voltage, while the other phase is connected to the return path. Based on the control method described above, the BLDC control circuit may be defined to have six (6) states, as shown in the table of fig. 11.

Referring to fig. 10, a schematic diagram of hall sensor states and positions for a brushless direct current (BLDC) motor in accordance with the teachings of the present disclosure is depicted. The SMMC interface disclosed herein may be used to control a BLDC motor if the BLDC motor has a sensor, such as a hall effect sensor, for detecting a state change while the motor is running.

Referring to fig. 12, a table of legend definitions for the waveform diagrams shown in fig. 13 and 14 according to a specific example of the present disclosure is depicted.

Referring to fig. 13, a schematic waveform of a BLDC motor rotated in a forward (counterclockwise) direction according to a specific example of the present disclosure is depicted. Initially, the forward/reverse (FR) bit is set low, indicating forward rotation, and the brake bit is set low, indicating no braking. The initial state of the motor sensor data in hexadecimal format is 0x3, which corresponds to state 5 (current state=0x5) in hexadecimal format as defined in fig. 11. The expected state and the next state (initial expected state=0x0; initial next state=0x5) are updated from the state table of fig. 11 based on the sensor data of the initial state of the rotor position. State 5 is energized and the rotor of the motor begins to rotate in the forward direction. Once the rotor rotates to a certain angle that changes the sensor data to 0x1, the edge detector block detects this change in sensor data and transitions the current state to state 0 (current state=0x0) as defined in fig. 11, and the edge detector block generates a pulse signal to the sequencer block. The sequence block then verifies the state received from the edge detector block by comparing the current state with the expected state (in which case the current state=0x0 and the expected state=0x0) and generates a valid state pulse if the expected state is received. State 0 is energized and the rotor of the motor continues to rotate in the forward direction. Then, the sequence block updates the next state (next state=0x0) according to the input conditions of the forward/reverse bit and the brake bit. Later, the active state bit is pulsed low, the sequence block updates the expected state (expected state=0x1) based on the state table of fig. 11, and the Counter (CNT) is reset. The sequence block then waits until sensor data corresponding to the expected state is received or overflows.

The next sensor data=0x5 corresponds to state 1 (current state=0x1) as defined in fig. 11, so the valid state bit is triggered high again because the current state=expected state=0x1, state 1 is activated, the next state=0x1, the valid state is pulsed low and the expected state=0x2, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

The next sensor data=0x4 corresponds to state 2 (current state=0x2) as defined in fig. 11, so the valid state bit is triggered high again because the current state=expected state=0x2, state 2 is activated, the next state=0x2, the valid state is pulsed low and the expected state=0x3, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

With continued reference to fig. 13, the brake bit pulse is high. The next sensor data=0x6 corresponds to state 3 (current state=0x3) as defined in fig. 11, so the valid state bit is triggered high again because the current state=expected state=0x3, state 3 is activated, the next state=0x0 because BR is high, the valid state is pulsed low and the expected state=0x4, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows. However, reading the sensor data is "glitched" but no action is taken until the sequence block receives sensor data corresponding to the expected state or overflows.

Since the next sensor data=0x2 corresponds to state 4 (current state=0x4) as defined in fig. 11, the brake bit remains high, so the valid state bit is again triggered high because the current state=expected state=0x4, state 4 is activated, the next state=0x1 because BR is high, the valid state is pulsed low and the expected state=0x5, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

When the motor continues in the forward direction, the brake bit pulse is low and the next sensor data=0x3 corresponds to state 5 (current state=0x5) as defined in fig. 11, so the valid state bit is again triggered high because the current state=anticipated state=0x5, state 5 is energized, the next state=0x5 because BR is now low, the valid state is pulsed low and anticipated state=0x0, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the anticipated state is received or overflows.

When the sensor data is read 0x1, 0x5 and 0x4 and the process is repeated as described, the motor continues in the forward direction.

When the motor continues in the forward direction, the next sensor data=0x3 corresponds to state 5 (current state=0x5) as defined in fig. 11, but in this case the valid state bit is not triggered high because the current state is not equal to the expected state (0x5×0x3). No state is activated and the expected state does not change (0 x 3), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

The motor continues in the forward direction and the next sensor data=0x1 corresponds to state 0 (current state=0x0) as defined in fig. 11, but the valid state bit is not triggered high again because the current state is not equal to the expected state (0x0x3). No state is activated and the expected state does not change (0 x 3), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows. The Counter (CNT) continues to increment until it reaches a maximum value and an Overflow (OVE) is triggered.

Referring to fig. 14, a schematic waveform of a BLDC motor rotated in a reverse (clockwise) direction according to a specific example of the present disclosure is depicted. Initially, the forward/reverse (FR) bit is set high, indicating reverse rotation, and the brake bit is set low, indicating no braking. The initial state of the sensor data=0x5, which corresponds to state 4 (current state=0x1) as defined in fig. 11. The expected state and the next state (initial expected state=0x0; initial next state=0x3) are updated from the state table of fig. 11 based on the sensor data of the initial state of the rotor position. State 4 is energized and the rotor of the motor begins to rotate in the reverse direction. Once the rotor rotates to a certain angle that changes the sensor data to 0x1, the edge detector block detects this change in sensor data and transitions the current state to state 3 (current state=0x0) as defined in fig. 11, and the edge detector block generates a pulse signal to the sequencer block. The sequence block then verifies the state received from the edge detector block by comparing the current state with the expected state (in which case the current state=0x0 and the expected state=0x0) and generates a valid state pulse if the expected state is received. State 3 is energized and the rotor of the motor continues to rotate in the reverse direction. Then, the sequence block updates the next state (next state=0x3) according to the input conditions of the forward/reverse bit and the brake bit. Later, the active state bit is pulsed low, the sequence block updates the expected state (expected state=0x2) based on the state table of fig. 11, and the Counter (CNT) is reset. The sequence block then waits until sensor data corresponding to the expected state is received or overflows.

The next sensor data=0x3 corresponds to state 2 (current state=0x2) as defined in fig. 11, so the valid state bit is triggered high again because the current state=expected state=0x2, state 2 is activated, the next state=0x2, the valid state is pulsed low and the expected state=0x1, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

When the sensor data is read 0x2 and the process is repeated as described, the motor continues in the reverse direction.

With continued reference to fig. 14, the brake bit pulse is high. The next sensor data=0x6 corresponds to state 3 (current state=0x3) as defined in fig. 11, so the valid state bit is triggered high again because the current state=expected state=0x3, state 3 is activated, the next state=0x3 because BR is high, the valid state is pulsed low and the expected state=0x2, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows. However, reading the sensor data is "glitched" but no action is taken until the sequence block receives sensor data corresponding to the expected state or overflows.

Since the next sensor data=0x4 corresponds to state 2 (current state=0x2) as defined in fig. 11, the brake bit remains high, so the valid state bit is again triggered high because the current state=expected state=0x2, state 2 is activated, the next state=0x2 because BR is high, the valid state is pulsed low and the expected state=0x1, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

When the motor continues in the reverse direction, the brake bit pulse is low and the next sensor data=0x5 corresponds to state 4 (current state=0x4) as defined in fig. 11, so the valid state bit is triggered high again because the current state=anticipated state=0x1, state 3 is energized, the next state=0x4 because BR is now low, the valid state is pulsed low and anticipated state=0x0, the Counter (CNT) is reset, and then the sequence block waits until sensor data corresponding to the anticipated state is received or overflows.

When the sensor data is read 0x1, 0x3 and 0x2 and the process is repeated as described, the motor continues in the forward direction.

When the motor continues in the reverse direction, the next sensor data=0x3 corresponds to state 2 (current state=0x5) as defined in fig. 11, but in this case the valid state bit is not triggered high because the current state is not equal to the expected state (0x5×0x3). No new state is activated and the expected state does not change (0 x 3), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows.

The motor continues in the reverse direction and the next sensor data=0x1 corresponds to state 3 (current state=0x0) as defined in fig. 11, but the valid state bit is not triggered high again because the current state is not equal to the expected state (0x0x3). No new state is activated and the expected state does not change (0 x 3), the Counter (CNT) is not reset, and then the sequence block waits until sensor data corresponding to the expected state is received or overflows. The Counter (CNT) continues to increment until it reaches a maximum value and an Overflow (OVE) is triggered.

The present disclosure has been described in terms of one or more examples, and many equivalents, alternatives, variations, and modifications, aside from those expressly stated, are possible and within the scope of the present disclosure. While the disclosure is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. The description herein of specific examples is not intended to limit the disclosure to the particular forms disclosed herein.

Claims

1. A state machine motor controller interface, the state machine motor controller interface comprising:

an edge detector having a plurality of first inputs and a plurality of first outputs, wherein:

each of the plurality of first inputs is adapted to be coupled to a respective one of a plurality of position sensors, whereby each of the plurality of position sensors indicates a different motor rotor angle range;

when the first input receives a sensor output from an associated position sensor, determining its state based on the sensor output logic values, wherein each state is defined by a logic value stored in a register and is compared to the sensor output logic value after its transition; and is also provided with

One of the plurality of first outputs provides the state and another of the plurality of first outputs provides a state change pulse;

a sequencer, the sequencer comprising:

a state input coupled to a state output from the edge detector;

a state change pulse input coupled to a state change pulse output from the edge detector;

An active state change event/interrupt output;

a plurality of definition registers for defining an expected state; and

comparison logic for verifying the state received from the edge detector with an associated one of the expected states, wherein if the state received prior to receiving an overflow from a counter is valid and a valid state change event/interrupt is generated, the next expected state is updated and if the received state is not valid until a counter overflow condition, the next expected state is not updated and a fault interrupt is generated;

a counter having a clock input coupled to a clock and a count value output, wherein:

the counter incrementing a count value of the received clock pulses until a valid status pulse is received from the sequencer;

thereby, the count value will be stored in a count register, and the count value of the counter will be reset to zero; and is also provided with

If the count value exceeds the maximum count, an overflow output will be generated.

2. The state machine motor controller interface of claim 1, wherein the defined state is selected from one or more of the group consisting of a forward state, a reverse state, a forward braking state, and a reverse braking state.

3. The state machine motor controller interface of any one of claims 1 to 2, wherein sequencer further comprises a control register having a length field that specifies a number of states to be received from the edge detector, whereby the sequencer is configurable for a plurality of rotor states.

4. A state machine motor controller interface according to any one of claims 1 to 3, wherein the edge detector is configurable to define a correlation of at least one input of rotor position and at least one rotor state.

5. The state machine motor controller interface of any one of claims 1 to 4, wherein the sequencer further comprises a rotor forward/reverse input, and the sequencer is configurable for either forward or reverse rotor rotation by the rotor forward/reverse input.

6. The state machine motor controller interface of any one of claims 1 to 5, wherein the sequencer further comprises a rotor braking input, and the sequencer is configurable for braking or non-braking rotor rotation by the rotor braking input.

7. The state machine motor controller interface of any one of claims 1 to 6, wherein the next expected state is configurable for an operational mode selected from the group consisting of: forward motor rotation, reverse motor rotation, braking forward motor rotation, and braking reverse motor rotation.

8. The state machine motor controller interface of any one of claims 1 to 7, wherein the sequencer further comprises: an active state pulse output to the counter and a fault condition output.

9. The state machine motor controller interface of any one of claims 1 to 8, wherein the sequencer further comprises an overflow input from the counter, wherein the counter is configurable to define a maximum count value, and wherein the counter outputs an overflow to the sequencer when the maximum count value is exceeded.

10. A state machine motor controller, the state machine motor controller comprising:

a processor;

a transitory storage medium comprising a plurality of registers for storing user-defined parameters and processed data, the plurality of registers comprising:

a plurality of definition registers for defining a desired rotor state;

a plurality of definition registers for defining a next rotor state; and

a non-transitory storage medium comprising a set of computer readable instructions stored in the non-transitory storage medium and configured, when executed by the processor, to control the controller to:

Calculating a rotor state based on user-defined parameters and storing the rotor state in the plurality of definition registers in the transient storage medium for defining an expected rotor state;

determining an initial rotor state based on the rotor position input data;

storing a next rotor state in the plurality of definition registers for defining the next rotor state;

storing the expected rotor state in the plurality of definition registers for defining the expected rotor state;

detecting a change in rotor state based on the rotor position input data;

verifying the rotor state as the expected rotor state and resetting the counter;

determining a next rotor state based on a user-defined parameter and the expected rotor state in the transient storage medium, and loading the next rotor state into one of the plurality of registers for defining an expected rotor state; and

updating the expected rotor state with the next rotor state.

11. The state machine motor controller of claim 10, wherein the rotor state is selected from one or more of the group consisting of a forward state, a reverse state, a forward braking state, and a reverse braking state.

12. The state machine motor controller of any one of claims 10 to 11, wherein the transitory storage medium further comprises a control register having a length field specifying a number of states, whereby the controller is configurable for a plurality of rotor states.

13. The state machine motor controller of any one of claims 10 to 12, wherein the set of computer readable instructions stored in the non-transitory storage medium and when executed by the processor are further configured to control a correlation of at least one input configurable to define a rotor position with at least one rotor state.

14. The state machine motor controller of any one of claims 10 to 13, wherein the transitory storage medium further comprises a control register having a rotor direction field specifying a direction selected from forward and reverse, whereby the controller is configurable for either forward or reverse rotor rotation.

15. The state machine motor controller of any one of claims 10 to 14, wherein the transitory storage medium further comprises a control register having a rotor braking condition field specifying a condition selected from braking and non-braking, whereby the controller is configurable for braking or non-braking rotation.

16. The state machine motor controller of any one of claims 10 to 15, wherein the next expected state is configurable for an operating mode selected from: forward motor rotation, reverse motor rotation, braking forward motor rotation, and braking reverse motor rotation.

17. The state machine motor controller of any one of claims 10 to 16, wherein the set of computer readable instructions stored in the non-transitory storage medium and when executed by the processor is further configured to control the controller to count clock pulses to update a count value, output valid state pulses when a rotor state corresponds to an expected rotor state, and reset the count value.

18. The state machine motor controller of any of claims 10 to 17, wherein the transitory storage medium including a plurality of registers for storing user-defined parameters and processed data includes a control register having a maximum count value, and wherein the set of computer readable instructions stored in the non-transitory storage medium and when executed by the processor are further configured to control the controller to count clock pulses to update a count value, compare the count value to a maximum count value, and generate an overflow when the count value exceeds the maximum count value.

19. A state machine motor controller, the state machine motor controller comprising:

a processor;

a control register having a length field specifying the number of rotor states;

a control register having a rotor direction field specifying a direction selected from forward and reverse;

a control register having a rotor braking condition field specifying a condition selected from braking and non-braking;

a plurality of definition registers for defining a desired rotor state;

a plurality of definition registers for defining a next rotor state; and

a control register having a maximum count value; and

Determining an initial rotor state based on the rotor position input data;

correlating the rotor position input data with rotor status;

detecting a change in rotor state based on the rotor position input data;

determining a next rotor state based on a user-defined parameter and the expected rotor state in the transient storage medium, and loading the next rotor state into one of the plurality of registers for defining an expected rotor state;

updating the expected rotor state with the next rotor state; and

the clock pulses are counted to update a count value, the count value is compared to a maximum count value, and an overflow is generated when the count value exceeds the maximum count value.

20. The state machine motor controller of claim 19, wherein the rotor state is selected from one or more of the group consisting of a forward state, a reverse state, a forward braking state, and a reverse braking state.