CN117279366A

CN117279366A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN117279366A
Application number: CN202210680843.5A
Authority: CN
Inventors: 郭帅
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-15
Filing date: 2022-06-15
Publication date: 2023-12-22

Abstract

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure, the semiconductor structure comprising: the semiconductor device comprises a first substrate and bit lines formed on the first substrate, wherein the bit lines extend along a first direction, a plurality of bit lines are parallel in a second direction, and the second direction is perpendicular to the first direction; the column structure extends in a third direction, one end of the column structure, which is close to the first substrate, is electrically connected with the bit line, the column structure comprises a first active area and a second active area which are not connected with each other, and the third direction is perpendicular to the first direction and the second direction; the isolation structure is positioned between the first active region and the second active region and extends along the second direction; the first word line is attached to the first active area, and the second word line is attached to the second active area, wherein the first word line and the second word line extend along the second direction; the first capacitor is electrically connected with the first active area, and the second capacitor is electrically connected with the second active area. The embodiment of the disclosure can improve the density of the memory cells.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of integrated circuit structures, and more particularly, to a semiconductor structure for a memory and a method of manufacturing the semiconductor structure.

Background

With the development of the semiconductor industry, the critical dimensions of devices are continuously reduced. VGT (Vertical Gate Transistor ) structures that have been studied at present, which can achieve very small linewidths and dimensions, are an important direction of future development. However, it has not been found that even smaller transistors than VGT structures, how to further reduce the integrated circuit size is a challenge.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

It is an object of the present disclosure to provide a semiconductor structure and a method of manufacturing the same for increasing the density of memory cells at least to some extent.

According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising: the semiconductor device comprises a first substrate and bit lines formed on the first substrate, wherein the bit lines extend along a first direction, a plurality of bit lines are parallel in a second direction, and the second direction is perpendicular to the first direction; the column structure extends in a third direction, one end of the column structure, which is close to the first substrate, is electrically connected with the bit line, wherein the column structure comprises a first active area and a second active area which are not connected with each other, and the third direction is perpendicular to the first direction and the second direction; the isolation structure is positioned between the first active area and the second active area, and extends along the second direction; the first word line is attached to the first active area, and the second word line is attached to the second active area, wherein the first word line and the second word line extend along the second direction; the first capacitor is electrically connected with the first active area, and the second capacitor is electrically connected with the second active area.

In one exemplary embodiment of the present disclosure, the semiconductor structure further includes: a first insulating layer located between the bit line and the first word line and between the bit line and the second word line in the third direction; a second insulating layer located over the first word line and the second word line in a third direction; and the third insulating layer is positioned above the columnar structure and the second insulating layer.

In one exemplary embodiment of the present disclosure, the isolation structure includes a second air gap.

In an exemplary embodiment of the present disclosure, the columnar structure is a cylindrical structure, a surface of the first active region attached to the isolation structure is a plane, and a surface facing away from the isolation structure is an arc surface; one surface of the second active region attached to the isolation structure is a plane, and one surface deviating from the isolation structure is an arc surface.

In an exemplary embodiment of the present disclosure, the columnar structure is a square columnar structure, one surface of the first active region, which is attached to the isolation structure, is a plane, and three surfaces, which are not attached to the isolation structure, are all planes; one surface of the second active area, which is attached to the isolation structure, is a plane, and three surfaces, which are not attached to the isolation structure, are planes.

In one exemplary embodiment of the present disclosure, the semiconductor structure further includes: the supporting layer is positioned above the third insulating layer; the lower end of the first contact pad is electrically connected with the first active area, and the upper end of the first contact pad is electrically connected with the first capacitor; the second contact pad, in the third direction, the lower extreme electric connection second active area of second contact pad, the upper end electric connection second electric capacity of second contact pad, wherein, first contact pad and second contact pad run through third insulating layer and supporting layer.

In one exemplary embodiment of the present disclosure, the height of the isolation structure is greater than the heights of the first and second active regions.

In one exemplary embodiment of the present disclosure, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer, wherein a first air gap is formed between the first sub-insulating layer and the second sub-insulating layer.

In one exemplary embodiment of the present disclosure, the first and second capacitors are electrically connected to the first and second active regions through a bonding process.

In one exemplary embodiment of the present disclosure, the first capacitor and the second capacitor each include a first portion and a second portion, wherein a junction of the first portion and the second portion has an inflection point.

According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising: providing a first substrate; manufacturing a plurality of bit lines on a first substrate, wherein the plurality of bit lines extend along a first direction and are arranged in parallel in a second direction, and the second direction is perpendicular to the first direction; manufacturing a cylindrical structure on the bit line, wherein the cylindrical structure extends along a third direction, and the third direction is perpendicular to the first direction and the second direction; manufacturing an isolation structure in the columnar structure, wherein the isolation structure extends along a second direction, and cutting the columnar structure into a first active region and a second active region which are not connected; forming a first word line attached to the first active region and a second word line attached to the second active region, wherein the first word line and the second word line extend along a second direction, and parts attached to the isolation structure exist in the second direction; forming a first capacitor electrically connected with the first active region and a second capacitor electrically connected with the second active region.

In one exemplary embodiment of the present disclosure, the step of fabricating a plurality of bit lines on a first substrate includes: etching a first groove extending along a first direction on a first substrate, and filling the first groove to manufacture a shallow trench isolation structure; etching a second groove extending along the first direction between two adjacent shallow groove isolation structures on the first substrate, wherein the bottom of the second groove is exposed out of the first substrate; ion implantation is performed on the first substrate through the second trench to form a bit line.

In one exemplary embodiment of the present disclosure, the step of fabricating a pillar structure on a bit line includes: forming a thin film stack structure on a first substrate, wherein the thin film stack structure comprises a first insulating layer, a first sacrificial layer and a second insulating layer, and the first sacrificial layer is positioned between the first insulating layer and the second insulating layer; forming a third groove penetrating through the film stacking structure, wherein the bottom of the third groove is exposed out of the bit line; and forming a source electrode, a channel region and a drain electrode which are stacked in the third groove, wherein the source electrode, the channel region and the drain electrode form a columnar structure.

In one exemplary embodiment of the present disclosure, the step of fabricating an isolation structure in a columnar structure includes: forming a third insulating layer on the columnar structure; forming a fourth groove in the columnar structure, wherein the bottom of the fourth groove exposes the bit line, and the height of the fourth groove in the third direction is larger than that of the columnar structure in the third direction; the fourth trench is filled to form an isolation structure.

In one exemplary embodiment of the present disclosure, the isolation structure is formed with a second air gap extending in the second direction.

In one exemplary embodiment of the present disclosure, the step of forming a first word line that conforms to the first active region and a second word line that conforms to the second active region includes: etching a fifth groove between two adjacent columnar structures, wherein the bottom of the fifth groove exposes the bit line, and the side wall of the fifth groove exposes the first sacrificial layer, and the fifth groove extends along the second direction; removing the first sacrificial layer by taking the fifth groove as a window to form a filling region; filling conductive material in the filling area to form an initial conductive layer, wherein the initial conductive layer is also filled with a fifth groove; removing part of the initial conductive layer in the fifth groove to form a first word line attached to the first active region and a second word line attached to the second active region;

in one exemplary embodiment of the present disclosure, after forming the first word line and the second word line, further comprising: and filling the fifth groove with an insulating medium to form a fourth insulating layer.

In an exemplary embodiment of the present disclosure, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the thin film stack structure further includes a second sacrificial layer between the first sub-insulating layer and the second sub-insulating layer, and the forming of the first word line to be bonded to the first active region and the second word line to be bonded to the second active region includes: etching a fifth groove between two adjacent columnar structures, wherein the bottom of the fifth groove exposes the bit line, and the side wall of the fifth groove exposes the first sacrificial layer and the second sacrificial layer, and the fifth groove extends along the second direction; removing the first sacrificial layer by taking the fifth groove as a window to form a filling region; filling conductive material in the filling area to form an initial conductive layer, wherein the initial conductive layer is also filled with a fifth groove; removing part of the initial conductive layer in the fifth groove to form a first word line attached to the first active region and a second word line attached to the second active region; after forming the first word line and the second word line, further comprising: removing the second sacrificial layer by taking the fifth groove as a window to form a first air gap layer; and filling the fifth groove with an insulating medium to form a fourth insulating layer, and forming a first air gap through the first air gap layer.

In one exemplary embodiment of the present disclosure, the filling region further exposes a portion of the sidewall of the first active region and a portion of the sidewall of the second active region, and further includes, prior to forming the first word line and the second word line: and oxidizing part of the side wall of the first active region and part of the side wall of the second active region exposed to the filling region to form a first gate oxide dielectric layer and a second gate oxide dielectric layer respectively.

In one exemplary embodiment of the present disclosure, the step of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region includes: forming a support layer on the third insulating layer; forming a first contact hole and a second contact hole penetrating through the supporting layer and the third insulating layer, wherein the first contact hole exposes the first active region, and the second contact hole exposes the second active region; and forming a first contact pad filling the first contact hole, forming a second contact pad filling the second contact hole, wherein the first contact pad is used for connecting the first capacitor, and the second contact pad is used for connecting the second capacitor.

In an exemplary embodiment of the present disclosure, the step of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region further includes: forming a first support structure on the support layer; forming a first capacitor hole and a second capacitor hole penetrating through the first supporting structure, wherein the bottom of the first capacitor hole exposes the first contact pad, and the bottom of the second capacitor hole exposes the second contact pad; a first capacitor is formed in the first capacitor hole, and a second capacitor is formed in the second capacitor hole.

In an exemplary embodiment of the present disclosure, the step of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region further includes: providing a second substrate; manufacturing a first capacitor and a second capacitor on a second substrate to form a capacitor wafer; bonding the capacitor wafer to the supporting layer so that the first capacitor is electrically connected with the first contact pad and the second capacitor is electrically connected with the second contact pad.

In one exemplary embodiment of the present disclosure, fabricating a first capacitor and a second capacitor on a second substrate to form a capacitor wafer includes: etching a first groove and a second groove on the second substrate, wherein the first groove and the second groove are trapezoidal columns, and the lower surface of each trapezoidal column protrudes out of the surface of the second substrate; filling the first groove and the second groove to form a first conductive structure and a second conductive structure; forming a second supporting structure on the first conductive structure and the second conductive structure, and forming a third capacitor hole and a fourth capacitor hole in the second supporting structure, wherein the bottom surface of the third capacitor hole is connected with the lower surface of the first conductive structure, the bottom surface of the fourth capacitor hole is connected with the lower surface of the second conductive structure, the width of the bottom surface of the third capacitor hole is smaller than the opening width of the third capacitor hole, and the width of the bottom surface of the fourth capacitor hole is smaller than the opening width of the fourth capacitor hole; forming a third supporting structure on the second supporting structure, etching the third supporting structure to form a fifth capacitor hole and a sixth capacitor hole, wherein the bottom surface of the fifth capacitor hole is communicated with the opening of the third capacitor hole to form a first electrode groove containing the third capacitor hole and the fifth capacitor hole, the bottom surface of the sixth capacitor hole is communicated with the opening of the fourth capacitor hole to form a second electrode groove containing the fourth capacitor hole and the sixth capacitor hole, the junction of the fifth capacitor hole and the third capacitor hole is provided with a corner, and the junction of the sixth capacitor hole and the fourth capacitor hole is provided with a corner; sequentially depositing a first conductive layer, a capacitance medium layer and a second conductive layer on the surfaces of the first electrode groove and the second electrode groove to form an upper electrode, a capacitance medium layer and a lower electrode of the first capacitor and the second capacitor; grinding the second conductive layer to expose the capacitance dielectric layer, sequentially forming a first insulation structure and a second insulation structure on the capacitance dielectric layer, and forming a first through hole and a second through hole with surfaces exposed out of the second conductive layer in the first insulation structure and the second insulation structure; and after widening the parts of the first through hole and the second through hole, which are positioned in the second insulating structure, filling the first through hole and the second through hole to form a third contact pad and a fourth contact pad, wherein the third contact pad is used for connecting the first contact pad, and the fourth contact pad is used for connecting the second contact pad.

According to the embodiment of the disclosure, the columnar structure is cut, and double memory cells are manufactured on one bit line, so that the density of the memory cells can be greatly improved, and the volume of the memory can be reduced under the same number of the memory cells.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are only a few embodiments of the present disclosure and that other drawings may be derived from these drawings without the exercise of inventive faculty.

Fig. 1 is a schematic structural view of a semiconductor structure in an exemplary embodiment of the present disclosure.

Fig. 2 is a perspective view of the semiconductor structure 100 shown in fig. 1 in one embodiment of the present disclosure.

Figure 3 is a schematic cross-sectional view of a semiconductor structure 100 in one embodiment of the present disclosure.

Fig. 4 is a method of manufacturing the semiconductor structure shown in fig. 1-3.

Fig. 5A to 5J are schematic views of step S2.

Fig. 6A to 6D are schematic views of step S3.

Fig. 7A to 7E are schematic views of step S4.

Fig. 8A to 8H are schematic views of step S5.

Fig. 9A to 9E are schematic views of step S6.

Fig. 10A and 10B are schematic views of a process for fabricating a capacitor in one embodiment of the present disclosure.

Fig. 11A to 11H are schematic views of a process for fabricating a capacitor according to another embodiment of the present disclosure.

Fig. 12 is a schematic diagram of wafer bonding effect in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will recognize that the aspects of the present disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities, not necessarily corresponding to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural view of a semiconductor structure in an exemplary embodiment of the present disclosure. Fig. 2 is a schematic perspective view of the semiconductor structure 100 shown in fig. 1.

Referring to fig. 1, a semiconductor structure 100 may include:

a first substrate 1 and bit lines 2 formed on the first substrate 1, the bit lines 2 extending in a first direction, the plurality of bit lines 2 being parallel in a second direction, the second direction being perpendicular to the first direction;

a pillar structure 3 extending in a third direction, one end of the pillar structure 3 adjacent to the first substrate 1 being electrically connected to the bit line 2, wherein the pillar structure 3 includes a first active region 31 and a second active region 32 which are not connected to each other, and the third direction is perpendicular to both the first direction and the second direction;

An isolation structure 4, the isolation structure 4 being located between the first active region 31 and the second active region 32, wherein the isolation structure 4 extends in the second direction;

a first word line 51 and a second word line 52, the first word line 51 being attached to the first active region 31, the second word line 52 being attached to the second active region 32, wherein the first word line 51 and the second word line 52 each extend in a second direction;

the first capacitor 61 is electrically connected to the first active region 31, and the second capacitor 62 is electrically connected to the second active region 32.

Shown in fig. 1 is a top view of a semiconductor structure 100.

Referring to fig. 1 and 2, in the embodiment of the present disclosure, the height of the isolation structure 4 is greater than the height of the first active region 31 and the second active region 32 (see left side of fig. 2) to completely divide the first active region 31 and the second active region 32. Adjacent first and second word lines 51 and 52 belonging to different pillar structures are separated by a fourth insulating layer 45 (see fig. 1), wherein the right view of fig. 2 is a schematic diagram of the structure of the isolation structure 4, the first active region 31, the second active region 32, the first word line 51 and the second word line 52 in the left view of fig. 2 in a top view.

In the embodiment shown in fig. 1 and 2, the cylindrical structure 3 is a cylindrical structure, one surface of the first active region 31, which is attached to the isolation structure 4, is a plane, and one surface of the first active region, which is away from the isolation structure 4, is an arc surface; the surface of the second active region 32, which is attached to the isolation structure 4, is a plane, and the surface, which is away from the isolation structure 4, is a cambered surface. Meanwhile, the first word line 51 and the second word line 52 wrap the first active region 31 and the second active region 32, respectively, and are attached to the isolation structure 4. The first word line 51 and the second word line 52 are generally in the same orientation as the isolation structure 4 (extending in the second direction), and are separated from the isolation structure 4 only when pillar structures 3 are involved. The outer surface of the semicircular active region is beneficial to reducing the length of word lines and improving the signal transmission quality, and meanwhile, the edge spacing between the current memory cell and other memory cells is increased under the condition of unchanged size, so that technical guarantee is provided for improving the element density.

In another embodiment, the columnar structure 3 is a square columnar structure, one surface of the first active region 31, which is attached to the isolation structure 4, is a plane, and three surfaces, which are not attached to the isolation structure 4, are all planes; one surface of the second active region 32, which is attached to the isolation structure 4, is a plane, and three surfaces, which are not attached to the isolation structure 4, are all planes. When the columnar structure 3 is a square columnar structure, the first active region 31 and the second active region 32 have relatively larger volumes, have more carriers, and have better conduction effect. Meanwhile, each active region and the word line have larger contact area, which is beneficial to improving the quality of the gate control signal.

In other embodiments, the pillar structures 3 may take other forms as long as the active region function is achieved.

In the embodiment shown in fig. 1 and 2, by using the isolation structure 4 to cut the pillar structure 3 into the first active region 31 and the second active region 32 that are not connected, and implementing the word line connection using the first word line 51 connected to the first active region 31 and the second word line 52 connected to the second active region 32, two complete active regions can be fabricated in a conventional VGT structure space, each of which includes a drain connected to the bit line 2, a source connected to the capacitor (first capacitor 61 or second capacitor 62), and a channel region connected to the word line (first word line 51 or second word line 52), as compared with the related art in which one complete active region is connected to one word line.

The shapes of the first capacitor 61 and the second capacitor 62 in fig. 1 and 2 are only schematic, and in practical applications, the first capacitor 61 and the second capacitor 62 may have other shapes.

Referring to fig. 3, looking at only the non-capacitive portion, the semiconductor structure 100, seen from a cross-sectional view cut along a first direction (left side of fig. 3) and from a cross-sectional view cut along a second direction (right side of fig. 3), includes, in addition to the regions shown in fig. 1, 2:

a first insulating layer 33 (see right side of fig. 3), the first insulating layer 33 being located between the bit line 2 and the first word line 51 and between the bit line 2 and the second word line 52 (see left side of fig. 3) in the third direction;

a second insulating layer 34, the second insulating layer 34 being located above the first word line 51 and the second word line 52 in the third direction;

a third insulating layer 35 located over the columnar structures 3 and the second insulating layer 34;

a support layer 36 located above the third insulating layer 35;

the first contact pad 65, in the third direction, the lower end of the first contact pad 65 is electrically connected to the first active region 31;

and a second contact pad (not shown) having a lower end electrically connected to the second active region 32 in the third direction, wherein the first contact pad 65 and the second contact pad penetrate the third insulating layer 35 and the support layer 36.

Wherein the first insulating layer 33 is used to isolate the word lines from the bit lines. In one embodiment, the first insulating layer 33 includes a first sub-insulating layer 331 and a second sub-insulating layer 332, with a first air gap 300 formed between the first sub-insulating layer 331 and the second sub-insulating layer 332. The provision of the first air gap 300 enables better isolation between the word line and the bit line to obtain a lower dielectric constant, thereby reducing parasitic capacitance and improving the insulating effect of the first insulating layer 33 without increasing the cost.

The second insulating layer 34 is used to isolate the upper half of the adjacent pillar structures 3 to improve the isolation effect between the adjacent pillar structures.

The third insulating layer 35 serves to isolate the upper portions of adjacent isolation structures 4. Because the height of the isolation structure 4 is greater than the heights of the first active region 31 and the second active region 32 so as to completely divide the first active region 31 and the second active region 32, the uppermost layer portion of the adjacent isolation structure 4 along the third direction has no other functional region, and the third insulating layer 35 can isolate and wrap the heightened isolation structure 4, so that the structural strength of the isolation structure 4 is improved.

Further, the fourth insulating layer 45 is used to divide the first word line 51 and the second word line 52 belonging to different pillar structures 3.

The support layer 36 is provided to accommodate the first contact pad 65 and the second contact pad, and structural strength of the first contact pad 65 and the second contact pad can be improved by etching grooves into the support layer 36 and the third insulating layer 35 and filling the grooves to form the first contact pad 65 and the second contact pad. Meanwhile, the support layer 36 combines with the third insulating layer 35 to play a role of isolating the first contact pad 65 and the second contact pad.

The first contact Pad 65 and the second contact Pad are Landing pads, i.e., pedestals for bonding capacitors in a subsequent process. In the embodiment of the present disclosure, the first contact pad 65 and the second contact pad are, for example, in a shape of a lower narrow upper wide, i.e., connected to the first active region 31 or the second active region 32 through a smaller lower surface to achieve connection with the upper surface of the smaller active region at a high element density; in addition, by connecting the first capacitor 61 or the second capacitor 62 to the larger upper surface, the conductive area of the capacitor substrate can be increased, allowing a capacitor with a larger cross section to be provided, and reducing the limitation of the capacitor volume at a high element density.

As seen in connection with fig. 1 and 2, in the disclosed embodiments, to reduce the volume limitations on the first and second capacitances 61 and 62, the first and second capacitances 61 and 62 are not aligned in the first direction, but are staggered. Therefore, the first capacitor 61 and the second capacitor 62, and the first contact pad 65 and the second contact pad corresponding to the first capacitor 61 and the second capacitor 62, respectively, cannot be simultaneously shown in the same cross section in fig. 3.

With continued reference to fig. 3, in one embodiment, the isolation structure 4 includes a second air gap 400. The provision of the second air gap 400 helps to isolate adjacent first and second word lines 51 and 52, and adjacent (belonging to the same pillar structure 3) first and second active regions 31 and 32, reducing parasitic capacitance. In other exemplary embodiments, the second air gap 400 may be absent.

The fabrication process and detail features of the semiconductor structure 100 provided by the present disclosure are described in detail below with respect to method embodiments.

Referring to fig. 4, a method 400 of fabricating a semiconductor structure may include:

step S1, providing a first substrate 1;

step S2, a plurality of bit lines 2 are manufactured on the first substrate 1, the plurality of bit lines 2 extend along a first direction and are arranged in parallel in a second direction, and the second direction is perpendicular to the first direction;

step S3, manufacturing a cylindrical structure 3 on the bit line 2, wherein the cylindrical structure 3 extends along a third direction, and the third direction is perpendicular to the first direction and the second direction;

step S4, manufacturing an isolation structure 4 in the columnar structure 3, wherein the isolation structure 4 extends along a second direction, and cutting the columnar structure 3 into a first active region 31 and a second active region 32 which are not connected;

Step S5, forming a first word line 51 attached to the first active region 31 and a second word line 52 attached to the second active region 32, wherein the first word line 51 and the second word line 52 extend along a second direction, and a part attached to the isolation structure 4 exists in the second direction;

in step S6, a first capacitor 61 connected to the first active region 31 and a second capacitor 62 connected to the second active region 32 are formed.

Fig. 5A to 5J are schematic views of step S2.

First, the left side of the following figures are all sectional views cut along the first direction, and the right side is all sectional views cut along the second direction. If the plan view is taken, the plan view is taken on the left side and is represented by the plan view of the left side drawing, and the plan view is taken on the right side and is represented by the plan view of the right side drawing.

Referring to fig. 5A, first an oxide layer 11 and a nitride layer 12 may be deposited on a first substrate 1. Illustratively, the material of the first oxide layer 11 comprises silicon oxide (SiO 2) and the material of the nitride layer 12 comprises silicon nitride (SiN).

Referring to fig. 5B, a first photoresist layer 13 is coated on the nitride layer 12, and a first etching window 14 extending in a first direction is etched through a mask on the first photoresist layer 13 as a positioning window of a shallow trench isolation structure (Shallow Trench Isolation, STI), the bottom of the first etching window 14 exposing the nitride layer 12.

Referring to fig. 5C, a first groove 15 extending in a first direction is etched to the first substrate 1 with the aid of a first etching window 14.

Referring to fig. 5D, the first photoresist layer 13 is removed, oxide is deposited such that the first trench 15 is filled with oxide, forming a shallow trench isolation structure 16.

Referring to fig. 5E, the excess oxide is removed by a CMP (Chemical-Mechanical Polish, chemical mechanical polishing) process.

Referring to fig. 5F, the nitride layer 12 serving as a sacrificial layer (SAC) is removed, exposing the planarized first oxide layer 11 and the upper surface of the shallow trench isolation structure 16.

Referring to fig. 5G, a second photoresist layer 17 is coated on the first oxide layer 11, and a second etching window 18 extending along the first direction is etched through a mask as a bit line alignment window, the bottom of the second etching window 18 exposing the first oxide layer 11.

Referring to fig. 5H, the first oxide layer 11 is etched through the second etching window 18 to form a second trench 19, and the bottom of the second trench 19 is exposed to the first substrate 1.

Referring to fig. 5I, the first substrate 1 exposed to the bottom of the second trench 19 is ion-implanted through the second trench 19 to form the bit line 2.

Referring to fig. 5J, the second photoresist layer 17 and the first oxide layer 11 are removed, exposing the flat upper surfaces of the bit lines 2 and the shallow trench isolation structures 16.

Thus, the fabrication of the plurality of bit lines 2 on the first substrate 1 is completed. In another embodiment of the present disclosure, in addition to forming the bit line 2 by ion implantation, the first oxide layer 11 and the first substrate 1 may be etched with the aid of the second etching window 18 to form a bit line trench penetrating into the first substrate 1 and filling the bit line trench to form the bit line 2, which is not particularly limited in the embodiment of the present disclosure.

Fig. 6A to 6D are schematic views of step S3.

Referring to fig. 6A, a thin film stack structure is formed on the first substrate 1, on which the fabrication of the bit line 2 and the shallow trench isolation structure 16 has been completed, the thin film stack structure including a first insulating layer 33, a first sacrificial layer 39, and a second insulating layer 34, wherein the first sacrificial layer 39 is located between the first insulating layer 33 and the second insulating layer 34. The material of the first sacrificial layer 39 is, for example, nitride. The first insulating layer 33 includes a first sub-insulating layer 331 and a second sub-insulating layer 332, and a second sacrificial layer 333 between the first sub-insulating layer 331 and the second sub-insulating layer 332, and the material of the second sacrificial layer 333 is, for example, polysilicon.

The first sacrificial layer 39 is used to fabricate the word line, the second sacrificial layer 333 is used to fabricate the first gap 300, and the second sacrificial layer 333, the first sub-insulating layer 331, and the second sub-insulating layer 332 may not be provided, and only the integrated first insulating layer 33 may be provided.

The materials of the first insulating layer 33 (the first sub insulating layer 331 and the second sub insulating layer 332) and the second insulating layer 34 may be, for example, oxides.

Referring to fig. 6B, a third photoresist layer 21 is coated on the second insulating layer 34, and a third etching window 22 is manufactured through a mask, the second insulating layer 34 is exposed at the bottom of the third etching window 22, and the third etching window 22 is used to position the pillar structures 3.

Referring to fig. 6C, the thin film stack structure is etched through the third etching window 22 to form a third groove 23 penetrating the thin film stack structure, and the bottom of the third groove 23 exposes the bit line 2. Then, the third photoresist layer 21 is removed.

Referring to fig. 6D, a source 24, a channel region 25, and a drain 26 are formed in the third trench 23 in a stacked arrangement, the source 24, the channel region 25, and the drain 26 to constitute the pillar structure 3. The process of forming the source 24, the channel region 25 and the drain 26 may be, for example, deposition, doping, ion implantation, etc., which is not particularly limited in this disclosure.

Fig. 7A to 7E are schematic views of step S4.

Referring to fig. 7A, silicon dioxide is deposited on the pillar structures 3 to form a third insulating layer 35, the third insulating layer 35 being used to form a sidewall surrounding the isolation structures 4. Then, a fourth photoresist layer 41 is coated on the third insulating layer 35 to form a fourth etching window 42 extending in the second direction by etching the fourth photoresist layer 41.

Referring to fig. 7B, a fourth trench 43 is formed through the fourth etching window 42, and the bottom of the fourth trench 43 exposes the bit line 2. The height of the fourth groove 43 in the third direction is greater than the height of the columnar structure 3 in the third direction.

Referring to fig. 7C, for depositing the second oxide layer 44 on the inner surface of the fourth trench 43, the second oxide layer 44 may be formed by a physical vapor deposition Process (PVD) or a chemical vapor deposition process (CVD), wherein the second oxide layer 44 is also deposited on the third insulating layer 35, for example.

Referring to fig. 7D, the fourth trench 43 is filled with a low dielectric coefficient material (low K) to form the isolation structure 4, and the height of the isolation structure 4 in the third direction is greater than the height of the pillar structure 3 in the third direction. In one embodiment, the second air gap 400 may be fabricated in the isolation structure 4 to enhance the isolation effect of the isolation structure 4.

Referring to fig. 7E, the fabrication of the isolation structure 4 is completed by the CMP process Cheng Moping over the second oxide layer 44. In some embodiments, the second oxide layer 44 may also be removed during the planarization process, and the top of the third insulating layer 35 may be planarized to complete the fabrication of the isolation structure 4.

Fig. 8A to 8H are schematic views of step S5.

Referring to fig. 8A, a fifth photoresist layer 53 is deposited over the second oxide layer 44 and a fifth etch window 54 is made.

Referring to fig. 8B, a fifth trench 55 is etched between adjacent two pillar structures 3, a bottom of the fifth trench 55 exposes the bit line 2, and sidewalls of the fifth trench 55 expose the first sacrificial layer 39, wherein the fifth trench 55 extends in the second direction.

In another embodiment, the first insulating layer 33 includes a first sub-insulating layer 331 and a second sub-insulating layer 332, and the thin film stack structure further includes a second sacrificial layer 333, the second sacrificial layer 333 being located between the first sub-insulating layer 331 and the second sub-insulating layer 332, and the sidewalls of the fifth trench 55 exposing the first sacrificial layer 39 and the second sacrificial layer 333 as shown in fig. 8B.

Referring to fig. 8C, the first sacrificial layer 39 is removed using the fifth trench 55 as a window, forming a filling region 56.

Referring to fig. 8D, before filling the conductive material in the filling region 56, a portion of the sidewalls of the first active region 31 and a portion of the sidewalls of the second active region 32 exposed to the filling region may be subjected to an oxidation process to form a first gate oxide dielectric layer 57 and a second gate oxide dielectric layer 58, respectively.

Referring to fig. 8E, a conductive material is filled in the filling region 56 to form an initial conductive layer 59 filling the fifth trench 55.

Referring to fig. 8F, a portion of the initial conductive layer 59 located in the fifth trench 55 is removed, forming a first word line 51 that conforms to the first active region 31 and a second word line 52 that conforms to the second active region 32. The first word line 51 and the second word line 52 are part of an initial conductive layer 59.

Referring to fig. 8G, when the first insulating layer 33 includes the first sub-insulating layer 331 and the second sub-insulating layer 332, the first air gap 300 may be further fabricated, that is, after forming the first word line 51 and the second word line 52, further including: the second sacrificial layer 333 is removed with the fifth trench 55 as a window, and the first air gap layer 301 is formed.

Referring to fig. 8H, the fifth groove 55 is filled with an insulating medium to form the fourth insulating layer 45, and when the first insulating layer 33 includes the first sub-insulating layer 331 and the second sub-insulating layer 332, the first air gap 300 may be formed through the first air gap layer 59 when the insulating medium is filled. The fourth insulating layer 45 is used to isolate adjacent word lines belonging to different semiconductor structures 100.

Thus, the fabrication of the structure associated with the active region is completed.

Fig. 9A to 9E are schematic views of step S6.

Referring to fig. 9A, a support layer 36 is formed on the third insulating layer 35. The material of the support layer 36 is, for example, silicon nitride (Si ₃ N ₄ )。

Referring to fig. 9B, a first contact hole 63 and a second contact hole (not shown) penetrating the support layer 36 and the third insulating layer 35 are formed, wherein the first contact hole 63 exposes the first active region 31 and the second contact hole exposes the second active region 32. The second cross-sectional view in fig. 9B and the second cross-sectional view in fig. 9A are second cross-sectional views at different positions in the semiconductor structure, that is, the second cross-sectional view in fig. 9A is a cross-sectional view at i-i ', and the second cross-sectional view in fig. 9B is a cross-sectional view at ii-ii'.

Referring to fig. 9C, the upper half of the first contact hole 63 is further widened, forming a first contact hole 63 having a wide upper portion and a narrow lower portion. The second contact hole is similarly not shown.

Referring to fig. 9D, the first contact hole 63 is filled with a conductive material.

Referring to fig. 9E, an upper surface of the conductive material is manufactured Cheng Moping by CMP to form a first contact pad 65 filling the first contact hole 63, and a second contact pad (not shown) filling the second contact hole is formed.

The capacitor is then completed.

In one embodiment, the columnar capacitors may be fabricated directly on the support layer 36, as in the embodiment shown in fig. 10A-10B. In another embodiment, the capacitor may also be fabricated by a bonding process or the like.

Referring to fig. 10A, a first support structure 67 is formed on the support layer 36, and then a first capacitor hole 68 and a second capacitor hole (not shown) are formed through the first support structure 67, wherein a bottom of the first capacitor hole 68 exposes the first contact pad 65 and a bottom of the second capacitor hole exposes the second contact pad.

Referring to fig. 10B, a first capacitor 61 is formed in the first capacitor hole 68, and a second capacitor 62 is formed in the second capacitor hole.

Although the detailed structures of the first capacitor 61 and the second capacitor 62 are not shown, it is understood that each of the first capacitor 61 and the second capacitor 62 may include an upper electrode, a dielectric layer, and a lower electrode, each of the upper electrode and the lower electrode being a conductive material, the dielectric layer being located between the upper electrode and the lower electrode. The embodiments of the present disclosure are not limited to the specific form of the first capacitor 61 and the second capacitor 62.

Instead of directly manufacturing the capacitor based on the wafer on which the first substrate is located, in an embodiment, the capacitor may be manufactured based on another wafer (capacitor wafer), and the manufactured capacitor wafer is bonded on the semiconductor structure corresponding to the first substrate, so as to electrically connect the first capacitor 61 and the first contact pad 65, and electrically connect the second capacitor and the second contact pad.

The process specifically may include: a second substrate is provided, and a first capacitor and a second capacitor are fabricated on the second substrate to form a capacitor wafer, and then the capacitor wafer is bonded to the support layer 36 such that the first capacitor 61 is electrically connected to the first contact pad 65, and the second capacitor is electrically connected to the second contact pad. The second substrate corresponds to the capacitor wafer, and the capacitor wafer and the wafer where the first substrate is located are not the same wafer.

The electric connection of the capacitor and the transistor is realized by using a wafer bonding mode, so that capacitors with various forms can be manufactured, and the capacitance performance in the memory cell is improved.

The fabrication of the first capacitor and the second capacitor on the second substrate can be referred to as the embodiment shown in fig. 11A to 11H.

Referring to the left side of fig. 11A, a first groove 81 and a second groove (not shown) are etched on the second substrate 701, the first groove 81 and the second groove each being a trapezoid pillar, a lower surface of the trapezoid pillar protruding from a surface of the second substrate 701. Specifically, the first isolation layer 702 and the second isolation layer 703 may be sequentially deposited on the second substrate 701 first, and then the first groove 81 with the bottom exposed to the second substrate 701 may be formed by etching the second isolation layer 703, the first isolation layer 702, and the second substrate 701. The first recess 81 is a trapezoidal cylinder, for which the smaller bottom surface is the upper surface and the larger bottom surface is the lower surface. The upper surface of the first groove 81 in the second substrate 701 is smaller and the lower surface parallel to the second isolation layer 703 is larger. The first recess 81 and the second recess may also be referred to as upper electrode external holes.

In one embodiment, the material of the first isolation layer 702 is, for example, silicon dioxide, and the material of the second isolation layer 703 is, for example, silicon nitride.

Referring to the right side of fig. 11A, next, the first and second grooves 81 and 81 may be filled with a conductive material to form first and second conductive structures 82 and (not shown). The conductive material is, for example, tungsten (W).

Referring to the left side of fig. 11B, after the excessive conductive material is polished by the CMP process, a second support structure 71 (including a third isolation layer 704, a fourth isolation layer 705 and a fifth isolation layer 706) is formed on the first conductive structure 82 and the second conductive structure, and a third capacitor hole 83 and a fourth capacitor hole (not shown) are etched in the second support structure 71, wherein a bottom surface of the third capacitor hole 83 is connected to a lower surface of the first conductive structure 82, a bottom surface of the fourth capacitor hole is connected to a lower surface of the second conductive structure, wherein a bottom surface width of the third capacitor hole 83 is smaller than an opening width of the third capacitor hole 83, and a bottom surface width of the fourth capacitor hole is smaller than an opening width of the fourth capacitor hole. The material of the third isolation layer 704 and the fifth isolation layer 706 is, for example, silicon nitride, and the material of the fourth isolation layer 705 is, for example, silicon dioxide.

Referring to the right side of fig. 11B, third and fourth capacitor holes 83 and (not shown) are filled and passed through CMP process Cheng Moping to form first and second sacrificial structures 84 and (not shown). The filling material is, for example, polysilicon and the filling means is, for example, deposition. The first sacrificial structure 84 and the second sacrificial structure function to provide a plane for a subsequent deposition process.

Referring to the left side of fig. 11C, a third support structure 72 (including a sixth isolation layer 707 and a seventh isolation layer 708) is formed on the second support structure 71, and a fifth capacitor hole 85 and a sixth capacitor hole (not shown) are etched in the third support structure 72. The material of the sixth isolation layer 707 is, for example, silicon dioxide, and the material of the seventh isolation layer 708 is, for example, silicon nitride.

Referring to the right side of fig. 11C, the first sacrificial structure 84 and the second sacrificial structure are removed, so that the bottom surface of the fifth capacitor hole 85 is penetrated with the opening of the third capacitor hole to form a first electrode slot 86 including the third capacitor hole and the fifth capacitor hole, and the bottom surface of the sixth capacitor hole is penetrated with the opening of the fourth capacitor hole to form a second electrode slot (not shown) including the fourth capacitor hole and the sixth capacitor hole, wherein the junction of the fifth capacitor hole and the third capacitor hole has a corner, and the junction of the sixth capacitor hole and the fourth capacitor hole has a corner.

Referring to the left and right sides of fig. 11D, a first conductive layer 91, a capacitance medium layer 92, and a second conductive layer 93 are sequentially deposited on the surfaces of the first electrode slot 86 and the second electrode slot to form upper electrodes, capacitance medium layers, and lower electrodes of the first capacitor and the second capacitor. When the junction of the fifth capacitor hole and the third capacitor hole is provided with a corner, and the junction of the sixth capacitor hole and the fourth capacitor hole is provided with a corner, the relative area between the capacitor dielectric layer and the upper electrode and the lower electrode can be increased, so that the storage capacity can be improved. In the embodiment shown in fig. 11D, the second conductive layer 93 does not completely fill the first electrode groove 86, and a void surrounded by the second conductive layer 93 is also formed in the first electrode groove 86. In other embodiments, the second conductive layer 93 may also completely fill the first electrode trench 86, i.e. no void exists in the first electrode trench 86. The material of the first conductive layer 91 and the second conductive layer 93 is, for example, metal, and tungsten is exemplified. The material of the capacitance dielectric layer 92 is HK (high dielectric coefficient) material.

Referring to the left side of fig. 11E, after CMP polishing is performed on the second conductive layer 93, the capacitor dielectric layer 92 is exposed. A first insulating structure 73 and a second insulating structure 74 are sequentially formed on the capacitor dielectric layer 92, wherein the first insulating structure 73 may include an eighth insulating layer 709 and a ninth insulating layer 710, the second insulating structure 74 may include a tenth insulating layer 711 and an eleventh insulating layer 712, a material of the eighth insulating layer 709 and the tenth insulating layer 711 may be, for example, silicon nitride, and a material of the ninth insulating layer 710 and the eleventh insulating layer 712 may be, for example, silicon dioxide. The first conductive layer 91, the capacitor dielectric layer 92 and the second conductive layer 93 in the third capacitor hole are the first part of the first capacitor, the first conductive layer 91, the capacitor dielectric layer 92 and the second conductive layer 93 in the fifth capacitor hole are the second part of the first capacitor, and the connection part between the first part and the second part has an inflection point; similarly, the first conductive layer 91, the capacitor dielectric layer 92 and the second conductive layer 93 in the fourth capacitor hole are the first part of the second capacitor, the first conductive layer 91, the capacitor dielectric layer 92 and the second conductive layer 93 in the sixth capacitor hole are the second part of the second capacitor, and the connection part between the first part and the second part has an inflection point.

Referring to the right side of fig. 11E, first and second through holes 87 and (not shown) whose surfaces expose the second conductive layer 93 are formed in the first and second insulating structures 73 and 74.

Referring to the left side of fig. 11F, the portions of the first through-hole 87 and the second through-hole located in the second insulating structure 74 are widened.

Referring to the right side of fig. 11F, the first and second through holes 87 and 87 are filled with a conductive material to form first and second connection structures 94 and (not shown). The filled conductive material is for example tungsten metal.

Referring to the left side of fig. 11G, portions of the first and second connection structures 94 and 74 located in the second insulating structure 74 may be etched away using a wet etching (wet etching) method to form first and second connection structure holes 88 and (not shown).

Referring to the right side of fig. 11G, the first and second connection structure holes 88 and 88 are filled with a conductive material to form third and fourth connection structures (not shown). The conductive material is copper, for example.

Wherein the third connection structure 95 is connected to the first connection structure 94 to form a third contact pad, and the fourth connection structure is connected to the second connection structure to form a fourth contact pad. The third contact pad is used for connecting the first contact pad in the subsequent bonding process, and the fourth contact pad is used for connecting the second contact pad in the subsequent bonding process.

The third connection structure 95 is larger in volume than the first connection structure 94 and the fourth connection structure is larger in volume than the second connection structure, thereby providing a larger conductive area.

In one embodiment, the filling process may also be controlled to form recesses on the lower surfaces of the third connection structure 95 and the fourth connection structure as shown in fig. 11H, so as to avoid the conductive metal from overflowing due to backlog during the subsequent bonding process, thereby causing faults such as short circuit.

The capacitor shown in fig. 11A to 11H has an electrode with a large area, and thus the capacitance of the capacitor can be increased when the contact area with the transistor is limited.

Thus, the preparation of the capacitor wafer is completed. And bonding the capacitor wafer and the wafer where the first substrate is positioned through a bonding process.

Referring to fig. 12, in a semiconductor structure 1200, a first wafer 1201 provides a transistor structure, a second wafer 1202 provides a capacitor structure, and the transistor is connected to the capacitor through a bonding process to form the semiconductor structure shown in fig. 1.

The method for manufacturing the semiconductor structure can further reduce the line width of the active region, thereby increasing the storage capacity of the DRAM.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A semiconductor structure, comprising:

a first substrate and bit lines formed on the first substrate, the bit lines extending in a first direction, a plurality of the bit lines being parallel in a second direction, the second direction being perpendicular to the first direction;

The column structure extends in a third direction, one end of the column structure, which is close to the first substrate, is electrically connected with the bit line, wherein the column structure comprises a first active area and a second active area which are not connected with each other, and the third direction is perpendicular to the first direction and the second direction;

an isolation structure located between the first active region and the second active region, wherein the isolation structure extends along the second direction;

a first word line and a second word line, the first word line being attached to the first active region and the second word line being attached to the second active region, wherein the first word line and the second word line both extend in the second direction;

the first capacitor is electrically connected with the first active region, and the second capacitor is electrically connected with the second active region.

2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

a first insulating layer located between the bit line and the first word line and between the bit line and the second word line in a third direction;

A second insulating layer located above the first word line and the second word line in a third direction;

and the third insulating layer is positioned above the columnar structure and the second insulating layer.

3. The semiconductor structure of claim 1, wherein the isolation structure comprises a second air gap.

4. The semiconductor structure of claim 1, wherein the columnar structure is a cylindrical structure, a surface of the first active region contacting the isolation structure is a plane, and a surface facing away from the isolation structure is a cambered surface; the second active area is attached to one surface of the isolation structure, the surface, away from the isolation structure, of the second active area is a plane, and the surface, away from the isolation structure, of the second active area is an arc surface.

5. The semiconductor structure of claim 1, wherein the columnar structure is a square columnar structure, one surface of the first active region, which is attached to the isolation structure, is a plane, and three surfaces of the first active region, which are not attached to the isolation structure, are all planes; the second active area is attached to one surface of the isolation structure and is a plane, and the three surfaces which are not attached to the isolation structure are planes.

6. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises:

A support layer over the third insulating layer;

a first contact pad, wherein in the third direction, the lower end of the first contact pad is electrically connected with the first active region, and the upper end of the first contact pad is electrically connected with the first capacitor;

and the lower end of the second contact pad is electrically connected with the second active region in the third direction, and the upper end of the second contact pad is electrically connected with the second capacitor, wherein the first contact pad and the second contact pad penetrate through the third insulating layer and the supporting layer.

7. The semiconductor structure of claim 1, wherein a height of the isolation structure is greater than a height of the first active region and the second active region.

8. The semiconductor structure of claim 2, wherein the first insulating layer comprises a first sub-insulating layer and a second sub-insulating layer, wherein a first air gap is formed between the first sub-insulating layer and the second sub-insulating layer.

9. The semiconductor structure of claim 1, wherein the first capacitor and the second capacitor electrically connect the first active region and the second active region through a bonding process.

10. The semiconductor structure of claim 9, wherein the first capacitor and the second capacitor each comprise a first portion and a second portion, wherein a junction of the first portion and the second portion has an inflection point.

11. A method of fabricating a semiconductor structure, comprising:

providing a first substrate;

manufacturing a plurality of bit lines on the first substrate, wherein the plurality of bit lines extend along a first direction and are arranged in parallel in a second direction, and the second direction is perpendicular to the first direction;

manufacturing a cylindrical structure on the bit line, wherein the cylindrical structure extends along a third direction, and the third direction is perpendicular to the first direction and the second direction;

manufacturing an isolation structure in the columnar structure, wherein the isolation structure extends along the second direction, and cutting the columnar structure into a first active region and a second active region which are not connected;

forming a first word line attached to the first active region and a second word line attached to the second active region, wherein the first word line and the second word line extend along the second direction, and a part attached to the isolation structure exists in the second direction;

Forming a first capacitor electrically connected with the first active region and a second capacitor electrically connected with the second active region.

12. The method of manufacturing of claim 11, wherein the step of fabricating a plurality of bit lines on the first substrate comprises:

etching a first groove extending along the first direction on the first substrate, and filling the first groove to manufacture a shallow trench isolation structure;

etching a second groove extending along the first direction between two adjacent shallow groove isolation structures on the first substrate, wherein the bottom of the second groove is exposed out of the first substrate;

and performing ion implantation on the first substrate through the second groove to form the bit line.

13. The method of manufacturing of claim 11, wherein the step of fabricating a pillar structure on the bit line comprises:

forming a thin film stack structure on the first substrate, the thin film stack structure including a first insulating layer, a first sacrificial layer, and a second insulating layer, wherein the first sacrificial layer is located between the first insulating layer and the second insulating layer;

forming a third groove penetrating through the film stacking structure, wherein the bottom of the third groove exposes the bit line;

And forming a source electrode, a channel region and a drain electrode which are stacked in the third groove, wherein the source electrode, the channel region and the drain electrode form the columnar structure.

14. The method of manufacturing of claim 12, wherein the step of fabricating an isolation structure in the columnar structure comprises:

forming a third insulating layer on the columnar structure;

forming a fourth groove in the columnar structure, wherein the bottom of the fourth groove exposes the bit line, and the height of the fourth groove in the third direction is larger than that of the columnar structure in the third direction;

the fourth trench is filled to form the isolation structure.

15. The method of manufacturing of claim 11, wherein the isolation structure is formed with a second air gap extending in the second direction.

16. The method of manufacturing of claim 13, wherein the step of forming a first word line that is bonded to the first active region and a second word line that is bonded to the second active region comprises:

etching a fifth groove between two adjacent columnar structures, wherein the bottom of the fifth groove exposes the bit line, and the side wall of the fifth groove exposes the first sacrificial layer, and the fifth groove extends along the second direction;

Removing the first sacrificial layer by taking the fifth groove as a window to form a filling area;

filling conductive material in the filling area to form an initial conductive layer, wherein the initial conductive layer also fills the fifth groove;

removing part of the initial conductive layer in the fifth groove to form a first word line attached to the first active region and a second word line attached to the second active region;

after forming the first word line and the second word line, further comprising:

and filling the fifth groove with an insulating medium to form a fourth insulating layer.

17. The method of manufacturing of claim 13, wherein the first insulating layer comprises a first sub-insulating layer and a second sub-insulating layer, the thin film stack structure further comprising a second sacrificial layer between the first sub-insulating layer and the second sub-insulating layer, the step of forming a first word line that is bonded to the first active region and a second word line that is bonded to the second active region comprising:

etching a fifth groove between two adjacent columnar structures, wherein the bottom of the fifth groove exposes the bit line, and the side wall of the fifth groove exposes the first sacrificial layer and the second sacrificial layer, and the fifth groove extends along the second direction;

after forming the first word line and the second word line, further comprising:

removing the second sacrificial layer by taking the fifth groove as a window to form a first air gap layer;

and filling the fifth groove with an insulating medium to form a fourth insulating layer, and forming a first air gap through the first air gap layer.

18. The method of manufacturing of claim 16 or 17, wherein the fill region further exposes a portion of the sidewall of the first active region and a portion of the sidewall of the second active region, further comprising, prior to forming the first word line and the second word line:

and oxidizing part of the side wall of the first active region and part of the side wall of the second active region exposed to the filling region to form a first gate oxide dielectric layer and a second gate oxide dielectric layer respectively.

19. The method of manufacturing of claim 14, wherein the step of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region comprises:

forming a support layer on the third insulating layer;

forming a first contact hole and a second contact hole penetrating through the support layer and the third insulating layer, wherein the first contact hole exposes the first active region, and the second contact hole exposes the second active region;

forming a first contact pad filling the first contact hole, forming a second contact pad filling the second contact hole, wherein the first contact pad is used for connecting the first capacitor, and the second contact pad is used for connecting the second capacitor.

20. The method of manufacturing of claim 19, wherein the steps of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region further comprise:

forming a first support structure on the support layer;

forming a first capacitor hole and a second capacitor hole penetrating through the first supporting structure, wherein the bottom of the first capacitor hole exposes the first contact pad, and the bottom of the second capacitor hole exposes the second contact pad;

And forming a first capacitor in the first capacitor hole and forming a second capacitor in the second capacitor hole.

21. The method of manufacturing of claim 19, wherein the steps of fabricating a first capacitor connected to the first active region and a second capacitor connected to the second active region further comprise:

providing a second substrate;

manufacturing the first capacitor and the second capacitor on the second substrate to form a capacitor wafer;

bonding the capacitor wafer to the supporting layer so that the first capacitor is electrically connected with the first contact pad, and the second capacitor is electrically connected with the second contact pad.

22. The method of manufacturing of claim 21, wherein the fabricating the first capacitor and the second capacitor on the second substrate to form a capacitor wafer comprises:

etching a first groove and a second groove on the second substrate, wherein the first groove and the second groove are trapezoidal columns, and the lower surface of each trapezoidal column protrudes out of the surface of the second substrate;

filling the first groove and the second groove to form a first conductive structure and a second conductive structure;

forming a second supporting structure on the first conductive structure and the second conductive structure, and etching in the second supporting structure to form a third capacitor hole and a fourth capacitor hole, wherein the bottom surface of the third capacitor hole is connected with the lower surface of the first conductive structure, the bottom surface of the fourth capacitor hole is connected with the lower surface of the second conductive structure, the width of the bottom surface of the third capacitor hole is smaller than the opening width of the third capacitor hole, and the width of the bottom surface of the fourth capacitor hole is smaller than the opening width of the fourth capacitor hole;

Forming a third supporting structure on the second supporting structure, and etching a fifth capacitor hole and a sixth capacitor hole in the third supporting structure, wherein the bottom surface of the fifth capacitor hole is communicated with the opening of the third capacitor hole to form a first electrode groove containing the third capacitor hole and the fifth capacitor hole, the bottom surface of the sixth capacitor hole is communicated with the opening of the fourth capacitor hole to form a second electrode groove containing the fourth capacitor hole and the sixth capacitor hole, and a corner is arranged at the juncture of the fifth capacitor hole and the third capacitor hole and the juncture of the sixth capacitor hole and the fourth capacitor hole;

depositing a first conductive layer, a capacitance medium layer and a second conductive layer on the surfaces of the first electrode groove and the second electrode groove in sequence to form an upper electrode, a capacitance medium layer and a lower electrode of the first capacitor and the second capacitor;

grinding the second conductive layer to expose the capacitance dielectric layer, sequentially forming a first insulation structure and a second insulation structure on the capacitance dielectric layer, and forming a first through hole and a second through hole with surfaces exposed out of the second conductive layer in the first insulation structure and the second insulation structure;

And after widening the parts of the first through hole and the second through hole, which are positioned in the second insulating structure, filling the first through hole and the second through hole to form a third contact pad and a fourth contact pad, wherein the third contact pad is used for connecting the first contact pad, and the fourth contact pad is used for connecting the second contact pad.