CN117278356A

CN117278356A - Reusable and expandable CHI link layer router

Info

Publication number: CN117278356A
Application number: CN202311562565.4A
Authority: CN
Inventors: 印象; 王凯; 何震子; 毛晓炜
Original assignee: Cetc Shentai Information Technology Co ltd
Current assignee: Cetc Shentai Information Technology Co ltd
Priority date: 2023-11-22
Filing date: 2023-11-22
Publication date: 2023-12-22

Abstract

The invention discloses a multiplexing expandable CHI link layer router, and belongs to the field of communication. The input end of the input buffer module is connected with the output end of the corresponding host, and the output end is connected with the input ends of each arbitration module and each gating module; the input end of the arbitration module is connected with the output end of each input buffer module and the output end of the output buffer module, and the output end of the arbitration module is connected with the input end of the gating module; the input end of the gating module is connected with the output end of each input buffer module and the output end of the arbitration module, and the output end of the gating module is connected with the input end of the output buffer module; the input end of the output buffer module is connected with the output end of the gating module, and the output end is connected with the input end of the arbitration module and the input end of the slave. The invention mediates the bus right of use through the arbitration module, receives and responds to the request of the host computer for the right of occupation, and gives the right of use to the proper host computer, thereby ensuring the reasonable dynamic allocation of the right of request to each host computer.

Description

Reusable and expandable CHI link layer router

Technical Field

The invention relates to the technical field of communication, in particular to a multiplexing expandable CHI link layer router.

Background

The CHI (Coherent Hub Interface) protocol is the latest generation bus protocol proposed by ARM company, has the key characteristics of easy architecture expansion, independent layering realization, packet transmission and the like, and meets the requirements of ultra-high performance and complex design.

The CHI protocol can be functionally divided into: protocol layer (Protocol), network layer (Network), link layer (Link). The CHI channels have two directions of receiving and transmitting, and each direction corresponds to 3 channels. The transmission direction channel is REQ, WDA, RSP; the reception direction channel is ACK, RDA, SNP.

NOC technology (Network on Chip) is a communication scheme for solving the problem of data transmission between different cores, core and non-core hardware units in a multi-core system on Chip, and constructs an extensible on-Chip interconnection structure for each hardware unit on Chip.

The NOC generally adopts a complex topology structure with multiple masters and multiple slaves, and generally encounters the problems of poor reusability and expansibility, while because the physical channel structures of the che bus link layer have similarity, a reusable and expandable router is needed to effectively improve the design efficiency and reduce the hardware cost.

Disclosure of Invention

The invention aims to provide a multiplexing expandable CHI link layer router to solve the problems in the background technology.

In order to solve the technical problems, the invention provides a multiplexing expandable CHI link layer router, which comprises a bus authority control unit based on an input buffer module, an arbitration module, a gating module and an output buffer module, wherein:

the input end of the input buffer module is connected with the output end of the corresponding host, and the output end of the input buffer module is connected with the input ends of each arbitration module and each gating module;

the input end of the arbitration module is connected with the output end of each input buffer module and the output end of the output buffer module, and the output end of the arbitration module is connected with the input end of the gating module;

the input end of the gating module is connected with the output end of each input buffer module and the output end of the arbitration module, and the output end of the gating module is connected with the input end of the output buffer module;

the input end of the output buffer module is connected with the output end of the gating module, and the output end of the output buffer module is connected with the input end of the arbitration module and the input end of the slave;

the input buffer module is used for receiving input data of a corresponding host, disassembling a data packet and routing the data packet to the corresponding gating module according to the node address; and sending an operation request to the corresponding arbitration module;

the arbitration module is used for receiving a host authority request signal, dynamically distributing bus authorities according to the received request signal and sending a gating signal to the gating module;

the gating module is used for receiving the data packet of the corresponding host from the input buffer module according to the authority judged by the arbitration module and sending the data packet to the corresponding output buffer module;

the output buffer module is used for receiving output data of the corresponding gating module and sending the output data to the slave; and sending a back pressure signal to the arbitration module according to the state of the internal storage space.

In one embodiment, the dynamic allocation of bus permissions changes the bus permission allocation order in a ring every time the bus permissions change, and all hosts of the same priority will equally acquire bus ownership.

In one embodiment, the bus right allocation sequence changes in a ring, and the sequential polling mechanism is used for mediating bus right requests, allocating the right to use according to the request sequence, and treating equally to the hosts with the same priority.

In one embodiment, the CHI link layer routers are reusable, the CHI bus link layer physical channel structure has similarity, the NOC structure is split into 6 basic routers, the unique distinction of each router is the data bit width of the router, and the bit width of the CHI link layer corresponding to each router is determined.

In one embodiment, the CHI link layer router is scalable, supporting two or more master-slave machines.

The invention provides a multiplexing expandable CHI link layer router, which comprises an input buffer module, an arbitration module, a gating module and an output buffer module; the bus right of use is mediated through the arbitration module, the request of the host computer for the right of occupation is received and responded, and the right of use is given to the proper host computer, so that the reasonable dynamic allocation of the right of request of each host computer is ensured. Furthermore, the present CHI link layer router supports multiplexing due to the structural similarity of the lanes of the CHI bus link layer.

Drawings

Fig. 1 is a block diagram of a multiplexing expandable CHI link layer router according to the present invention.

FIG. 2 is a bus privilege status jump diagram of the present invention.

Detailed Description

The invention provides a reusable and expandable CHI link layer router which is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

In order to improve the reusability and expansibility of NOCs based on CHI buses, the invention provides a reusable and expandable CHI link layer router taking a REQ channel as an example.

The block diagram of the present invention is shown in fig. 1, and includes a host No. 0 101, a host No. 1 102, a first input buffer module 103, a second input buffer module 104, a first arbitration module 105, a second arbitration module 106, a first strobe module 107, a second strobe module 108, a first output buffer module 109, and a second output buffer module 110.

Specifically, the priority of host No. 0 101 and host No. 1 102 are the same.

The first input buffer module 103 receives data from the host No. 0 101, the second input buffer module 104 receives data from the host No. 1 102, the first input buffer module 103 disassembles the data packet, routes the data packet to the first strobe module 107 according to the node address, and the first input buffer module 103 sends an operation request to the first arbitration module 105; the second input buffer module 104 disassembles the data packet, routes it to the second strobe module 108 according to the node address, and the second input buffer module 104 sends an operation request to the second arbitration module 106.

The first arbitration module 105 and the second arbitration module 106 are used for mediating the bus use right; the arbitration module mediates requests sent by a plurality of hosts, receives and responds to the request of the occupying authority of the host, and gives the proper host with the using authority.

Taking the first arbitration module 105 as an example, according to the current state of the owner, the control is performed in a priority state machine mode; for the mediation of bus use right requests, a sequential polling mechanism is used, use right allocation is carried out according to the request sequence, and hosts with the same priority are treated equally.

The first arbitration module 105 has 2 states, i.e. "host No. 0 has bus control right" and "host No. 1 has bus control right", respectively, as shown in fig. 2. When the host 0 has the bus use right, the bus request priority order is that the host 0 is greater than the host 1. Host # 0 may be licensed if it requires continued bus use.

And when the host No. 0 releases the bus and the host No. 1 requests the bus, the bus use right is given to the host No. 1. If all hosts do not request use of the bus, the current state is maintained.

Similarly, when host No. 1 holds the bus usage right, the priority order is "host No. 1 > host No. 0"; as the priority of the bus authority changes in a ring shape every time the bus authority changes, all hosts with the same priority can equally acquire the bus ownership.

The first gating module 107 and the second gating module 108 respectively buffer the permissions determined by the first arbitration module 105 and the second arbitration module 106, respectively receive corresponding data packets from the first input buffer module 103 or the second input buffer module 104, and respectively send the corresponding data packets to the first output buffer module 109 and the second output buffer module 110;

the first output buffer module 109 and the second output buffer module 110 respectively receive the data from the first strobe module 107 and the second strobe module 108 and send the data to the slave; according to the internal memory space state, the back pressure signals are sent to the first arbitration module 105 and the second arbitration module 106 respectively.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. The utility model provides a multiplexing scalable CHI link layer router which characterized in that includes based on input buffer module, arbitration module, strobe module, output buffer module's bus permission control unit, wherein:

2. The reusable scalable CHI link layer router according to claim 1, wherein the dynamically assigned bus permissions change in a ring-like manner whenever the bus permissions change, and all of the same priority hosts acquire bus ownership equally.

3. The reusable scalable CHI link layer router according to claim 2, wherein the bus rights allocation order varies in a ring, and for mediation of bus rights requests, a sequential polling mechanism is used to allocate rights in the order of requests and treat equally prioritized hosts.

4. The multiplexing extensible che link layer router of claim 1, wherein the che link layer router is multiplexing, the che bus link layer physical channel structure has similarity, the NOC structure is split into 6 basic routers, the only difference of each router is the data bit width of the router, and the bit width of the che link layer corresponding to each router is determined.

5. The multiplexing-extensible CHI link layer router of claim 1, wherein the CHI link layer router is extensible and supports two or more master-slave machines.