CN117278100A - Service execution method, device and storage medium based on space-based information system - Google Patents

Service execution method, device and storage medium based on space-based information system Download PDF

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CN117278100A
CN117278100A CN202311227172.8A CN202311227172A CN117278100A CN 117278100 A CN117278100 A CN 117278100A CN 202311227172 A CN202311227172 A CN 202311227172A CN 117278100 A CN117278100 A CN 117278100A
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cpu
satellite node
data
npu
processed data
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CN117278100B (en
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薛宏亮
贾森泓
颜迪颖
李超
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Zhejiang Lab
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Zhejiang Lab
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851Systems using a satellite or space-based relay
    • H04B7/18513Transmission in a satellite or space-based system
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/14Relay systems
    • H04B7/15Active relay systems
    • H04B7/185Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851Systems using a satellite or space-based relay
    • H04B7/18515Transmission equipment in satellites or space-based relays
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The specification discloses a service execution method, a device and a storage medium based on a space-based information system. The method comprises the following steps: a plurality of satellite nodes are arranged in the space-based information system, a pre-trained service model is deployed in each satellite node, and the satellite nodes acquire acquired image data aiming at each satellite node in the space-based information system; preprocessing image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data; transmitting the processed data to a central processing unit CPU arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural network processor NPU arranged in the satellite node through the CPU; respectively executing calculation tasks aiming at the service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model; and executing the target service according to the output result.

Description

Service execution method, device and storage medium based on space-based information system
Technical Field
The present disclosure relates to the field of satellite information processing technologies, and in particular, to a method and apparatus for executing a service based on a space-based information system, and a storage medium.
Background
With the vigorous development and the continuous deep application of various military and commercial satellites, the number of various satellites is increased continuously to meet the increasingly complex application demands of users, and simultaneously, new requirements are provided for timeliness and intellectualization of satellite system task processing. Low cost, high real-time, high intelligent satellite mission processing systems have become a trend.
However, the traditional satellite task processing system architecture is limited by a computing architecture and single-satellite computing capability, and is an architecture of a ground data center computing formula, a satellite acquires massive data, and the data needs to be downloaded to a ground data center for processing due to limited computing capability of the single satellite so as to achieve the purpose of user application requirements. Obviously, the architecture of the ground data center calculation formula needs to perform mass data transmission between the satellite and the ground, is limited by the communication rate of the satellite and the ground center, generates larger data transmission delay, and cannot meet the real-time processing scene requirement.
Therefore, how to ensure the efficiency of processing data, reduce the transmission delay, and meet the real-time processing scene requirement is a problem to be solved urgently.
Disclosure of Invention
The present disclosure provides a method, an apparatus, and a storage medium for executing a service based on a space-based information system, so as to partially solve the foregoing problems in the prior art.
The technical scheme adopted in the specification is as follows:
the present specification provides a service execution method based on a space-based information system, including:
aiming at each satellite node in the space-based information system, the satellite node acquires acquired image data;
preprocessing the image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data;
transmitting the processed data to a central processing unit CPU arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural network processor NPU arranged in the satellite node through the CPU;
respectively executing calculation tasks aiming at a service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model;
and executing the target service according to the output result.
Optionally, for each satellite node in the space-based information system, a first memory and a second memory are arranged in the satellite node, wherein the first memory comprises a memory, and the second memory comprises a flash memory;
the first memory is used for storing cache data generated by the CPU and the NPU in the process of executing the calculation task aiming at the service model;
The second memory is used for storing the output result.
Optionally, the image data is preprocessed through a field programmable gate array FPGA disposed in the satellite node, so as to obtain processed data, which specifically includes:
transmitting the image data to a defogging algorithm module in the FPGA so as to perform defogging processing on the image data through the defogging algorithm module to obtain processed data, and storing the processed data in a cache module outside the FPGA;
after the data control bus module inside the FPGA is monitored to generate an interrupt, the processed data in the cache module is transmitted to the CPU.
Optionally, the computing tasks for the service model are executed according to the respective corresponding processed data through the CPU and the NPU respectively, which specifically includes:
dividing the computing task into a first subtask and a second subtask through the CPU, and issuing the second subtask to the NPU;
executing the first subtask through the CPU, executing the second subtask through the NPU, executing the first subtask through the CPU according to the self-reserved processed data, and executing the second subtask through the NPU according to the received processed data.
Optionally, the CPU divides the computing task into a first subtask and a second subtask, and issues the second subtask to the NPU, which specifically includes:
and dividing the computing task into a first subtask and a second subtask according to at least one of task types, precision requirements and parallelism requirements related to different tasks in the process of executing the computing task by the CPU.
Optionally, the output result of the service model is obtained by executing a calculation task for the service model according to the respective corresponding processed data through the CPU and the NPU, which specifically includes:
executing the first subtask through the CPU to obtain a first execution result, executing the second subtask through the NPU to obtain a second execution result, executing the first subtask through the CPU according to the processed data reserved by the CPU to obtain a first execution result, and executing the second subtask through the NPU according to the received processed data to obtain a second execution result;
and integrating the first execution result and the second execution result to obtain the output result.
Optionally, for each satellite node in the space-based information system, training a service model in the satellite node specifically includes:
acquiring sample data;
preprocessing the sample data through an FPGA arranged in the satellite node to obtain processed sample data;
transmitting the processed sample data to a CPU disposed in the satellite node, so as to transmit at least part of the processed sample data to an NPU disposed in the satellite node through the CPU;
respectively executing training tasks aiming at the service model according to the respectively corresponding processed sample data through the CPU and the NPU to obtain target gradient information;
transmitting the target gradient information to each adjacent satellite node adjacent to the satellite node, and receiving the target gradient information transmitted by each adjacent satellite node;
and updating the model parameters of the service model according to the received target gradient information.
The present specification provides a service execution device based on a space-based information system, including:
the acquisition module is used for acquiring acquired image data aiming at each satellite node in the space-based information system;
The processing module is used for preprocessing the image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data;
the distribution module is used for transmitting the processed data to a Central Processing Unit (CPU) arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural Network Processor (NPU) arranged in the satellite node through the CPU;
the calculation module is used for executing calculation tasks aiming at the service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model;
and the execution module executes the target service according to the output result.
The present specification provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-described method of executing a service based on a space-based information system.
The present specification provides a satellite comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the above-mentioned method of service execution based on a space-based information system when executing the program.
The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:
in the service execution method based on the space-based information system provided by the specification, a plurality of satellite nodes are arranged in the space-based information system, a pre-trained service model is deployed in each satellite node, and the satellite nodes acquire acquired image data aiming at each satellite node in the space-based information system; preprocessing image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data; transmitting the processed data to a central processing unit CPU arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural network processor NPU arranged in the satellite node through the CPU; respectively executing calculation tasks aiming at the service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model; and executing the target service according to the output result.
According to the method, after the satellite in the day-based information system collects the image data, a series of processing and distribution can be carried out on the image data based on the FPGA, the CPU and the NPU of the satellite, so that the calculation efficiency of a service model is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings:
fig. 1 is a schematic flow chart of a service execution method based on a space-based information system provided in the present specification;
FIG. 2 is a schematic diagram of a distributed edge smart computing architecture provided herein;
fig. 3 is a schematic hardware structure of a satellite node provided in the present specification;
fig. 4 is a schematic hardware structure of an FPGA provided in the present specification;
FIG. 5 is a schematic diagram of a data flow within a satellite node provided in the present specification;
FIG. 6 is a schematic diagram of a distributed training process for a business model provided in the present specification;
fig. 7 is a schematic diagram of a service execution device based on the space-based information system provided in the present specification;
fig. 8 is a schematic view of an electronic device corresponding to fig. 1 provided in the present specification.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present specification will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.
Fig. 1 is a flow chart of a service execution method based on a space-based information system provided in the present specification, which includes the following steps:
s101: for each satellite node in the space-based information system, the satellite node acquires acquired image data.
In recent years, with the continuous development of aerospace technology, integrated circuit design production capacity and intelligent deep learning technology, the computing capacity and the intelligent degree of a single satellite are greatly improved. The computing unit on the satellite adopts a super-heterogeneous hardware architecture, so that strong computing power support is provided for intelligent satellite data processing; in-orbit applications for Commercial Shelf products (COTS) devices have also greatly reduced satellite costs. These techniques enable intelligent data processing at the satellite edge side. When the computing power of a single satellite cannot meet the computing power requirement of the deep learning model training, the distributed deep learning is performed by considering a plurality of satellites. These enable real-time and intelligent satellite mission processing systems.
Based on this, the present disclosure provides a service execution method based on a space-based information system, where the space-based information system is composed of a plurality of satellites with super-heterogeneous computing power resources, each satellite may correspond to one edge computing node of the space-based information system, that is, satellite nodes, where the satellite nodes form an edge computing power network on which distributed model training and reasoning is performed, so as to form a distributed edge intelligent computing architecture. For ease of understanding, the present description provides a distributed edge intelligent computing architecture schematic, as shown in fig. 2.
Fig. 2 is a schematic diagram of a distributed edge intelligent computing architecture provided in the present specification.
The service model corresponding to the service application can be a deep learning model, the deep learning model is deployed in each satellite node, and in the process of executing the calculation task, a single satellite node in the distributed edge intelligent calculation architecture calls the distributed parallel calculation framework, and then the plurality of satellite nodes perform real-time hybrid tasks.
Further, the present disclosure also provides a hardware structure schematic diagram of the satellite node, as shown in fig. 3.
Fig. 3 is a schematic hardware structure of a satellite node provided in the present specification.
Two groups of intelligent computing boards are arranged on a single satellite computing node, two groups of power boards and a back board are arranged in each group of intelligent computing boards, and a programmable gate array (Field Programmable Gate Array, FPGA), a central processing unit (Central Processing Unit, CPU) and an embedded Neural network processor (nerve-network Processing Units, NPU) are mutually connected through a high-speed PCIe bus to provide a high-speed low-delay data transmission channel.
The intelligent computing board card is used as the core of the computing node, adopts a 1+1 redundant fault-tolerant design, and ensures the reliability of the on-orbit operation of the node. The smart computing card provides hardware computing power support and corresponding storage support required for computing. The FPGA provides a data transmission interface matched with the load interface and a data preprocessing function; the CPU controls the data flow direction, schedules the task and provides certain computing power; the NPU is used as a hardware acceleration core device under the architecture, and can provide a calculation energy efficiency ratio of 1.5 Tops/W.
The FPGA and the NPU are connected with the CPU through a PCIe high-speed bus interface and are PCIe nodes serving as the CPU.
In addition, two memories, namely a first memory and a second memory, can be further arranged in the intelligent computing board, the first memory can be a high-speed memory and used for storing cache data generated in the computing process, and the second memory can be a flash memory and used for storing computing results, output results of the model and gradient information in the model training process.
The power supply board card is used for providing power for the intelligent computing board card, mainly converting a high-voltage primary side power supply into a 12V power supply, and supplying the power to the internal chips and circuits of the board card after the power supply board card is converted by the DC/DC power supply chip in the intelligent computing board card. The backboard board card provides a slot and a signal interconnection channel. The whole computing node accords with the VPX standard architecture.
All boards in the satellite node are based on COTS devices, so that the requirements of low cost and high reliability are met.
In the specification, each satellite node adopts a redundant fault-tolerant design, and a 1+1 redundant design mode is adopted for a core board intelligent computing board and a power board; adopting an on-orbit verified maturation scheme; the internal important module of the FPGA adopts a triple modular redundancy design; derating design is carried out strictly according to the GJB/Z35-93 highest grade; the hardware watchdog design is adopted to prevent the CPU from being halted due to the single event upset problem; FEMA analysis can be performed on the computing nodes and the board card in the design process, and weak links of reliability design in the nodes are identified and improved to a certain extent.
In practical applications, it is generally required to perform multiple services through images acquired by satellites in a space-based information system, for example, weather prediction is performed according to an air image acquired by the satellites (including a ground air image and a high-altitude air image), and real-time target recognition, target tracking, path navigation, etc. are performed according to the ground image acquired by the satellites.
Thus, in the process of executing the target service, a single satellite node can acquire image data through its own sensor.
S102: and preprocessing the image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data.
The CPU can run the parallel computing framework to schedule and manage heterogeneous computing resources, specifically, after the CPU runs the parallel computing framework, image data generated by the load firstly enter the FPGA through the data interface, and the FPGA preprocesses the original data to obtain processed data. The FPGA has the characteristics of programmability, high calculation parallelism and the like, can be matched with different interfaces of different load types, and realizes user-defined data preprocessing on image data.
Specifically, the FPGA can perform preprocessing of image data, such as image defogging, so that interference of mist in an optical remote sensing image on target observation in an imaging area is reduced as much as possible. The defogging algorithm is processed serially on a software platform, the real-time performance is low, the FPGA has the advantages of high calculation parallelism, low power consumption and the like, and is suitable for hardware acceleration of the defogging algorithm, and the real-time performance of the image defogging algorithm is improved. For ease of understanding, the present disclosure provides a schematic hardware structure of an FPGA, as shown in fig. 4.
Fig. 4 is a schematic hardware structure of an FPGA provided in the present specification.
The load image data can be received by the FPGA internal data receiving module through a specific interface, the internal data control bus module sends the received data to the defogging algorithm module, the defogging algorithm module transmits the processed image data to DDR particles outside the FPGA through the DDR controller module for data caching, then the internal data control bus module generates interruption, and the defogging processed image data in the external DDR particles is transmitted to the uplink CPU through the PCIe controller module.
S103: and inputting the processed data into a Central Processing Unit (CPU) arranged in the satellite node, and transmitting at least part of the processed data to an embedded neural Network Processor (NPU) arranged in the satellite node through the CPU.
After the FPGA finishes preprocessing a group of image data, an interrupt can be sent to inform the CPU, the processed data enters the CPU through the PCIe bus, and the CPU unloads the data to the NPU for calculation under the control of the parallel calculation framework.
That is, a part of data is reserved in the CPU and another part of data is transmitted to the NPU for calculation, where, because the CPU needs to perform more logic control tasks (such as controlling each PCIe node to perform data transceiving, data allocation, and data storage, etc.), the processed data transmitted to the NPU may be more than the processed data reserved by the CPU itself. Of course, the CPU may also transmit all of the processed data to the NPU for calculation. For ease of understanding, the present disclosure provides a schematic diagram of data flow within a satellite node, as shown in fig. 5.
Fig. 5 is a schematic diagram of a data flow in a satellite node provided in the present specification.
The data carrying process from the CPU to the NPU after the processing can be realized by a direct memory access (Direct Memory Access, DMA) mode, the mode effectively improves the data carrying bandwidth, releases the computing resources of the CPU and improves the data processing efficiency.
S104: and executing calculation tasks aiming at the service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model.
S105: and executing the target service according to the output result.
After the processed data is input into the business model, the CPU and the NPU are required to complete the calculation tasks related to the business model in the reasoning and prediction process.
Specifically, the CPU may execute a calculation task for the service model according to the data retained by itself, and the NPU may execute a calculation task for the service model according to the data received by itself, and then the CPU may integrate the calculation result of itself and the calculation result of the NPU, to obtain an output result of the service model.
In addition, in the task scheduling process, the CPU can divide the calculation task aiming at the service model into a first subtask and a second subtask according to at least one of task types, precision requirements and parallelism requirements of different tasks related in the model reasoning process. In the model reasoning process, the CPU executes a first subtask according to the self-reserved processed data to obtain a first calculation result, the NPU executes a second subtask according to the self-reserved data to obtain a second calculation result, and then the CPU can integrate the first calculation result and the second calculation result to obtain an output result of the service model.
For example, the CPU may divide a computational task involving logical operations (e.g., data flow, data allocation) into a first sub-task for processing by the CPU itself, and a computational task involving arithmetic operations (e.g., convolution computation, activation computation, etc.) into a second sub-task for processing by the NPU.
It should be noted that, in the task scheduling process, since the processed data required to be calculated by the CPU is different from the processed data required to be calculated by the NPU, the CPU and the NPU may perform a part of the same calculation task, that is, at least a part of the first subtask and the second subtask are the same.
For example, the CPU and NPU may each perform feature extraction tasks for their own retained and received processed data, except that the extracted feature data requires a convolution and activation operation (second subtask) by the NPU by the CPU controlling the data flow (first subtask).
And then the satellite node can execute the service according to the output result of the service model, for example, when the service model is an image recognition model, the output result of the service model can be the image recognition result, and the satellite node can transmit the image recognition result to the ground terminal in real time so that the ground terminal can perform the services of path planning, target tracking and the like aiming at the recognized target object.
For another example, when the business model is a weather prediction model, the output result of the business model may be weather data, and the satellite node may transmit the weather data to the ground terminal in real time, so that the ground terminal performs weather early warning according to the received weather data.
Of course, in some service scenarios, a single satellite node may also receive service model output results of other satellite nodes in the space-based information system, and integrate and send all output results to the ground terminal.
Furthermore, through executing actual business execution in the satellite nodes, the model training process can be accelerated through the edge satellite nodes based on the technology of adopting a pre-trained model, a lightweight model and the like, and the real-time performance of mixed task processing is improved.
The edge satellite node is not only a source for data generation, but also a node for data processing, so that the delay of data transmission to a post-stage center for processing can be saved, and the instantaneity of data processing can be improved. Each node of the edge satellite network generates data, so that the data has distributed attributes naturally, each node can directly acquire own data for model training, and the distributed common training of the model is realized through local updating and global sharing of model parameters among the nodes. For ease of understanding, the present disclosure provides a distributed training process schematic of a business model, as shown in fig. 6.
Fig. 6 is a schematic diagram of a distributed training process of a business model provided in the present specification.
The system comprises a ground data set, a service model, a satellite node, a parameter gradient calculation module and a data analysis module, wherein the service model can be pre-trained in advance through the ground data set and deployed to each edge satellite node, and each satellite node carries out parameter gradient calculation according to data generated by the satellite node as a training set of the satellite node: the parameter gradient calculation task is divided into N parts (N is the number of satellite nodes), one part is calculated, and the part is transmitted to adjacent satellite nodes in the network.
After N-1 rounds of transmission, each satellite node has parameter gradient values of all satellite nodes, each satellite node updates parameters of the model by using the parameter gradient values of all satellite nodes, and each satellite node has the same updated model parameters.
In the process, a single satellite node can acquire sample data, and the sample data is preprocessed through an FPGA arranged in the satellite node to obtain processed sample data; transmitting the processed sample data to a CPU (central processing unit) arranged in the satellite node, so that at least part of the processed sample data is transmitted to an NPU (non point processing unit) arranged in the satellite node through the CPU, and training tasks aiming at a service model are executed according to the respective corresponding processed sample data through the CPU and the NPU respectively to obtain target gradient information; and sending the target gradient information to each adjacent satellite node adjacent to the satellite node, receiving the target gradient information sent by each adjacent satellite node, and updating the model parameters of the service model according to the received target gradient information.
The single satellite node can firstly predict the collected image data through the pre-trained service model, and after a plurality of predictions, the prediction result and the image data are issued to the ground, and after correction is carried out by ground personnel, the ground terminal returns the corrected sample data to the satellite node to carry out fine adjustment on the pre-trained service model.
Of course, the single satellite node can also perform self-supervision training on the pre-trained service model by taking the image data acquired in real time as a training sample in a self-supervision training mode.
For example, a corresponding discrimination network may be set in the training process for judging the authenticity of the predicted result, so that the predicted result of the service model may be discriminated as true by the discrimination network as far as possible, and the discrimination network may discriminate the predicted result of the service model as false as far as possible as an optimization target, and train the service model.
According to the method, the real-time performance and the intellectualization of satellite task processing can be greatly improved, the cost of a satellite computing unit can be reduced by a super-heterogeneous hardware platform based on the VPX bus standard of a COTS device, and the on-orbit operation reliability is considered; the hardware platform is enabled to have elastic and extensible capabilities; while satisfying the reinforcing property.
The above is one or more embodiments of the present disclosure implementing a service execution method based on a space-based information system, and based on the same concept, the present disclosure further provides a corresponding service execution device based on a space-based information system, as shown in fig. 7.
Fig. 7 is a schematic diagram of a service execution device based on a space-based information system provided in the present specification, including:
the acquisition module 701 is configured to acquire, for each satellite node in the space-based information system, acquired image data;
the processing module 702 is configured to pre-process the image data through a field programmable gate array FPGA disposed in the satellite node, to obtain processed data;
a distribution module 703, configured to transmit the processed data to a central processing unit CPU disposed in the satellite node, so as to send, by the CPU, at least part of the processed data to an embedded neural network processor NPU disposed in the satellite node;
the computing module 704 is configured to execute, according to the CPU and the NPU, a computing task for a service model according to the respective corresponding processed data, to obtain an output result of the service model;
And the executing module 705 is configured to execute the target service according to the output result.
Optionally, for each satellite node in the space-based information system, a first memory and a second memory are arranged in the satellite node, wherein the first memory comprises a memory, and the second memory comprises a flash memory; the first memory is used for storing cache data generated by the CPU and the NPU in the process of executing the calculation task aiming at the service model; the second memory is used for storing the output result.
Optionally, the processing module 702 is specifically configured to transmit the image data to a defogging algorithm module in the FPGA, perform defogging processing on the image data by using the defogging algorithm module to obtain processed data, and store the processed data in a cache module outside the FPGA; after the data control bus module inside the FPGA is monitored to generate an interrupt, the processed data in the cache module is transmitted to the CPU.
Optionally, the computing module 704 is specifically configured to divide, by the CPU, the computing task into a first subtask and a second subtask, and issue the second subtask to the NPU; executing the first subtask by the CPU according to the self-reserved processed data, and executing the second subtask by the NPU according to the received processed data.
Optionally, the computing module 704 is specifically configured to divide, by the CPU, the computing task into a first subtask and a second subtask according to at least one of a task type, a precision requirement, and a parallelism requirement related to different tasks in executing the computing task.
Optionally, the calculating module 704 is specifically configured to execute, by using the CPU, the first subtask according to the processed data retained by the CPU to obtain a first execution result, and execute, by using the NPU, the second subtask according to the received processed data to obtain a second execution result; and integrating the first execution result and the second execution result to obtain the output result.
Optionally, the apparatus further comprises:
a training module 706, configured to obtain sample data; preprocessing the sample data through an FPGA arranged in the satellite node to obtain processed sample data; transmitting the processed sample data to a CPU disposed in the satellite node, so as to transmit at least part of the processed sample data to an NPU disposed in the satellite node through the CPU; respectively executing training tasks aiming at the service model according to the respectively corresponding processed sample data through the CPU and the NPU to obtain target gradient information; transmitting the target gradient information to each adjacent satellite node adjacent to the satellite node, and receiving the target gradient information transmitted by each adjacent satellite node; and updating the model parameters of the service model according to the received target gradient information.
The present specification also provides a computer-readable storage medium storing a computer program operable to execute a method of executing a service based on the space-based information system provided in fig. 1, as described above.
The present specification also provides a schematic block diagram of a satellite corresponding to that of fig. 1, as shown in fig. 8. At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile storage, as illustrated in fig. 8, although other hardware required by other services may be included. The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to realize the service execution method based on the space-based information system described in the above-mentioned figure 1. Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.
Improvements to one technology can clearly distinguish between improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) and software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., field programmable gate array (Field Programmable Gate Array, FPGA)) is an integrated circuit whose logic function is determined by the programming of the device by a user. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.
The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims (10)

1. The task execution method based on the space-based information system is characterized in that a plurality of satellite nodes are arranged in the space-based information system, and each satellite node is provided with a pre-trained service model, and the task execution method comprises the following steps:
aiming at each satellite node in the space-based information system, the satellite node acquires acquired image data;
preprocessing the image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data;
Transmitting the processed data to a central processing unit CPU arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural network processor NPU arranged in the satellite node through the CPU;
respectively executing calculation tasks aiming at a service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model;
and executing the target service according to the output result.
2. The method of claim 1, wherein for each satellite node in the space-based information system, a first memory and a second memory are provided in the satellite node, the first memory comprising memory and the second memory comprising flash memory;
the first memory is used for storing cache data generated by the CPU and the NPU in the process of executing the calculation task aiming at the service model;
the second memory is used for storing the output result.
3. The method according to claim 1, wherein the image data is preprocessed by a field programmable gate array FPGA provided in the satellite node to obtain processed data, in particular comprising:
Transmitting the image data to a defogging algorithm module in the FPGA so as to perform defogging processing on the image data through the defogging algorithm module to obtain processed data, and storing the processed data in a cache module outside the FPGA;
after the data control bus module inside the FPGA is monitored to generate an interrupt, the processed data in the cache module is transmitted to the CPU.
4. The method of claim 1, wherein performing, by the CPU and the NPU, a computational task for a business model according to the respective corresponding processed data, comprises:
dividing the computing task into a first subtask and a second subtask through the CPU, and issuing the second subtask to the NPU;
executing the first subtask by the CPU according to the self-reserved processed data, and executing the second subtask by the NPU according to the received processed data.
5. The method of claim 4, wherein dividing the computing task into a first subtask and a second subtask by the CPU and issuing the second subtask to the NPU comprises:
And dividing the computing task into a first subtask and a second subtask according to at least one of task types, precision requirements and parallelism requirements related to different tasks in the process of executing the computing task by the CPU.
6. The method of claim 4, wherein the calculating tasks for the service model are executed according to the respective corresponding processed data by the CPU and the NPU, respectively, to obtain the output result of the service model, specifically including:
executing the first subtask according to the self-reserved processed data by the CPU to obtain a first execution result, and executing the second subtask according to the received processed data by the NPU to obtain a second execution result;
and integrating the first execution result and the second execution result to obtain the output result.
7. The method according to claim 1, wherein for each satellite node in the space-based information system, training a traffic model in that satellite node comprises:
acquiring sample data;
preprocessing the sample data through an FPGA arranged in the satellite node to obtain processed sample data;
Transmitting the processed sample data to a CPU disposed in the satellite node, so as to transmit at least part of the processed sample data to an NPU disposed in the satellite node through the CPU;
respectively executing training tasks aiming at the service model according to the respectively corresponding processed sample data through the CPU and the NPU to obtain target gradient information;
transmitting the target gradient information to each adjacent satellite node adjacent to the satellite node, and receiving the target gradient information transmitted by each adjacent satellite node;
and updating the model parameters of the service model according to the received target gradient information.
8. A service execution device based on a space-based information system, comprising:
the acquisition module is used for acquiring acquired image data aiming at each satellite node in the space-based information system;
the processing module is used for preprocessing the image data through a Field Programmable Gate Array (FPGA) arranged in the satellite node to obtain processed data;
the distribution module is used for transmitting the processed data to a Central Processing Unit (CPU) arranged in the satellite node so as to transmit at least part of the processed data to an embedded neural Network Processor (NPU) arranged in the satellite node through the CPU;
The calculation module is used for executing calculation tasks aiming at the service model according to the respectively corresponding processed data through the CPU and the NPU to obtain an output result of the service model;
and the execution module executes the target service according to the output result.
9. A computer-readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of any of the preceding claims 1-7.
10. A satellite comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any of the preceding claims 1-7 when the program is executed by the processor.
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