CN117277395A

CN117277395A - Method, device, equipment and medium for generating trigger pulse of valve control equipment

Info

Publication number: CN117277395A
Application number: CN202311125328.1A
Authority: CN
Inventors: 贺振宇; 高冲; 路建良; 刘宏; 张升
Original assignee: State Grid Smart Grid Research Institute Co ltd; State Grid Corp of China SGCC
Current assignee: State Grid Smart Grid Research Institute Co ltd; State Grid Corp of China SGCC
Priority date: 2023-09-01
Filing date: 2023-09-01
Publication date: 2023-12-22

Abstract

The invention relates to the technical field of direct current transmission, and discloses a method, a device, equipment and a medium for generating trigger pulse of valve control equipment, wherein the method comprises the following steps: the method comprises the steps of controlling a first FPGA chip and a second FPGA chip to receive a main and standby state sent by the other party, and correspondingly triggering a master-slave signal and a control pulse signal sent by a monitoring master control board, wherein the master-slave signal is used for controlling the main and standby state of the first FPGA chip or the second FPGA chip, and the main and standby state comprises: a primary state and a standby state; when the primary-standby switching is forbidden in the primary-standby switching interval, if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate trigger pulses, and the primary-standby switching interval is forbidden to comprise a rising edge of a control pulse signal window and a first preset interval after the rising edge. The problem that thyristor trigger pulse generated by valve control equipment in the related technology is unreliable is solved.

Description

Method, device, equipment and medium for generating trigger pulse of valve control equipment

Technical Field

The invention relates to the technical field of direct current transmission, in particular to a method, a device, equipment and a medium for generating trigger pulse of valve control equipment.

Background

The high-voltage direct-current power transmission plays an important role in the aspect of long-distance large-capacity power transmission due to technical and economic advantages, and the direct-current power transmission converter valve is used as core equipment of a converter station and is an important hub for alternating-current and direct-current power conversion. The valve control device of the high-voltage direct-current transmission converter valve is used as a direct control unit of the converter valve, and can realize the triggering and state monitoring of the thyristor of the converter valve. In order to improve the reliability of a power transmission system, the valve control equipment of the HVDC transmission converter valve generally adopts two sets of identical control systems which are redundant for standby.

At present, during the live operation of a high-voltage direct-current transmission converter valve, when the switching of a main system and a standby system occurs, the phenomenon that the trigger pulse of a thyristor is lost or is triggered by mistake is extremely easy to occur at the switching moment due to the asymmetry of the operation of the two systems, and even the commutation failure is caused under severe conditions, so that the operation of the whole system is unstable. Therefore, there is a need to solve the problem in the prior art that the valve control device is unreliable in generating the thyristor trigger pulse.

Disclosure of Invention

In view of the above, the invention provides a method, a device, equipment and a medium for generating a trigger pulse of a valve control device, so as to solve the problem that the trigger pulse of a thyristor generated by the valve control device is unreliable.

In a first aspect, the present invention provides a method for generating a trigger pulse of a valve control device, where the valve control device is configured to send the trigger pulse to a thyristor of a converter valve, the valve control device includes two redundant sets of control systems, one set of control system includes a first FPGA chip, a trigger monitoring main control board corresponding to the first FPGA chip, and the other set of control system includes a second FPGA chip and a trigger monitoring main control board corresponding to the second FPGA chip, and the trigger monitoring main control board is configured to send a master-slave signal and a control pulse signal to the corresponding FPGA chip, where the method includes: the method comprises the steps of controlling a first FPGA chip and a second FPGA chip to receive a main and standby state sent by the other party, and correspondingly triggering a master-slave signal and a control pulse signal sent by a monitoring master control board, wherein the master-slave signal is used for controlling the main and standby state of the first FPGA chip or the second FPGA chip, and the main and standby state comprises: a primary state and a standby state; when the primary-standby switching is forbidden in the primary-standby switching interval, if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate trigger pulses, and the primary-standby switching interval is forbidden to comprise a rising edge of a control pulse signal window and a first preset interval after the rising edge.

In the embodiment of the invention, the primary-standby switching interval is set to enable the first FPGA chip or the second FPGA chip in the primary state to still generate the trigger pulse correctly when the primary-standby switching occurs, so that the process of outputting the trigger pulse to the thyristor of the converter valve by the primary system caused by system switching of the valve control equipment is prevented from being interrupted, the reliability of generating the trigger pulse by the valve control equipment is improved, and the problem that the trigger pulse of the thyristor generated by the valve control equipment in the related technology is unreliable is solved.

In an alternative embodiment, during operation of the valve control device, the first FPGA chip and the second FPGA chip send an occupation signal, where the occupation signal is 1 in a primary-standby prohibition switching interval, 0 outside the primary-standby prohibition switching interval, and when primary-standby is generated in the primary-standby prohibition switching interval, if the first FPGA chip or the second FPGA chip is in a primary state and the other is in a standby state, the first FPGA chip or the second FPGA chip is controlled to generate a trigger pulse, and the primary-standby prohibition switching interval includes a rising edge of a control pulse signal window and a first preset interval after the rising edge, including: when the active-standby switching occurs, if the first FPGA chip or the second FPGA chip is in the active state, the other is in the standby state, and the occupied signal sent by the first FPGA chip or the second FPGA chip is 1, the first FPGA chip or the second FPGA chip is controlled to generate a trigger pulse.

In the embodiment of the invention, the occupation signal is used for indicating whether the first FPGA chip or the second FPGA chip is in a trigger pulse starting generation state, namely judging whether the control pulse signal is in a primary-standby switching prohibition interval, and if so, keeping the FPGA chip of the primary system to generate the trigger pulse, thereby achieving the purpose of avoiding the process of interrupting the process of outputting the trigger pulse to the thyristor of the converter valve by the primary system due to system switching of the valve control equipment.

In an alternative embodiment, controlling the first FPGA chip or the second FPGA chip to generate the trigger pulse includes: controlling the first FPGA chip or the second FPGA chip to generate a double pulse signal at the rising edge of the control pulse signal, wherein the double pulse signal is used for triggering the thyristor of the converter valve and simultaneously starting the automatic re-triggering function of the thyristor of the converter valve; and/or generating a single pulse signal at the falling edge of the control pulse signal, wherein the single pulse signal is used for closing the automatic re-triggering function of the thyristor of the converter valve.

In the embodiment of the invention, the first FPGA chip or the second FPGA chip can generate trigger pulse, which can be a double pulse signal, a single pulse signal, a double pulse signal and a single pulse signal, different trigger pulses have different roles, and the generated trigger pulse is sent to the thyristor of the converter valve by the valve control equipment, so that different control purposes of the thyristor of the converter valve can be realized.

In an alternative embodiment, the method further comprises: if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state, after the main and standby switching is carried out, the second FPGA chip or the first FPGA chip is controlled to generate a double pulse signal at the rising edge of a corresponding control pulse signal window; and controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal at the falling edge of the corresponding control pulse signal window.

In the embodiment of the invention, after the main and standby switching, the first FPGA chip or the second FPGA chip which is in the main use state (original standby state) is made to complement a double pulse signal, so that the problem that the thyristor of the converter valve does not receive the trigger pulse due to the system switching of the valve control equipment is avoided, and the reliability of the valve control equipment for generating the trigger pulse is further improved.

In an alternative embodiment, if the first FPGA chip or the second FPGA chip is in the active state and the other FPGA chip is in the standby state, after performing active-standby switching, the second FPGA chip or the first FPGA chip is controlled to generate a double pulse signal at a rising edge of the corresponding control pulse signal window, which includes: when the first FPGA chip or the second FPGA chip is in a main state, the other is in a standby state, and when the occurrence of main-standby switching is detected, the first FPGA chip and the second FPGA chip are controlled to perform main-standby switching when the occupation signal is 0, and a control pulse signal is built in a collision interval which is an interval in which the first FPGA chip and the second FPGA chip are in the main state or in the standby state; after the active/standby switching is performed, the second FPGA chip or the first FPGA chip is controlled to generate a double-pulse signal at the rising edge of the corresponding control pulse signal window.

In the embodiment of the invention, when the first FPGA chip and the second FPGA chip are in the active state or in the standby state, the control pulse signal is set to 0, and after the active-standby switching is finished, the first FPGA chip or the second FPGA chip which is in the active state is enabled to supplement a double pulse signal at the rising edge of the window when the control pulse signal is changed from 0 to be effective again, so that the effect of improving the triggering reliability of the thyristor of the converter valve is achieved.

In an optional implementation manner, after the first FPGA chip or the second FPGA chip is controlled to generate the trigger pulse if the first FPGA chip or the second FPGA chip is in the active state and the other FPGA chip is in the standby state, the method further includes: if the first FPGA chip or the second FPGA chip is in a main state, the other party is in a standby state, and after the main and standby switching is carried out, if the second FPGA chip or the first FPGA chip does not receive the control pulse signal, the second FPGA chip or the first FPGA chip is controlled to generate a single pulse signal.

In the embodiment of the invention, after the main and standby switching, if the control pulse signal received by the first FPGA chip or the second FPGA chip which is in the main state is finished, the first FPGA chip or the second FPGA chip is controlled to complementarily send a single pulse signal, thereby achieving the effect of avoiding the false triggering of the thyristor of the converter valve and further improving the reliability of the valve control equipment for generating the trigger pulse.

In an optional implementation manner, the primary-standby switching prohibition interval further includes a second preset interval after a falling edge of the control pulse signal window, and the control of the second FPGA chip or the first FPGA chip to generate a single pulse signal includes: and controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal outside the primary and standby switching prohibition interval.

In the embodiment of the invention, after the switching of the main and the standby is controlled, the first FPGA chip or the second FPGA chip which is in the main state and is in the new use state and has the control pulse signal ended is delayed to supplement one single pulse signal, so that the problem that two single pulse signals are mistakenly regarded as one double pulse signal is avoided, and the reliability of the valve control equipment for generating the trigger pulse is further improved.

In a second aspect, the present invention provides a device for generating a trigger pulse of a valve control device, where the valve control device is configured to send the trigger pulse to a thyristor of a converter valve, the valve control device includes two redundant sets of control systems, one set of control system includes a first FPGA chip, a trigger monitoring main control board corresponding to the first FPGA chip, and the other set of control system includes a second FPGA chip and a trigger monitoring main control board corresponding to the second FPGA chip, and the trigger monitoring main control board is configured to send a master-slave signal and a control pulse signal to the corresponding FPGA chip, where the device includes: the receiving module is used for controlling the first FPGA chip and the second FPGA chip to receive the main and standby state sent by the other party, and correspondingly triggering the master-slave signal and the control pulse signal sent by the monitoring master control board, wherein the master-slave signal is used for controlling the main and standby state of the first FPGA chip or the second FPGA chip, and the main and standby state comprises: a primary state and a standby state; the trigger pulse generation module is used for controlling the first FPGA chip or the second FPGA chip to generate trigger pulses if the first FPGA chip or the second FPGA chip is in a main state and the other FPGA chip is in a standby state when main-standby switching is forbidden in the main-standby switching interval, and the main-standby switching interval is forbidden to comprise a rising edge of a control pulse signal window and a first preset interval after the rising edge.

In an alternative embodiment, during operation of the valve control device, the first FPGA chip and the second FPGA chip send an occupation signal, where the occupation signal is 1 in the primary-standby prohibition switching interval and 0 outside the primary-standby prohibition switching interval, and the trigger pulse generating module includes: and the trigger pulse generation unit is used for controlling the first FPGA chip or the second FPGA chip to generate trigger pulses if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state and the occupation signal sent by the first FPGA chip or the second FPGA chip is 1 when the main and standby switching occurs.

In an alternative embodiment, the trigger generation module further includes: the double-pulse signal generating unit is used for controlling the first FPGA chip or the second FPGA chip to generate a double-pulse signal on the rising edge of the control pulse signal, wherein the double-pulse signal is used for triggering the thyristor of the converter valve and simultaneously starting the automatic re-triggering function of the thyristor of the converter valve; and the single pulse signal generating unit is used for and/or generating a single pulse signal at the falling edge of the control pulse signal, wherein the single pulse signal is used for closing the automatic re-triggering function of the thyristor of the converter valve.

In an alternative embodiment, the apparatus further comprises: the double-pulse signal complement module is used for controlling the second FPGA chip or the first FPGA chip to generate a double-pulse signal at the rising edge of the corresponding control pulse signal window after the primary and standby switching is carried out if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state; the single pulse signal generation module is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal at the falling edge of the corresponding control pulse signal window.

In an alternative embodiment, the dual pulse signal reissue module includes: the control pulse modulation unit is used for controlling the first FPGA chip and the second FPGA chip to perform active-standby switching and setting a control pulse signal to be 0 in a collision interval when the first FPGA chip or the second FPGA chip is in an active state and the other is in a standby state and detecting that active-standby switching occurs, wherein the collision interval is an interval when the first FPGA chip and the second FPGA chip are in the active state or in the standby state; and the double pulse signal complement unit is used for controlling the second FPGA chip or the first FPGA chip to generate a double pulse signal at the rising edge of the corresponding control pulse signal window after the main/standby switching is performed.

In an alternative embodiment, the apparatus further comprises: the single pulse signal reissue module is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state and after the main and standby switching is carried out, the second FPGA chip or the first FPGA chip does not receive the control pulse signal.

In an optional implementation manner, the primary-standby switching prohibition interval further includes a second preset interval after a falling edge of the control pulse signal window, and the single pulse signal complementary sending module includes: the single pulse signal complement unit is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal outside the primary-standby switching prohibition interval.

In a third aspect, the present invention provides a computer device comprising: the valve control device trigger pulse generating method comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so that the valve control device trigger pulse generating method of the first aspect or any corresponding implementation mode of the first aspect is executed.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the valve control apparatus trigger pulse generating method of the first aspect or any of the embodiments corresponding thereto.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a valve control device architecture of a hvth converter valve in the related art;

FIG. 2 is a flow chart of a method of generating a trigger pulse for a valve control apparatus according to an embodiment of the present invention;

FIG. 3 is a flow chart of another method of generating a trigger pulse for a valve control apparatus according to an embodiment of the present invention;

fig. 4 is a schematic diagram of thyristor trigger pulse generation in a normal communication state according to an embodiment of the invention;

FIG. 5 is a schematic diagram of thyristor firing pulses when performing a master-slave switch during a control pulse signal window according to an embodiment of the invention;

FIG. 6 is a flow chart of yet another method of generating a trigger pulse for a valve control apparatus according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of thyristor trigger pulse generation when master-slave switching is performed after a control pulse signal window according to an embodiment of the present invention;

FIG. 8 is a flow chart of yet another method of generating a trigger pulse for a valve control apparatus according to an embodiment of the present invention;

fig. 9 is a block diagram of a structure of a valve control apparatus trigger pulse generating device according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that in the description of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In addition, if the meaning of "and/or" in the present invention includes three parallel schemes, taking "a and/or B" as an example, it includes a scheme a, a scheme B, or a scheme that a and B satisfy simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

At present, high-voltage direct-current power transmission plays an important role in the aspect of long-distance large-capacity power transmission due to the unique technical and economic advantages of the high-voltage direct-current power transmission, wherein a direct-current power transmission converter valve is used as core equipment in a converter station and is an important hub for alternating-current and direct-current power conversion. The high-voltage direct-current transmission converter valve control equipment is used as a direct control unit of the converter valve, can realize the triggering and state monitoring of the thyristor of the converter valve, has the protection function of the converter valve, and plays an important role in the safe and stable operation of the converter valve and the whole transmission system. In order to improve the reliability of a power transmission system, valve control equipment of a high-voltage direct-current power transmission converter valve generally adopts two sets of identical control systems to mutually redundant standby: when one set of system is the main system, the other set of system is in a hot standby state. The actual control of the thyristor and the protection output of the converter valve are realized by the main system, the standby system follows the current main system state at any time, synchronously receives the control command of the upper-layer pole control and the state information of the converter valve, and sends the state information received by the standby system to the pole control equipment correspondingly connected, but the valve control standby system has no actual control authority on the converter valve. Only when the main system fails or a system switching instruction is received, the valve control equipment lifts the system in a standby state into the main system and reduces the main system into the standby system. During live operation of the high-voltage direct-current transmission converter valve, at least two bridge arm thyristors are in a trigger conduction state, when the switching of the main system and the standby system occurs, the problem that thyristor trigger pulses are lost or mistakenly triggered easily occurs at the switching moment due to the fact that the two sets of systems are in asymmetry in operation, and even commutation failure is caused under severe conditions, so that the whole system is unstable in operation. In order to realize reliable switching of the main and standby systems, it is needed to provide a reliable generation method of thyristor pulses during switching of the main and standby systems of the valve control equipment, so as to avoid the situation of losing trigger pulses or false triggering.

Fig. 1 is a schematic diagram of a valve control device architecture of a hvdc transmission converter valve in the related art, and as shown in fig. 1, the hvdc transmission converter valve control device is generally a two-layer architecture, including: a communication management chassis and a trigger monitor chassis. The communication management machine box is connected with the pole control unit on the upper part and connected with the trigger monitoring machine box on the lower part, and the communication management machine box is independently operated by two identical machine boxes (the communication management machine box 1 and the communication management machine box 2) as a main system and a standby system respectively. The trigger monitoring machine case is connected with the communication management machine case on the pair, is directly connected with the converter valve on the pair, and comprises two trigger monitoring main control boards (the trigger monitoring main control board 1 and the trigger monitoring main control board 2) which are respectively used as a main system and a standby system to independently operate, and the two trigger monitoring main control boards are respectively connected with the two corresponding communication management machine cases. The trigger monitoring chassis further comprises a plurality of trigger monitoring boards which are connected with a plurality of converter valve thyristors (TTM board 1 … n), each trigger monitoring board comprises two FPGA chips, each chip is connected with the two trigger monitoring main control boards through the back plate, and the two trigger monitoring main control boards are respectively used as a main system and a standby system to independently operate. The two FPGA chips on each trigger monitoring board output trigger signals to the output light ports of each trigger monitoring board through a logic chip (logic selector), and the trigger signals are sent to the converter valve thyristors through the output light ports. All hardware except the single-set configuration of an output light port connected with the thyristor of the converter valve by the triggering monitoring plate on the hardware is in double-redundancy configuration, and the hardware is respectively used as a main system and a standby system to independently operate, and meanwhile, the two systems respectively send own main and standby state information to the other system.

When the system operates normally, the communication management cabinets of the main system and the standby system respectively receive a main and standby signal and a converter valve control pulse signal (CP signal) issued by the corresponding pole control system, the main and standby signal and the control pulse signal are issued to a trigger monitoring main control board correspondingly connected in a trigger monitoring cabinet of the corresponding bridge arm, the trigger monitoring main control board sends the main and standby signal and the control pulse signal to the trigger monitoring board through a back plate, two independent FPGAs on the trigger monitoring board select the control pulse signal received by the FPGA chip of the main system as a trigger signal output condition sent to a thyristor TTM board through a logic selector, and generate a trigger signal to be sent to the thyristor TTM board of the converter valve, so that the control of the converter valve is realized.

According to an embodiment of the present invention, there is provided a valve control apparatus trigger pulse generation method embodiment, it being noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

In this embodiment, a method for generating trigger pulses of a valve control device is provided, where the valve control device adopts the architecture shown in fig. 1, and the method can be used in the above mobile terminal, such as a central processing unit, a server, and the like. The valve control equipment is used for sending trigger pulses to the thyristor of the converter valve, and comprises two redundant sets of control systems, one set of control system comprises a first FPGA chip and a trigger monitoring main control board corresponding to the first FPGA chip, the other set of control system comprises a second FPGA chip and a trigger monitoring main control board corresponding to the second FPGA chip, and the trigger monitoring main control board is used for sending master-slave signals and control pulse signals to the corresponding FPGA chips. Fig. 2 is a schematic flow chart of a method for generating trigger pulses of a valve control device according to an embodiment of the present invention, as shown in fig. 2, the flow chart includes the following steps:

step S201, controlling the first FPGA chip and the second FPGA chip to receive the master-slave state sent by the other party and the master-slave signal and the control pulse signal sent by the corresponding trigger monitoring master control board, where the master-slave signal is used to control the master-slave state of the first FPGA chip or the second FPGA chip, and the master-slave state includes: a primary state and a standby state. Optionally, the first FPGA chip and the second FPGA chip in the two sets of control systems receive the master-slave state sent by the other party, and simultaneously receive the master-slave signal and the control pulse signal sent by the corresponding trigger monitoring master control board. According to the master-slave signals, the current master-slave state of the first FPGA chip or the second FPGA chip can be determined, master-slave switching occurs at any time, master-slave switching is completed at any time, and the like.

Step S202, when the primary-standby switching is prohibited in the primary-standby switching interval, if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate a trigger pulse, and the primary-standby switching interval is prohibited to include a rising edge of a control pulse signal window and a first preset interval after the rising edge. Optionally, the rising edge of the control pulse signal window and the first preset interval after the rising edge are set as the active-standby switching prohibition interval, that is, the interval in which the valve control device is not allowed to perform active-standby switching. If the main and standby switching occurs in the interval, the first FPGA chip or the second FPGA chip in the main state when the main and standby switching occurs is controlled to continuously generate trigger pulses, and the trigger pulses are not influenced by the main and standby system switching of the valve control equipment.

In this embodiment, a method for generating a trigger pulse of a valve control device is provided, which may be used in the above mobile terminal, such as a central processing unit, a server, etc., and fig. 3 is a schematic flow chart of another method for generating a trigger pulse of a valve control device according to an embodiment of the present invention, as shown in fig. 3, where the flow chart includes the following steps:

step S301, controlling the first FPGA chip and the second FPGA chip to receive the master-slave state sent by the other party and the master-slave signal and the control pulse signal sent by the corresponding trigger monitoring master control board, where the master-slave signal is used to control the master-slave state of the first FPGA chip or the second FPGA chip, and the master-slave state includes: a primary state and a standby state. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.

In step S302, when the active/standby switching is prohibited from occurring in the active/standby switching interval, if the first FPGA chip or the second FPGA chip is in the active state and the other FPGA chip is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate the trigger pulse, and the active/standby switching interval is prohibited from including the rising edge of the control pulse signal window and the first preset interval after the rising edge. In an alternative embodiment, during the operation of the valve control device, the first FPGA chip and the second FPGA chip send an occupancy signal, where the occupancy signal is 1 in the primary-standby switching prohibition interval and 0 outside the primary-standby switching prohibition interval, and step S302 includes:

And a step a, when the main and standby switching occurs, if the first FPGA chip or the second FPGA chip is in a main state, the other is in a standby state, and the occupied signal sent by the first FPGA chip or the second FPGA chip is 1, the first FPGA chip or the second FPGA chip is controlled to generate a trigger pulse. Optionally, the occupation signal is used to indicate whether the first FPGA chip or the second FPGA chip is in a trigger pulse starting generating state, that is, whether the control pulse signal is in a primary-standby switching prohibition interval is judged, if so, the FPGA chip of the primary system is kept to generate the trigger pulse, so as to achieve the purpose of avoiding interruption of the process of outputting the trigger pulse to the thyristor of the converter valve by the primary system due to system switching of the valve control device.

In an alternative embodiment, controlling the first FPGA chip or the second FPGA chip to generate the trigger pulse includes: controlling the first FPGA chip or the second FPGA chip to generate a double pulse signal at the rising edge of the control pulse signal, wherein the double pulse signal is used for triggering the thyristor of the converter valve and simultaneously starting the automatic re-triggering function of the thyristor of the converter valve; and/or generating a single pulse signal at the falling edge of the control pulse signal, wherein the single pulse signal is used for closing the automatic re-triggering function of the thyristor of the converter valve. The double pulse signal and the single pulse signal can be alternatively generated, or both signals can be generated.

Optionally, fig. 4 is a schematic diagram of generating a trigger pulse of a thyristor in a normal communication state according to an embodiment of the present invention, as shown in fig. 4, the first FPGA chip or the second FPGA chip generates a double pulse signal at a rising edge of a corresponding control pulse signal window (CP signal window), where the double pulse signal is used to trigger the thyristor, and at the same time, starts an automatic re-triggering function of the thyristor. As an example of a typical control pulse signal and a double pulse signal, the control pulse signal window width is 6.67ms, and the interval between two adjacent control pulse signal windows is 20ms; the double pulse signal has a width of 30us and comprises two single pulses of 10us and a spacing of 10us.

Specifically, the first FPGA chip or the second FPGA chip generates a single pulse signal at the falling edge of the corresponding control pulse signal window (CP signal window), and sends the single pulse signal to the thyristor of the converter valve, so as to close the automatic re-triggering function of the thyristor of the converter valve. As an example of a single pulse signal, the single pulse signal has a width of 10us. The width of the control pulse signal, the double pulse signal, and the single pulse signal is not particularly limited in this embodiment. The thyristor automatic re-triggering function is configured as shown in fig. 4, and is turned on after receiving the double pulse signal and turned off after receiving the single pulse signal.

Step S303, if the first FPGA chip or the second FPGA chip is in the active state and the other is in the standby state, after the active-standby switching is performed, the second FPGA chip or the first FPGA chip is controlled to generate a double pulse signal at the rising edge of the corresponding control pulse signal window. Specifically, step S303 includes:

and b1, when the first FPGA chip or the second FPGA chip is in a main state, the other party is in a standby state, and when the occurrence of main-standby switching is detected, the first FPGA chip and the second FPGA chip are controlled to perform main-standby switching when the occupation signal is 0, and control pulse signals are built in a collision interval which is an interval in which the first FPGA chip and the second FPGA chip are in the main state or in the standby state. Specifically, when the occupancy signal is 0 (the active/standby switching interval is not prohibited), the valve control device is controlled to perform active/standby switching, and when the valve control device performs active/standby switching, there may be a case where two FPGA chips are in active states or standby states in a short moment, as shown in the active/standby switching interval in fig. 5. In order to ensure that reliable thyristor trigger pulse is generated, when the occupation signal is 0, the control pulse signal is embedded into 0 in a conflict zone, namely a zone in which two FPGA chips are in a main state or in a standby state.

And b2, after the main and standby switching is performed, controlling the second FPGA chip or the first FPGA chip to generate a double-pulse signal at the rising edge of the corresponding control pulse signal window. As shown in fig. 5, after the switching between the active and standby (i.e., the active and standby switching actions) is completed, the second FPGA chip (FPGA 2) in the active state (active) is controlled to send a double pulse signal (i.e., the FPGA2 sends a double pulse signal with diagonal lines filled with TTM trigger signals) on the rising edge of the corresponding control pulse signal window (the rising edge of the window after the FPGA2 receives the CP signal window collision interval). In the embodiment of the invention, after the main and standby switching, the first FPGA chip or the second FPGA chip which is in the main use state (original standby state) is made to complement a double pulse signal, so that the problem that the thyristor of the converter valve does not receive the trigger pulse due to the system switching of the valve control equipment is avoided, and the reliability of the valve control equipment for generating the trigger pulse is further improved.

Step S304, the second FPGA chip or the first FPGA chip is controlled to generate a single pulse signal at the falling edge of the corresponding control pulse signal window. As shown in fig. 5, after the switching between the active and the standby is completed, the second FPGA chip (FPGA 2) that is currently in the active state is controlled to normally generate a single pulse signal at the falling edge of the control pulse signal window. Thereafter, the trigger pulse may be generated according to the thyristor trigger pulse generation schematic diagram in the normal communication state as shown in fig. 4.

In this embodiment, a method for generating a trigger pulse of a valve control device is provided, which may be used in the above mobile terminal, such as a central processing unit, a server, etc., and fig. 6 is a schematic flow chart of another method for generating a trigger pulse of a valve control device according to an embodiment of the present invention, as shown in fig. 6, where the flow chart includes the following steps:

step S601, controlling the first FPGA chip and the second FPGA chip to receive the master-slave state sent by the other party and the master-slave signal and the control pulse signal sent by the corresponding trigger monitoring master control board, where the master-slave signal is used to control the master-slave state of the first FPGA chip or the second FPGA chip, and the master-slave state includes: a primary state and a standby state. Please refer to step S301 in the embodiment shown in fig. 3 in detail, which is not described herein.

In step S602, when the active/standby switching is prohibited from occurring in the active/standby switching interval, if the first FPGA chip or the second FPGA chip is in the active state and the other FPGA chip is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate the trigger pulse, and the active/standby switching interval is prohibited from including the rising edge of the control pulse signal window and the first preset interval after the rising edge. Please refer to step S302 in the embodiment shown in fig. 3 in detail, which is not described herein.

In step S603, if the first FPGA chip or the second FPGA chip is in the active state, and the other is in the standby state, after the active-standby switching is performed, if the second FPGA chip or the first FPGA chip does not receive the control pulse signal, the second FPGA chip or the first FPGA chip is controlled to generate a single pulse signal. In the embodiment of the invention, after the main and standby switching, if the control pulse signal received by the first FPGA chip or the second FPGA chip which is in the main state is finished, the first FPGA chip or the second FPGA chip is controlled to complementarily send a single pulse signal, thereby achieving the effect of avoiding the false triggering of the thyristor of the converter valve and further improving the reliability of the valve control equipment for generating the trigger pulse.

In an optional implementation manner, the primary-standby switching prohibition interval further includes a second preset interval after the falling edge of the control pulse signal window, and the step S603 of controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal includes: and controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal outside the primary and standby switching prohibition interval. Specifically, the primary-standby switching prohibition interval includes a first preset interval after a rising edge and a rising edge of the control pulse signal window, and further includes a second preset interval after a falling edge and a falling edge of the control pulse signal window, where the first preset interval and the second preset interval may be the same or different, and may be set according to specific situations. As shown in fig. 7, after the active/standby switching is performed, the FPGA2 is in the active state, but the control pulse signal is already ended at this time, and in order to avoid losing the single pulse signal, the FPGA2 is controlled to complement a single pulse signal outside the active/standby switching prohibition interval (i.e., the active/standby switching prohibition interval). The problem that two single pulse signals are mistakenly regarded as a double pulse signal is solved, and the reliability of the valve control equipment for generating the trigger pulse is further improved.

In this embodiment, a method for generating a trigger pulse of a valve control device is provided, which may be used in the above mobile terminal, such as a central processing unit, a server, etc., and fig. 8 is a schematic flow chart of another method for generating a trigger pulse of a valve control device according to an embodiment of the present invention, as shown in fig. 8, where the flow chart includes the following steps:

step S801, the first FPGA chip or the second FPGA chip is controlled to judge whether the first FPGA chip or the second FPGA chip receives the current active/standby state and the sending pulse busy state sent by the trigger monitoring main control board and the other FPGA chip. The "busy" status of the pulse is an occupied signal, and the detailed description of the step is referred to as step S301 in the embodiment shown in fig. 3, and is not repeated herein.

In step S802, if the two FPGA chips are in the active/standby state and the state is unchanged, a busy signal is set to 1 in the rising edge of the control pulse signal window and the Δt time interval thereafter, so as to keep the double pulse and single pulse output of the main system unchanged. The rising edge of the control pulse signal window and the subsequent delta T time interval are the primary and standby switching prohibition intervals, and when the busy signal is 1, the logic selector keeps the output of the double pulse and single pulse trigger signals of the original primary system FPGA unchanged.

In step S803, when the two FPGA chips start to perform the master-slave switching operation, if the "busy" signal is still 1, the output of the dual-pulse and single-pulse trigger signals of the original main system FPGA is kept unchanged. The master-slave switching operation is started, that is, the master-slave switching operation is performed or the master-slave switching command is received, and the detailed description of the step is referred to in step a of the embodiment shown in fig. 3, which is not repeated herein.

In step S804, it is determined that the two FPGA chips are in the same master or slave states, and the "busy" signals are all 0, and the control pulse signal window is divided into two parts by setting the control pulse signal to 0. Please refer to step b2 in step S303 in the embodiment shown in fig. 3, which is not described herein.

In step S805, it is determined that the two FPGA chips are in the same master or slave states, respectively, and the current "busy" signal is 0, and then system switching is performed. Please refer to step b1 in step S303 in the embodiment shown in fig. 3, which is not described herein.

Step S806, the master-slave switching is completed, the control pulse signal is normally received, and the FPGA which is raised to the master system continues to generate double pulses by utilizing the second half part of the received control pulse signal. Please refer to step b3 in step S303 in the embodiment shown in fig. 3, which is not described herein.

Step S807, after the master-slave switching is completed, the FPGA rising to the master system detects that the control pulse signal is finished, and then the single pulse is reissued after time delay. Please refer to step S603 in the embodiment shown in fig. 6, which is not described herein.

In an alternative implementation manner, this embodiment proposes a method for generating a trigger pulse of a thyristor in a normal communication state, as shown in fig. 4, specifically, two FPGAs of a trigger monitor board each receive a control pulse signal window (with a typical signal width of 6.67 ms), and generate a double pulse signal with a width of 10us and an interval of 10us at a rising edge of the control pulse signal window, where the double pulse signal is used for triggering the thyristor, and simultaneously starting an automatic re-triggering function of the thyristor. At the end position of the control pulse signal window (the falling edge of the pulse-making signal window), a single pulse signal with the length of 10us is generated and sent to the TTM for closing the automatic re-triggering function of the thyristor, and the valve control also adopts the pulse time sequence to judge the state of the thyristor.

In an alternative implementation manner, this embodiment proposes a method for generating a trigger pulse of a thyristor when performing master-slave switching during a control pulse signal window, as shown in fig. 5, because of asymmetry in operation of two sets of systems, when a valve control device performs system switching, in order to prevent an FPGA double pulse transmitting process of a previous main system in a trigger monitoring board from being interrupted, a thyristor TTM board receives double pulses incompletely and then rises to an FPGA of the main system, and if a control pulse signal received by its own system is still valid, it is necessary to reissue double pulses to the TTM board, so as to ensure normal triggering of the thyristor. In order to reduce the interruption of the double-pulse transmitting process of the original main system, a 'master-slave switching disallowed interval' is set in an FPGA program of a trigger monitoring board, and the master-slave switching is executed after the double-pulse transmitting is finished; when the system is switched, two sets of systems are primary systems or standby systems, and when the primary system and the opposite sets of systems are primary systems or standby systems, the middle position of a control pulse signal window with the time width of 6.67ms is modulated to be 0, so that the control pulse signal window is divided into two parts, such as a primary-standby switching same-primary or same-secondary interval in fig. 5; the FPGA chip of the new main system sends complete double-pulse and single-pulse signals at the latter half part of the control pulse signal window, so that the normal triggering and the stopping triggering of the thyristor are ensured.

In an alternative implementation manner, the present embodiment proposes a method for generating a thyristor trigger pulse when performing master-slave switching after controlling a pulse signal window. The thyristor TTM unit starts an automatic re-triggering function after receiving double pulses, but the thyristor is easy to lose single pulse due to the asymmetric double systems of the valve control equipment, data acquisition errors or calculation errors and the like, so that the thyristor is triggered and conducted by mistake. To prevent the above, a mechanism as shown in fig. 7 is provided: after the master-slave switching is finished, if the FPGA which is newly increased to the master system detects that the FPGA is not in the control pulse signal window, a single pulse signal is reissued, and the automatic re-triggering function of the thyristor TTM board is turned off. In order to prevent the time deviation of the repeated monopulse signal from the normal double pulse or monopulse signal, the time deviation is too short, the repeated monopulse signal is erroneously judged to be double pulse, and a 'master-slave switching disallowing interval' is additionally arranged before the repeated monopulse signal.

The high-voltage direct-current transmission valve control equipment adopts a redundant architecture, so that the operation reliability is improved; 2 completely redundant FPGA chips on the trigger monitoring board can realize the selection of control instructions through a logic selector, and after any FPGA chip fails (the trigger signal can become high level or low level), the other FPGA chip can send the normal trigger signal to the converter valve through the logic selector through the control signal; by setting a section which does not allow master-slave switching, the double pulse and single pulse signals of the original master system are prevented from being interrupted; the double pulse signals are reissued after the master-slave switching in the control pulse signal window, so that the reliability of triggering the thyristor is improved; the single pulse signal is reissued after the master-slave switching after the control pulse signal window, so that the thyristor is prevented from being triggered by mistake, and the problem that the thyristor trigger pulse generated by the valve control equipment in the related technology is unreliable is solved.

The embodiment also provides a device for generating trigger pulses of a valve control device, which is used for implementing the foregoing embodiments and preferred implementations, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a trigger pulse generating device of a valve control apparatus, as shown in fig. 9, including: the receiving module 901 is configured to control the first FPGA chip and the second FPGA chip to receive a master-slave signal and a control pulse signal sent by the opposite party and triggered by the monitoring master control board, where the master-slave signal is used to control the master-slave state of the first FPGA chip or the second FPGA chip, and the master-slave state includes: a primary state and a standby state; the trigger pulse generating module 902 is configured to control the first FPGA chip or the second FPGA chip to generate a trigger pulse if the first FPGA chip or the second FPGA chip is in the active state and the second FPGA chip is in the standby state when active/standby switching is prohibited in the active/standby switching interval, where the active/standby switching prohibition interval includes a rising edge of a control pulse signal window and a first preset interval after the rising edge.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The valve-controlled apparatus trigger pulse generating means in this embodiment is in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit ) circuit, a processor and a memory executing one or more software or fixed programs, and/or other devices that can provide the above functions.

The embodiment of the invention also provides computer equipment, which is provided with the trigger pulse generating device of the valve control equipment shown in the figure 9.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 10, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a valve control equipment trigger pulse generation method which characterized in that, valve control equipment is used for sending trigger pulse to converter valve thyristor, valve control equipment includes two sets of redundant control system, and one set of control system includes first FPGA chip, the trigger monitoring main control board that first FPGA chip corresponds, and another set of control system includes second FPGA chip and the trigger monitoring main control board that second FPGA chip corresponds, trigger monitoring main control board is used for issuing master-slave signal and control pulse signal to corresponding FPGA chip, the method includes:

the method comprises the steps of controlling a first FPGA chip and a second FPGA chip to receive a main and standby state sent by an opposite side, and a master and slave signal and a control pulse signal which are correspondingly triggered to be sent by a monitoring master control board, wherein the master and slave signal is used for controlling the main and standby state of the first FPGA chip or the second FPGA chip, and the main and standby state comprises: a primary state and a standby state;

When the primary-standby switching is forbidden in the primary-standby switching interval, if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state, the first FPGA chip or the second FPGA chip is controlled to generate trigger pulses, and the primary-standby switching interval comprises a rising edge of a control pulse signal window and a first preset interval after the rising edge.

2. The method for generating a trigger pulse of a valve control device according to claim 1, wherein during operation of the valve control device, the first FPGA chip and the second FPGA chip send an occupation signal, the occupation signal is 1 in a primary-standby prohibition switching interval and 0 outside the primary-standby prohibition switching interval, and when primary-standby switching occurs in the primary-standby prohibition switching interval, if the first FPGA chip or the second FPGA chip is in a primary state and the other is in a standby state, the first FPGA chip or the second FPGA chip is controlled to generate the trigger pulse, and the primary-standby prohibition switching interval includes a rising edge of a control pulse signal window and a first preset interval after the rising edge, including:

when the active-standby switching occurs, if the first FPGA chip or the second FPGA chip is in the active state, the other is in the standby state, and the occupied signal sent by the first FPGA chip or the second FPGA chip is 1, the first FPGA chip or the second FPGA chip is controlled to generate a trigger pulse.

3. The method for generating trigger pulses of a valve control device according to claim 1, wherein controlling the first FPGA chip or the second FPGA chip to generate trigger pulses includes:

controlling the first FPGA chip or the second FPGA chip to generate a double pulse signal at the rising edge of the control pulse signal, wherein the double pulse signal is used for triggering a thyristor of the converter valve and simultaneously starting an automatic re-triggering function of the thyristor of the converter valve;

and/or generating a single pulse signal at the falling edge of the control pulse signal, wherein the single pulse signal is used for closing the automatic re-triggering function of the thyristor of the converter valve.

4. The valve control apparatus trigger pulse generation method according to claim 2, characterized in that the method further comprises:

if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state, after the main and standby switching is carried out, the second FPGA chip or the first FPGA chip is controlled to generate a double pulse signal at the rising edge of a corresponding control pulse signal window;

and controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal at the falling edge of the corresponding control pulse signal window.

5. The method for generating trigger pulse of valve control device according to claim 4, wherein if the first FPGA chip or the second FPGA chip is in the active state and the other FPGA chip is in the standby state, after performing active-standby switching, the second FPGA chip or the first FPGA chip is controlled to generate a double pulse signal at the rising edge of the corresponding control pulse signal window, comprising:

When the first FPGA chip or the second FPGA chip is in a main state, the other is in a standby state, and when the occurrence of main-standby switching is detected, the first FPGA chip and the second FPGA chip are controlled to perform main-standby switching when the occupation signal is 0, and a control pulse signal is built in a collision interval to be 0, wherein the collision interval is an interval in which the first FPGA chip and the second FPGA chip are in the main state or in the standby state;

after the active/standby switching is performed, the second FPGA chip or the first FPGA chip is controlled to generate a double-pulse signal at the rising edge of the corresponding control pulse signal window.

6. The method for generating a trigger pulse of a valve control device according to claim 1, wherein, when the first FPGA chip or the second FPGA chip is in a main state and the other FPGA chip is in a standby state, the first FPGA chip or the second FPGA chip is controlled to generate the trigger pulse, and the main/standby switching inhibition interval includes a rising edge of a control pulse signal window and a first preset interval after the rising edge, the method further includes:

if the first FPGA chip or the second FPGA chip is in a main state, the other party is in a standby state, and after the main and standby switching is carried out, if the second FPGA chip or the first FPGA chip does not receive the control pulse signal, the second FPGA chip or the first FPGA chip is controlled to generate a single pulse signal.

7. The method for generating a trigger pulse of a valve control device according to claim 6, wherein the primary-standby switching prohibition interval further includes a control pulse signal window falling edge and a second preset interval after the falling edge, and the controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal includes:

and controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal outside the primary and standby switching prohibition interval.

8. The utility model provides a valve accuse equipment trigger pulse generating device, its characterized in that, valve accuse equipment is used for sending trigger pulse to the converter valve thyristor, valve accuse equipment includes two sets of redundant control system, and one set of control system includes first FPGA chip, the trigger monitoring main control board that first FPGA chip corresponds, and another set of control system includes the trigger monitoring main control board that second FPGA chip corresponds, trigger monitoring main control board is used for issuing master-slave signal and control pulse signal to corresponding FPGA chip, the device includes:

the receiving module is used for controlling the first FPGA chip and the second FPGA chip to receive the main and standby state sent by the other party, and a master-slave signal and a control pulse signal which are sent by the corresponding trigger monitoring master control board, wherein the master-slave signal is used for controlling the main and standby state of the first FPGA chip or the second FPGA chip, and the main and standby state comprises: a primary state and a standby state;

The trigger pulse generation module is used for controlling the first FPGA chip or the second FPGA chip to generate trigger pulses if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state when main-standby switching is forbidden in a main-standby switching interval, and the main-standby switching interval comprises a rising edge of a control pulse signal window and a first preset interval after the rising edge.

9. The device for generating a trigger pulse of a valve control apparatus according to claim 8, wherein during operation of the valve control apparatus, the first FPGA chip and the second FPGA chip send an occupancy signal, the occupancy signal is 1 in a primary-standby switching prohibition interval and is 0 outside the primary-standby switching prohibition interval, and the trigger pulse generating module comprises:

and the trigger pulse generation unit is used for controlling the first FPGA chip or the second FPGA chip to generate trigger pulses if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state and the occupation signal sent by the first FPGA chip or the second FPGA chip is 1 when the main and standby switching occurs.

10. The valve control device trigger pulse generation apparatus of claim 8, wherein the trigger pulse generation module further comprises:

The double-pulse signal generating unit is used for controlling the first FPGA chip or the second FPGA chip to generate a double-pulse signal on the rising edge of the control pulse signal, and the double-pulse signal is used for triggering the thyristor of the converter valve and simultaneously starting the automatic re-triggering function of the thyristor of the converter valve;

and the single pulse signal generating unit is used for and/or generating a single pulse signal at the falling edge of the control pulse signal, wherein the single pulse signal is used for closing the automatic re-triggering function of the thyristor of the converter valve.

11. The valve control apparatus trigger pulse generating device of claim 9, wherein the device further comprises:

the double-pulse signal complement module is used for controlling the second FPGA chip or the first FPGA chip to generate a double-pulse signal at the rising edge of the corresponding control pulse signal window after the primary and standby switching is carried out if the first FPGA chip or the second FPGA chip is in the primary state and the other is in the standby state;

the single pulse signal generation module is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal at the falling edge of the corresponding control pulse signal window.

12. The valve control apparatus trigger pulse generating device of claim 11, wherein the double pulse signal reissue module comprises:

The control pulse modulation unit is used for controlling the first FPGA chip and the second FPGA chip to perform active-standby switching and setting a control pulse signal to be 0 in a conflict zone when the first FPGA chip or the second FPGA chip is in an active state and the other side is in a standby state and detecting that active-standby switching occurs, wherein the conflict zone is a zone where the first FPGA chip and the second FPGA chip are in the active state or in the standby state;

and the double pulse signal complement unit is used for controlling the second FPGA chip or the first FPGA chip to generate a double pulse signal at the rising edge of the corresponding control pulse signal window after the main/standby switching is performed.

13. The valve control apparatus trigger pulse generating device of claim 8, further comprising:

the single pulse signal reissue module is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal if the first FPGA chip or the second FPGA chip is in a main state and the other is in a standby state and after the main and standby switching is carried out, the second FPGA chip or the first FPGA chip does not receive the control pulse signal.

14. The apparatus for generating a trigger pulse of a valve control device according to claim 13, wherein the primary-standby switching prohibition interval further includes a falling edge of a control pulse signal window and a second preset interval after the falling edge, and the single pulse signal complementary module includes:

The single pulse signal complement unit is used for controlling the second FPGA chip or the first FPGA chip to generate a single pulse signal outside the primary-standby switching prohibition interval.

15. A computer device, comprising:

a memory and a processor communicatively coupled to each other, the memory having stored therein computer instructions that, upon execution, cause the processor to perform the valve control apparatus trigger pulse generation method of any one of claims 1 to 7.

16. A computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the valve control apparatus trigger pulse generation method according to any one of claims 1 to 7.