CN117276279A

CN117276279A - Semiconductor device and method of forming the same

Info

Publication number: CN117276279A
Application number: CN202311112733.XA
Authority: CN
Inventors: 尤韦翔; 何韦德; 洪昕扬; 林孟佑; 黄祥鸿; 郑存甫; 胡宽侃; 陈思桦; 吴亭昀; 曾威程; 林威呈; 王振印; 黄瑞乾; 廖思雅
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-08-31
Filing date: 2023-08-31
Publication date: 2023-12-22

Abstract

An embodiment of the present invention provides a method of forming a semiconductor device, including: forming a first transistor and a second transistor stacked over the first transistor; forming a first opening adjacent to the first transistor and the second transistor; forming a gate isolation layer in the first opening; forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening; forming an incision tract in the conductive layer; forming a dielectric layer on the conductive layer in the cut region; forming front side source/drain contacts in contact with the second transistor and the conductive layer; and forming backside source/drain contacts in contact with the first transistor and the conductive layer. The embodiment of the invention also provides a semiconductor device.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present invention relate to semiconductor devices and methods of forming the same.

Background

The demand for computing power for electronic devices, including smart phones, tablet computers, desktop computers, notebook computers, and many other types of electronic devices, continues to increase. Integrated circuits provide computational power for these electronic devices. One way to increase computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that a given area of a semiconductor substrate may include.

Complementary Field Effect Transistors (CFETs) may be used to increase the density of transistors in an integrated circuit. The CFET may include vertically stacked N-type transistors and P-type transistors. The gate electrodes of the N-type transistor and the P-type transistor may be electrically shorted together.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device including: a complementary transistor, the complementary transistor comprising: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor and having a third source/drain region overlapping the first source/drain region and a fourth source/drain region overlapping the second source/drain region; a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent to the first transistor and the second transistor; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact, and comprising: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being located in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region, or both the fourth source/drain region and the second source/drain region; and a dielectric layer located in the opening and on the conductive layer in the gate isolation structure.

Further embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: forming a first transistor and a second transistor stacked over the first transistor; forming a first opening adjacent to the first transistor and the second transistor; forming a gate isolation layer in the first opening; forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening; forming an incision tract in the conductive layer; forming a dielectric layer on the conductive layer in the cut region; forming front side source/drain contacts in contact with the second transistor and the conductive layer; and forming backside source/drain contacts in contact with the first transistor and the conductive layer.

Still further embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: forming a first transistor and a second transistor stacked over the first transistor; forming a first opening adjacent to the first transistor and the second transistor; forming a gate isolation layer in the first opening; forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening; forming front side source/drain contacts in contact with the upper surfaces of the second transistor and the conductive layer; forming a cut region in the conductive layer after forming the front side source/drain contacts; forming a dielectric layer on the conductive layer in the cut region; and forming backside source/drain contacts in contact with the first transistor and the conductive layer.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1F are diagrams of an integrated circuit including a CFET, according to some embodiments.

Fig. 2A-2M are cross-sectional views of an integrated circuit at various stages of processing according to some embodiments.

Fig. 3A-16 are cross-sectional views of an integrated circuit at various stages of processing according to some embodiments.

Fig. 17 and 18 are flowcharts of processes for forming integrated circuits according to some embodiments.

Detailed Description

In the following description, numerous thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given for the various embodiments by way of example. Those of skill in the art will recognize in light of the present disclosure that other dimensions and materials may be used in many cases without departing from the scope of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail in order to avoid unnecessarily obscuring descriptions of the embodiments of the disclosure.

Throughout the specification and the claims which follow, unless the context requires otherwise, the word "comprise" and variations such as "comprises" and "comprising" will be interpreted in an open, inclusive sense, i.e. as "including, but not limited to.

The use of ordinal numbers such as first, second and third does not necessarily imply a sequential ordering, but may merely distinguish between multiple instances of a step or structure.

Reference throughout this specification to "some embodiments" or "an embodiment" means that a particular component, structure, or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular components, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

As used in this specification and the appended claims, the terms "filled", "thereby filled" and "filled" by … … include the meanings of partially filled and fully filled (or "filled", "thereby filled" and "filled", etc.). For example, the conductive layer may be said to "fill" the opening, which may include the conductive layer contacting an adjacent wall of the opening, or the conductive layer being present in the opening, with one or more layers of different materials between the conductive layer and the adjacent wall.

As used in this specification and the appended claims, the terms "around," "thereby surrounding" and "surrounded" include the meanings of completely surrounding and partially surrounding (or "around," "thereby surrounding" and "surrounded," etc.). For example, a "surrounding" hexagonal volume (e.g., a right angle prism) includes the meaning of being completely surrounded by material on all six sides, or may be partially surrounded such that one or more of the six sides are not completely surrounded by material and at least a portion thereof is exposed.

Embodiments of the present disclosure provide integrated circuits with CFETs having improved electrical characteristics. The CFET includes a first transistor vertically stacked on a second transistor. The first transistor and the second transistor each have a plurality of semiconductor nanostructures that function as channel regions for the first transistor and the second transistor. The first gate metal surrounds the semiconductor nanostructure of the first transistor. The second gate metal surrounds the semiconductor nanostructure of the second transistor.

Three-dimensional (3D) stacks forming CFETs have been proposed as potential transistor architectures to further extend moore's law. Due to the nature of 3D stacked NFETs and PFETs, vertical local interconnects (VLI, or conductive through substrate layers "TSL") facilitate connecting top and bottom devices to each other. However, a larger area of the VLI may result in a substantial gate-to-source/drain capacitance (Cgs/Cgd), which may significantly degrade the performance and/or power of Complementary Metal Oxide Semiconductor (CMOS) circuits. The first metal layer on top of the VLI may be separated from the VLI by a large distance due to potential shorting to the VLI through the source/drain contacts and source/drain vias, which wastes limited first metal layer routing resources.

The conductive TSL has an L-shape or other shape with a cut-out region overlapping one or more transistors adjacent to the first transistor and/or the second transistor. In the cut-out region, the conductive material of the conductive TSL is replaced with a non-conductive material, such as a dielectric material, which reduces parasitic capacitance between the conductive TSL and the overlying transistor. The conductive TSL with the cut-out region enhances routing flexibility, e.g., allows contacts to be positioned on the dielectric material without shorting to the conductive TSL, thereby freeing up first metal layer routing resources. Improved design may be achieved by controlling the dielectric material region recession, for example by balancing resistance and capacitance. The gate isolation structure pad (in which the conductive TSL is formed) may employ a low-k dielectric, which is advantageous in reducing the capacitance of the L-type conductive TSL.

Fig. 1A and 1B are schematic top views of integrated circuits 100, 100A according to various embodiments. The integrated circuit 100 includes an L-shaped conductive TSL 250, the L-shaped conductive TSL 250 having a lower portion that is wider than an upper portion thereof. The integrated circuit 100A includes an inverted-L conductive TSL 250, the inverted-L conductive TSL 250 having an upper portion wider than a lower portion thereof. Fig. 1C-1E are schematic cross-sectional and perspective views of CFETs of integrated circuits 100, 100A. For clarity of illustration, some components may be omitted from the views in the drawings.

Fig. 1C is a cross-sectional view of an integrated circuit 100 according to some embodiments. The view of fig. 1C may correspond to the cross-sectional line A-A in fig. 1A and 1B. Integrated circuit 100 includes a Complementary Field Effect Transistor (CFET) 102.CFET 102 includes a first transistor 104 of a first conductivity type and a second transistor 105 of a second conductivity type. The first transistor 104 is vertically stacked on the second transistor 105. The CFET 102 separates the stacked channel region of the first transistor 104 from the stacked channel region of the second transistor 105 with an isolation structure 126 in order to improve the electrical characteristics of the CFET 102. In other words, a hybrid nanostructure (e.g., hybrid sheet) is formed that includes the stacked channel region of the first transistor 104, the isolation structure 126, and the stacked channel region of the second transistor 105.

CFET transistor 102 may correspond to a full-gate-all-around transistor. The full-gate-all-around transistor structure may be patterned by any suitable method. For example, structures may be formed using one or more photolithographic processes including a double patterning process or a multiple patterning process. Typically, a double patterning process or multiple patterning process combines lithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the full-ring gate structure. Further, the full gate-all-around CFET 102 may include a plurality of semiconductor nanostructures corresponding to the channel regions of the CFET 102. The semiconductor nanostructures may include nanoplatelets, nanowires, or other types of nanostructures. Full-gate-all-around transistors may also be referred to as nanostructure transistors.

The view of fig. 1C is an X-view of integrated circuit 100, where the X-axis is the horizontal axis, the Z-axis is the vertical axis, and the Y-axis extends into and out of the drawing sheet. As used herein, the term "X-view" corresponds to a cross-sectional view in which the X-axis is horizontal and the Z-axis is vertical. As used herein, the term "Y view" corresponds to a cross-sectional view in which the Y-axis is horizontal and the Z-axis is vertical.

The integrated circuit 100 includes a substrate 101. The substrate 101 may include a semiconductor layer, a dielectric layer, or a combination of a semiconductor layer and a dielectric layer. Further, as will be described in more detail below, conductive structures may be formed within the substrate 101 as backside conductive vias and interconnects. In some embodiments, the substrate 101 includes a single crystal semiconductor layer on at least a surface portion. The substrate 101 may comprise a single crystal semiconductor material such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP.

In some embodiments, the substrate 101 may include a dielectric layer including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. In some embodiments, the substrate 101 may include shallow trench isolation regions formed in the semiconductor layer. Various configurations of the substrate 101 may be employed without departing from the scope of the present disclosure. In some embodiments, for example, when the substrate 101 is removed prior to forming the backside interconnect structure, the substrate 101 is not present.

A transistor 105 is formed over the substrate 101. Transistor 104 is formed over transistor 105. In some embodiments, transistor 104 is an N-type transistor and transistor 105 is a P-type transistor. However, in some embodiments, transistor 104 may be a P-type transistor and transistor 105 may be an N-type transistor.

The transistor 104 includes a plurality of semiconductor nanostructures 106. The semiconductor nanostructures 106 are stacked in the vertical direction or the Z-direction. In the example of fig. 1C, there are three stacked semiconductor nanostructures 106. However, in practice, there may be only two stacked nanostructures 106 or there may be more than three stacked semiconductor nanostructures 106 without departing from the scope of the present disclosure. Furthermore, in some embodiments, only a single semiconductor nanostructure 106 and a single semiconductor nanostructure 107 may be present. The semiconductor nanostructure 106 corresponds to a channel region of the transistor 102. The semiconductor nanostructures 106 may be nanoplatelets, nanowires, or other types of nanostructures.

The transistor 105 includes a plurality of semiconductor nanostructures 107. The semiconductor nanostructures 107 are stacked in the vertical direction or the Z-direction. In the example of fig. 1C, there are three stacked semiconductor nanostructures 107. However, in practice, there may be only two stacked nanostructures 107 or there may be more than three stacked nanostructures 107 without departing from the scope of the present disclosure. The semiconductor nanostructure 107 corresponds to a channel region of the transistor 102. The semiconductor nanostructures 107 may be nanoplatelets, nanowires, or other types of nanostructures. The number of semiconductor nanostructures 107 may be the same as the number of semiconductor nanostructures 106 or may be different from the number of semiconductor nanostructures 106.

Semiconductor nanostructures 106 and 107 may comprise Si, siGe, or other semiconductor materials. In the non-limiting example described herein, the semiconductor nanostructure 106 is silicon. The vertical thickness of the semiconductor nanostructures 106 may be between 2nm and 5 nm. The semiconductor nanostructures 106 may be separated from each other by 4nm to 10nm in the vertical direction. Other thicknesses and materials may be used for the semiconductor nanostructures 106 without departing from the scope of the disclosure. The semiconductor nanostructures 107 may be of the same material and size as the semiconductor nanostructures 106, or may be of a different semiconductor material than the semiconductor nanostructures 106.

Transistor 104 and transistor 105 include gate dielectrics. The gate dielectric includes an interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110. Interfacial gate dielectric 108 is a low K gate dielectric. The interfacial gate dielectric layer is in contact with semiconductor nanostructure 106 and semiconductor nanostructure 107. The high-K gate dielectric layer 110 is in contact with the low-K gate dielectric layer. An interfacial gate dielectric layer 108 is disposed between the semiconductor nanostructure 106 and the high-K gate dielectric layer 110, and between the semiconductor nanostructure 107 and the high-K gate dielectric layer 110.

Interfacial gate dielectric layer 108 may comprise a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. Interfacial gate dielectric layer 108 may comprise a relatively low K dielectric relative to a high K dielectric such as hafnium oxide or other high K dielectric material that may be used for the gate dielectric of a transistor. The interfacial gate dielectric layer 108 may include a native oxide layer grown on the surfaces of the semiconductor nanostructures 106 and 107. The interfacial gate dielectric layer 108 may have a thickness between 0.4nm and 2 nm. Other materials, configurations, and thicknesses may be used for the interfacial gate dielectric layer 108 without departing from the scope of the present disclosure.

The high-K gate dielectric layer includes one or more layers of dielectric material, such as HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. The thickness of the high-k dielectric is in the range of about 1nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-K gate dielectric layer without departing from the scope of the present disclosure. The high-K gate dielectric layer may include a first layer including HfO having dipole doping including La and Mg, and a second layer ₂ The second layer includes a second layer having a crystalline high-K ZrO layer.

Transistor 104 includes gate metal 112. Gate metal 112 surrounds semiconductor nanostructure 106. The gate metal 112 is in contact with the high-K gate dielectric layer 110. Gate metal 112 corresponds to the gate electrode of transistor 104. In examples where transistor 104 is an N-type transistor, gate metal 112 may include a material that produces a desired work function with semiconductor nanostructure 106. In one example, the gate metal 112 includes titanium aluminum, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive material. In some embodiments, the gate metal 112 surrounds the semiconductor nanostructure 106 on four sides, e.g., top, bottom, left side, and right side. In some embodiments, such as in a fork-slice transistor, the gate metal 112 may surround the semiconductor nanostructure 106 on three sides, the gate metal 112 being substantially absent on the fourth side. For example, the gate metal 112 may be present on an outer edge of the fourth side and may occupy less than about 5% of the area of the fourth side.

Fig. 1C shows a single gate metal 112. In practice, however, the gate electrode of transistor 104 may comprise multiple metal layers. For example, the gate metal 112 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. The gate metal 112 may include a gate fill material that fills the remaining volume between the semiconductor nanostructures 106 after the one or more liner layers have been deposited. Various materials, combinations of materials, and configurations may be used for the gate metal 112 without departing from the scope of the present disclosure.

Transistor 105 includes gate metal 113. Gate metal 113 surrounds semiconductor nanostructure 107. The gate metal 113 is in contact with the high-K gate dielectric layer 110. Gate metal 113 corresponds to the gate electrode of transistor 105. In examples where transistor 105 is a P-type transistor, gate metal 113 may include a material that produces a desired work function with semiconductor nanostructure 107. In one example, the gate metal 113 comprises titanium nitride, titanium, aluminum, tungsten, ruthenium, molybdenum, copper, gold, or other conductive material.

Fig. 1C shows a single gate metal 113. In practice, however, the gate electrode of transistor 105 may include multiple metal layers surrounding semiconductor nanostructure 107. For example, the gate metal 113 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. The gate metal 113 may include a gate fill material that fills the remaining volume between the semiconductor nanostructures 107 after the one or more liner layers have been deposited. Various materials, combinations of materials, and configurations may be used for the gate metal 113 without departing from the scope of the present disclosure.

Transistor 104 includes source/drain regions 116. Source/drain regions 116 are in contact with each semiconductor nanostructure 106. Each semiconductor nanostructure 106 extends in the X-direction between source/drain regions 116. The source/drain regions 116 comprise a semiconductor material. Transistor 105 includes source/drain regions 117. Source/drain regions 117 are in contact with each semiconductor nanostructure 107. Each semiconductor nanostructure 107 extends in the X-direction between source/drain regions 117. The source/drain regions 117 comprise a semiconductor material.

In the example where transistor 104 is an N-type transistor and transistor 105 is a P-type transistor, source/drain regions 116 may be doped with an N-type dopant species. The N-type dopant species may include P, as or other N-type dopant species. In the case of a P-type transistor, the source/drain regions 117 may be doped with a P-type dopant species. The P-type dopant species may include B or other P-type dopant species. Doping may be performed in situ in the epitaxially grown devices of source/drain regions 117. Source/drain regions 116 and 117 may comprise other materials and structures without departing from the scope of the present disclosure.

As used herein, the term "source/drain region" may refer to either a source region or a drain region, either individually or collectively, depending on the context. Accordingly, one of the source/drain regions 116 may be a source region while the other of the source/drain regions 116 is a drain region, and vice versa. Further, in some cases, one or both of the source/drain regions 116 may be shared by one or more laterally adjacent transistors.

Transistors 104 and 105 each include an internal spacer 114. The inner spacer 114 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials without departing from the scope of the present disclosure. In one example, the inner spacer 114 comprises silicon oxynitride.

The internal spacers 114 of the transistor 104 physically separate the gate metal 112 from the source/drain regions 116. This prevents shorting between the gate metal 112 and the source/drain regions 116. The internal spacers 114 of the transistor 105 physically separate the gate metal 113 from the source/drain regions 117. This prevents shorting between the gate metal 113 and the source/drain regions 117.

The transistor 104 may include source/drain contacts 118. Each source/drain contact 118 is disposed over a respective source/drain region 116 and is electrically connected to a respective source/drain region 116. An electrical signal may be applied to the source/drain regions 116 via the source/drain contacts. The source/drain contacts 118 may include silicide 120. Silicide 120 is formed at the top of source/drain regions 116. Silicide 120 may comprise titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicide.

The source/drain contacts 118 may also include a conductive layer 122 disposed on the silicide 120. The conductive layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive material. The source/drain contacts 118 may also include a conductive layer 124 on the conductive layer 122. Conductive layer 124 may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive material. Other materials and configurations may be used for the source/drain contacts 118 without departing from the scope of the present disclosure.

Transistor 105 may include source/drain contacts 119. Each source/drain contact 119 is disposed below a respective source/drain region 117 and is electrically connected to a respective source/drain region 117. An electrical signal may be applied to the source/drain regions 117 via the source/drain contacts. The source/drain contacts 119 may include silicide 121. Silicide 121 is formed at the bottom of source/drain regions 117. Silicide 121 may comprise titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicide.

The source/drain contacts 119 may also include a conductive layer 123 disposed on the silicide 121. The conductive layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive material. The source/drain contacts 119 may also include a conductive layer 125 on the conductive layer 123. Conductive layer 125 may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive material. Other materials and configurations may be used for the source/drain contacts 119 without departing from the scope of the present disclosure.

Transistor 102 includes sidewall spacers 131. Sidewall spacers 131 are disposed adjacent the uppermost portion of gate metal 112 and electrically isolate gate metal 112 from source/drain contacts 118. Sidewall spacer 131 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. Other thicknesses and materials may be used for sidewall spacer 131 without departing from the scope of this disclosure.

Transistor 102 may include a gate cap metal 132 disposed on an uppermost portion of gate metal 112. In some embodiments, the gate cap metal 132 comprises tungsten, fluorine-free tungsten, or other suitable conductive material. The gate cap metal 132 may have a height between 1nm and 10 nm. Other configurations, materials, and thicknesses may be used for the gate-covering metal 132 without departing from the scope of the present disclosure.

The substrate 101 may include a dielectric layer 136 and a dielectric layer 138. Dielectric layer 138 may be disposed in contact with sidewalls of source/drain contacts 119 and the lowermost portion of interfacial gate dielectric layer 108 of transistor 105. Dielectric layer 138 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. Dielectric layer 136 is disposed in contact with dielectric layer 138. Dielectric layer 136 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

Transistor 102 may be operated by applying voltages to source/drain regions 116/117 and gate metals 112/113. A voltage may be applied to the source/drain regions 116/117 via source/drain contacts 118/119. A voltage may be applied to gate metal 112/113 via a gate contact not shown in fig. 1C. Although not visible in the view of fig. 1C, gate metal 112 and gate metal 113 are shorted together. Accordingly, gate metal 112 and gate metal 113 collectively correspond to the gate electrode of CFET 102. The voltage applied to gate metal 112/113 may turn on transistor 104 and turn off transistor 105 or may turn on transistor 105 and turn off transistor 104. When the gate metals 112/113 are shorted together, the source/drain regions 116 are not shorted together with the source/drain regions 117. Depending on the particular circuit configuration, current flow through source/drain region 116 and source/drain region 117, respectively, may be selectively enabled or disabled.

As previously described, by employing different materials for gate metals 112 and 113, it may be beneficial to obtain the desired work functions for transistors 104 and 105. One possible way to form gate metal 112/113 is to first deposit gate metal 113 around all semiconductor nanostructures 106 and 107, and then perform a timed etch to remove gate metal 113 from around semiconductor nanostructures 106. A gate metal 112 is then deposited around the semiconductor nanostructures 106 after a timed etch of the gate metal 113. However, one disadvantage of this process is that in some cases the gate metal 113 directly below the lowermost semiconductor nanostructure 106 may not be completely removed. This can interfere with the work function of the transistor 104, thereby affecting the threshold voltage of the transistor 104 in an undesirable manner.

CFET 102 avoids or reduces the likelihood of work function interference by employing isolation structures 126 between semiconductor nanostructures 106 and 107. More specifically, isolation structures 126 are disposed directly between the lowermost semiconductor nanostructure 106 and the uppermost semiconductor nanostructure 107. The isolation structure 126 may include an upper semiconductor layer 127 and a lower semiconductor layer 127, and a dielectric layer 129 between the upper semiconductor layer 127 and the lower semiconductor layer 127. Various structures and compositions may be used for isolation structure 126 without departing from the scope of the present disclosure.

Dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. The dielectric layer 129 may have a length between 15nm and 30nm in the X direction. A length within this range may be sufficient to match or exceed the length of semiconductor nanostructures 106 and 107 in the X-direction. However, depending on the length of the semiconductor nanostructures 106 and 107, a longer or shorter length of the dielectric layer 129 may be selected. The dielectric layer 129 may have a height in the X direction between 5nm and 25 nm. These dimensions may be sufficient to ensure that there is no possibility of work function interference from the gate metal 113 to the semiconductor nanostructure 106. In addition, these dimensions may provide reduced gate drain capacitance. Other materials, dimensions, and configurations may be used for dielectric layer 129 without departing from the scope of the present disclosure. Dielectric layer 129 may be referred to as a dielectric nanostructure. The dielectric nanostructures may include dielectric nanoplatelets, dielectric nanowires, or another type of dielectric nanostructure.

Dielectric layer 129 has a top surface 135 and a bottom surface 137. Gate metal 112 and gate metal 113 meet at interface 139. In some embodiments, the interface 139 between the gate metal 112 and the gate metal 113 is below the top surface 135 of the dielectric layer 129. In some embodiments, interface 139 is below top surface 135 and above bottom surface 137 of dielectric layer 139. This helps ensure that there is no work function disturbance of the transistor 104 by the gate metal 113.

Each semiconductor layer 127 may have a vertical thickness between 1nm and 5 nm. Semiconductor layer 127 may comprise silicon or another suitable semiconductor material. Other materials and dimensions may be used for semiconductor layer 127 without departing from the scope of the present disclosure.

Although fig. 1C shows a single dielectric layer 129, in practice, dielectric layer 129 may comprise multiple layers of different dielectric materials located between semiconductor layers 127. For example, a first dielectric layer of silicon oxide may be provided in contact with each semiconductor layer 127. A second dielectric layer of silicon nitride may be disposed between the upper and lower portions of the first dielectric layer. Various configurations of dielectric barriers between the top semiconductor nanostructures 107 and the bottom semiconductor nanostructures 106 may be employed without departing from the scope of the present disclosure.

Fig. 1D is a Y-view of the integrated circuit 100 of fig. 1C taken along the cut line C-C of fig. 1C. Accordingly, in the view of FIG. 1D, the Y-axis is the horizontal axis and the X-axis extends into and out of the drawing sheet. The view of fig. 1D is a wide cut through gate metal 112 and gate metal 113 of transistors 104 and 105. Fig. 1D shows how the gate metal 112 surrounds each semiconductor nanostructure 106 of the transistor 104. Accordingly, gate metal 113 surrounds each semiconductor nanostructure 107 of transistor 105.

Fig. 1D shows that gate contact 240 extends into dielectric layer 134. The gate contact 240 contacts the gate cap metal 132. Accordingly, gate contact 240 is electrically connected to gate metal 112 and gate metal 113 of transistors 104 and 105. The gate contact 240 may include tungsten, titanium, tantalum, aluminum, copper, tantalum nitride, titanium nitride, or other suitable conductive material. Various configurations and materials may be used for the gate contact 240 without departing from the scope of the present disclosure.

Fig. 1D also shows an isolation structure 126 disposed between the lowermost semiconductor nanostructure 106 and the uppermost semiconductor nanostructure 107. Isolation structure 126 includes a dielectric layer 129 and a semiconductor layer 127 located above and below dielectric layer 129. Fig. 1D also shows that an interfacial gate dielectric layer 108 is present on the outer surface of semiconductor layer 127. high-K gate dielectric layer 110 surrounds isolation structure 126 in the Y-Z plane.

In some embodiments, the width of the isolation structures 126 in the Y-direction is substantially equal to or slightly greater than the width of the semiconductor nanostructures 106/107 in the Y-direction. The isolation structures 126 are thicker in the Z-direction than the semiconductor nanostructures 106/107. Furthermore, the isolation structure 126 is thicker in the Z-direction than the portion of the gate metal 113 between the top semiconductor nanostructure 107 and the isolation structure 126. This is because the sacrificial semiconductor layer 154 (see fig. 2A) is thicker than the sacrificial semiconductor layer 152. Gate metal 112/113 is formed in place of sacrificial semiconductor nanostructure 152.

In some embodiments, the junction or interface of gate metal 112/113 occurs at a vertical height corresponding to the vertical mid-level of isolation structure 126. The junction or interface of gate metals 112/113 may occur at any vertical level between semiconductor layers 127. Other configurations of gate metal 112/113 and isolation structure 126 may be employed without departing from the scope of the present disclosure.

Fig. 1E is a cross-sectional view of the integrated circuit 100 of fig. 1C taken along the cut line E-E of fig. 1C. Accordingly, in the view of FIG. 1E, the Y-axis is the horizontal axis and the X-axis extends into and out of the drawing sheet. The view of fig. 1E is a broad cut through the source/drain regions 116 and 117 from one side of the CFET 102.

Fig. 1E shows dielectric layer 130 surrounding source/drain regions 116 and 117 in the Y-Z plane except where source/drain contacts 118/119 are connected to source/drain regions 116/117. Fig. 1E also shows interlayer dielectric layer 128 surrounding the outer surface of dielectric layer 130 and filling the space between source/drain regions 116 and source/drain regions 117. Fig. 1E also shows conductive vias 242 electrically connected to source/drain contacts 118 of transistor 104. Conductive vias 242 may include tungsten, titanium, aluminum, copper, titanium nitride, tantalum nitride, or other suitable conductive layers. Although not shown in fig. 1E, conductive vias may also extend through the substrate 101 to contact the bottom of the source/drain contacts 119 in order to provide electrical connection to the source/drain regions 117.

Fig. 1F is a perspective view of the integrated circuit 100 of fig. 1C, according to some embodiments. Fig. 1F does not show interlayer dielectric layer 128 or dielectric layer 130 so that the locations of source/drain regions 116 and 117 are visible. Fig. 1F shows semiconductor nanostructures 106 and 107, interfacial gate dielectric layer 108 and high-K gate dielectric layer 110 surrounding semiconductor nanostructures 106 and 107, gate metal 112 surrounding semiconductor nanostructure 106, and gate metal 113 surrounding semiconductor nanostructure 107. Isolation structures 126 exist between the lowermost semiconductor nanostructure 106 and the uppermost semiconductor nanostructure 107. The gate cap metal 132 is visible on top of the gate metal 112. Source/drain contacts 118 are coupled to source/drain regions 116. Fig. 1F also shows that a high-K dielectric layer 110 is also present on the sidewalls of gate metal 112 and gate metal 113, and that the bottom of gate metal 113 is shown. The substrate 101 may also include the semiconductor layer 133, but after the formation of the backside conductive structure, the semiconductor layer 133 may also be completely removed at this point in the process. Various other configurations of integrated circuit 100 may be employed without departing from the scope of the present disclosure.

Fig. 2A-2M are cross-sectional views of integrated circuit 100 at various stages of processing according to some embodiments. Fig. 2A-2M illustrate a process of forming CFET 102 according to some embodiments.

Fig. 2A is a cross-sectional X-view of integrated circuit 100 according to some embodiments. In fig. 2A, a semiconductor fin 149 includes a plurality of semiconductor layers 150, a plurality of sacrificial semiconductor layers 152 stacked on a substrate 101, a semiconductor layer 127, and a special sacrificial semiconductor layer 154. The sacrificial semiconductor layer 152 is disposed between the semiconductor layers 150. As will be described in more detail below, the semiconductor layer 150 will ultimately be patterned to form semiconductor nanostructures 106/107 corresponding to channel regions of complementary transistors 104/105 that together comprise the CFET 102. Accordingly, the semiconductor layer 150 may have the materials and vertical thicknesses described with respect to the semiconductor nanostructures 106/107 of fig. 1A and 1B. As will be described in more detail below, the semiconductor fin 149 may be referred to as a hybrid nanostructure, or the semiconductor fin 149 may be patterned to form a hybrid nanostructure.

The sacrificial semiconductor layer 152 includes a semiconductor material different from that of the semiconductor layer 150. Specifically, the sacrificial semiconductor layer 152 includes a material that is selectively etchable relative to the material of the semiconductor layer 150. As will be described in more detail below, the sacrificial semiconductor layer 152 will ultimately be patterned to form sacrificial semiconductor nanostructures. The sacrificial semiconductor nanostructures will eventually be replaced by gate metal substitutes disposed between the semiconductor nanostructures 106. In one example, the sacrificial semiconductor layer 152 may comprise a single crystal semiconductor material, such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In the example process described herein, the sacrificial semiconductor layer 152 comprises SiGe and the semiconductor layer 150 comprises Si. Other materials and configurations may be used for sacrificial semiconductor layer 152 and semiconductor layer 150 without departing from the scope of this disclosure.

In some embodiments, each semiconductor layer 150 comprises intrinsic silicon and each sacrificial semiconductor layer 152 comprises silicon germanium. The sacrificial semiconductor layer may have a relatively low germanium concentration of between 10% and 35%. The concentration in this range may provide sacrificial semiconductor layer 152 that is selectively etchable relative to semiconductor layer 150. In some embodiments, semiconductor layer 150 has a thickness between 2nm and 5 nm. In some embodiments, the sacrificial semiconductor layer 152 has a thickness between 4nm and 10 nm. Other materials, concentrations, and thicknesses may be used for semiconductor layer 150 and sacrificial semiconductor layer 152 without departing from the scope of the present disclosure.

In some embodiments, the semiconductor fin 149 is formed by performing a series of epitaxial growth processes. The first epitaxial growth process grows the lowermost sacrificial semiconductor layer 152 on the substrate 101. The second epitaxial growth process grows the lowermost semiconductor layer 150 on the lowermost sacrificial semiconductor layer 152. An alternating epitaxial growth process is performed to form four lowermost sacrificial semiconductor layers 152 and three lowermost semiconductor layers 150. Depending on the number of desired semiconductor nanostructures of the lower transistor 105 of the CFET 102, more or fewer sacrificial semiconductor layers 152 and semiconductor layers 150 may be formed.

After the semiconductor layer 150 and the sacrificial semiconductor layer 152 associated with the lower transistor 105 have been formed, the layers associated with the isolation structure 126 will be formed. Specifically, an epitaxial growth process is performed to form the lower semiconductor layer 127. In one example, the lower semiconductor layer 127 is intrinsic silicon having a thickness between 1nm and 3 nm. After forming the lower semiconductor layer 127, another epitaxial growth process is performed to form a special sacrificial semiconductor layer 154. The sacrificial semiconductor layer 154 has a composition that is selectively etchable relative to the semiconductor layer 150 and the sacrificial semiconductor layer 152. In the example where sacrificial semiconductor layer 152 is silicon germanium having a relatively low concentration of germanium, sacrificial semiconductor layer 154 may comprise silicon germanium having a relatively high concentration of germanium. In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is greater than 50%.

In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is at least 25% higher than the germanium concentration in sacrificial semiconductor layer 152. For example, if sacrificial semiconductor layer 152 has a germanium concentration of 35%, sacrificial semiconductor layer 154 will have a germanium concentration of greater than or equal to 60%. In some embodiments, the germanium concentration in sacrificial semiconductor layer 154 is 2 to 5 times greater than the germanium concentration in sacrificial semiconductor layer 152. In some embodiments, the germanium concentration of sacrificial semiconductor layer 154 is less than or equal to 80%. The sacrificial semiconductor layer 154 may have a thickness between 5nm and 25nm and a length between 15nm and 30 nm. The thickness of the sacrificial semiconductor layer 154 is greater than the thickness of the sacrificial semiconductor layer 152. The thickness of the sacrificial semiconductor layer 152 is greater than the thickness of the semiconductor layer 150. Other compositions, materials, and thicknesses may be used for sacrificial semiconductor layer 154 without departing from the scope of this disclosure.

After the sacrificial semiconductor layer 154 is formed, an epitaxial growth process is performed to form the upper semiconductor layer 127 on the sacrificial semiconductor layer 154. The upper semiconductor layer 127 may have a composition thickness substantially the same as that of the lower semiconductor layer 127.

After the sacrificial semiconductor layer 154 and the upper semiconductor layer 127 are formed, the upper sacrificial semiconductor layer 152 and the semiconductor layer 150 related to the upper transistor 104 are formed. The upper sacrificial semiconductor layer 152 and the semiconductor layer 150 may be formed using the alternating epitaxial growth process described with respect to the lower semiconductor layer 150 and the sacrificial semiconductor layer 152.

A dummy gate structure 156 has been formed on top of the uppermost semiconductor layer 150. The dummy gate structure 156 may correspond to a fin extending in the Y direction. The dummy gate structure 156 is referred to as a dummy gate structure or "sacrificial gate structure" because the gate electrode of the transistor 102 will be formed to partially replace the dummy gate structure 156.

The dummy gate structure 156 includes a dielectric layer 158. Dielectric layer 158 may include a thin layer of silicon oxide grown on top semiconductor layer 150 via Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). The dielectric layer 158 may have a thickness between 0.2nm and 2 nm. Other thicknesses of materials and deposition processes may be used for dielectric layer 158 without departing from the scope of this disclosure.

The dummy gate structure 156 includes a polysilicon layer 160. The polysilicon layer 160 may have a thickness between 20nm and 100 nm. The polysilicon layer 160 may be deposited by an epitaxial growth, a CVD process, a Physical Vapor Deposition (PVD) process, or an ALD process. Other thicknesses and deposition processes may be used to deposit the polysilicon layer 160 without departing from the scope of the present disclosure.

The dummy gate structure 156 may also include one or more additional dielectric layers over the polysilicon layer 160. Various configurations and materials may be used for the dummy gate structure 156 without departing from the scope of the present disclosure.

Fig. 2B is an X-view of integrated circuit 100 according to some embodiments. In fig. 2B, sidewall spacers 131 have been formed on the sidewalls of the dummy gate structure 156. The sidewall spacers 131 may include a plurality of dielectric layers. Each dielectric layer of the sidewall spacers 131 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. The dielectric layer of sidewall spacer 131 may be deposited by CVD, PVD, ALD or other suitable process.

Fig. 2C is an X-view of integrated circuit 100 according to some embodiments. In fig. 2C, source/drain trenches 164 have been formed through the semiconductor fin 149. The source/drain trench 164 corresponds to a location where the source/drain region 116 and the source/drain region 117 are to be formed. The etching process to form the source/drain trenches 164 etches the semiconductor layer 150, the sacrificial semiconductor layer 152, the semiconductor layer 127, and the sacrificial semiconductor layer 154 to form the semiconductor nanostructures 106 and 107 from the semiconductor layer 150. More specifically, the etching process forms a stack of semiconductor nanostructures 106 and semiconductor nanostructures 107. Semiconductor nanostructure 106 corresponds to a channel region of transistor 104. The semiconductor nanostructure 107 corresponds to a channel region of the transistor 105. The etching process also forms sacrificial semiconductor nanostructures 165 from sacrificial semiconductor layer 152. Sacrificial semiconductor nanostructures 165 are disposed between semiconductor nanostructures 106 and between semiconductor nanostructures 107. Source/drain trenches 164 extend into substrate 101.

The etching process may include one or more anisotropic etching processes that selectively etch the materials of the semiconductor layer 150 and the sacrificial semiconductor layer 152 in a vertical direction. The etching process may include a single step or multiple steps. The etching process may include one or more timed etches. Other types of etching processes may be employed without departing from the scope of the present disclosure.

In fig. 2C, a recessing step has been performed to recess the sacrificial semiconductor nanostructures 165. The recessing process removes the outer portions of the sacrificial semiconductor nanostructures 165 without completely removing the sacrificial semiconductor nanostructures 165. The recessing process may be performed with an isotropic etch that selectively etches the material of the sacrificial semiconductor nanostructures 165 relative to the material of the semiconductor nanostructures 106/107, the sacrificial semiconductor layer 154, and the substrate 101. The isotropic etching process may include a timed etching process. The duration of the etching process is selected to remove only a portion of the sacrificial semiconductor nanostructures 165, but not to completely remove the sacrificial semiconductor nanostructures 165. The result of the etching process is the formation of grooves 166 in the sacrificial semiconductor nanostructures 165.

The etching process may include using SF ₆ 、H ₂ And CF (compact F) ₄ Dry etching of the mixture of (a) is performed. The etching process may etch the sacrificial semiconductor nanostructures 165 at a rate that is greater than 10 times the rate at which the sacrificial semiconductor layer 154 is etched. Other etchants and etching processes may be employed without departing from the scope of this disclosure.

Fig. 2D is an X-view of integrated circuit 100 according to some embodiments. In fig. 2D, the inner spacer 114 has been formed in the recess 166. The inner spacers 114 may be formed by depositing a dielectric layer on the exposed sidewalls of the semiconductor nanostructures 106/107, on the bottom of the source/drain trenches 164, and in the recesses 166 formed in the sacrificial semiconductor nanostructures 165. The dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials without departing from the scope of the present disclosure. The dielectric layer may be formed by CVD, PVD, ALD or via another process. The lateral thickness of the dielectric layer may be between 2nm and 10 nm. Other thicknesses, materials, and deposition processes may be used for the dielectric layer without departing from the scope of the present disclosure.

An etching process is then performed to remove the excess portion of the dielectric layer. The etching process may include an isotropic etching process that etches in all directions. The isotropic etching process is timed such that the dielectric layer is removed at all locations except where the lateral thickness increases due to the grooves 166 in the sacrificial semiconductor nanostructures 165. The result is that the inner spacers 114 remain at the recesses 166 in the sacrificial semiconductor nanostructures 165. Other processes may be employed to form the inner spacer 114 without departing from the scope of the present disclosure.

Fig. 2E is an X-view of integrated circuit 100 according to some embodiments. In fig. 2E, an etching process has been performed to remove the sacrificial semiconductor layer 154 from between the semiconductor layers 127. The etching process may include an isotropic etch that selectively etches the sacrificial semiconductor layer 154 relative to the semiconductor nanostructures 106/107, the substrate 101, and the sacrificial semiconductor layer 165. Because sacrificial semiconductor layer 154 has a significantly different germanium concentration relative to sacrificial semiconductor nanostructures 165, sacrificial semiconductor layer 154 may be selectively etched relative to sacrificial semiconductor nanostructures 165 and semiconductor nanostructures 106/107. In some embodiments, the etching process may include using a CF ₄ Or HBr gas etchant, CF ₄ Or HBr gas, etches sacrificial semiconductor layer 154 at a rate 10 times greater than the etch rates of semiconductor nanostructures 106/107 and semiconductor layer 127. Other etching processes may be employed without departing from the scope of the present disclosure.

As a result of the etching process in fig. 2E, a void 170 is formed between the semiconductor layers 127. As will be described in more detail below, a dielectric layer 129 will be formed in place of the void 170.

Fig. 2F is an X-view of integrated circuit 100 according to some embodiments. In fig. 2F, a dielectric layer 172 has been deposited. A dielectric layer 172 is deposited in the gaps 170 between the semiconductor layers 127 and in the source/drain trenches 164 and over the dummy gate structure 156. Dielectric layer 172 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials without departing from the scope of the present disclosure. The dielectric layer 172 may be deposited using CVD, ALD, or PVD. Other materials and deposition processes may be used for dielectric layer 172 without departing from the scope of the present disclosure.

Fig. 2G is an X-view of integrated circuit 100 according to some embodiments. In fig. 2G, a dielectric layer 129 has been formed between the semiconductor layers 127. Dielectric layer 129 is formed by performing an etching process on dielectric layer 172. The etching process may include anisotropic etching that selectively etches in a downward direction. The etching process removes dielectric layer 172 from all locations except between semiconductor layers 127. Accordingly, dielectric layer 129 is a residue of dielectric layer 172. As will be described in more detail below, the dielectric layer 129 and the semiconductor layer 127 may collectively correspond to a hybrid nanoplatelet that will help provide improved gate metal characteristics.

Although fig. 2G shows dielectric layer 129 having substantially vertical sidewalls, in practice, dielectric layer 129 may include recessed sidewalls. This may be the result of an anisotropic etching process. This may occur because the isotropic etching process may not be perfectly anisotropic. For example, the anisotropic etching process may etch in the downward direction at a rate between 10 and 100 times greater than in the lateral direction. Although relatively small, some etching occurs in the lateral direction, creating a recess in dielectric layer 129. The dielectric layer 129 may have various other configurations without departing from the scope of the present disclosure.

Fig. 2H is an X-view of integrated circuit 100 according to some embodiments. In fig. 2H, a layer of polymeric material 174 has been deposited in the source/drain trench 164. Alternatively, the polymeric material 174 may be replaced with a non-polymeric dielectric material. After deposition of the polymer material 174, an etch back process is performed to reduce the height of the polymer material 174 to a level below the lower semiconductor layer 127.

In fig. 2H, a dielectric layer 176 has been deposited over the polymer material 174, and over the dielectric layer 129, the inner spacers 114, the nanostructures 106, and the sidewalls of the sidewall spacers 131. In some embodiments, dielectric layer 176 includes Al ₂ O ₃ . Dielectric layer 176 may be deposited by CVD, PVD or ALD. Other materials and processes may be used for dielectric layer 176 without departing from the scope of this disclosure. After depositing dielectric layer 176, an anisotropic etching process is performed to remove dielectric layer 176 from the horizontal surfaces of polymer material 174 and dummy gate structure 156.

Fig. 2I is an X-view of integrated circuit 100 according to some embodiments. In fig. 2I, the polymeric material 174 has been removed. The removal of the polymer material 174 exposes the sidewalls of the semiconductor nanostructures 107 and the substrate 101. In fig. 2I, source/drain regions 117 have been formed in source/drain trenches 164 at locations not covered by dielectric layer 176. The source/drain regions 117 may be formed by epitaxial growth from the semiconductor nanostructures 107 as well as from the substrate 101. The source/drain regions 117 comprise a semiconductor material. The semiconductor material may comprise the same semiconductor material as the semiconductor nano-structures 107. Alternatively, the semiconductor material of the source/drain regions 117 may be different from the semiconductor material of the semiconductor nanostructures 107. The source/drain regions 117 may be doped in situ with dopant atoms during the epitaxial growth process. In the example where the lower transistor 105 is a P-type transistor, the source/drain regions 117 may be doped in situ with P-type dopant atoms. The P-type dopant atoms may include boron or other P-type dopant atoms.

Fig. 2J is an X-view of integrated circuit 100 according to some embodiments. In fig. 2J, dielectric layer 176 has been removed. A dielectric layer 180 has been deposited. A polymer layer 182 has also been deposited. Dielectric layer 180 may comprise the same material as dielectric layer 176. The polymer layer 182 may have the same material as the polymer material 174. An etch back process is also performed to reduce the height of the dielectric layer 180 and the polymer layer 182 to expose the sidewalls of the semiconductor nanostructures 106.

Fig. 2K is an X-view of integrated circuit 100 according to some embodiments. In fig. 2K, source/drain regions 116 have been formed in source/drain trenches 164 over dielectric layer 180 and polymer layer 182. The source/drain regions 116 may be formed by epitaxial growth from the semiconductor nanostructures 106. The source/drain regions 116 comprise a semiconductor material. The semiconductor material may include the same semiconductor material as the semiconductor nanostructures 106. Alternatively, the semiconductor material of the source/drain regions 116 may be different from the semiconductor material of the semiconductor nanostructures 106. The source/drain regions 116 may be doped in situ with dopant atoms during the epitaxial growth process. In the example where the upper transistor 104 is an N-type transistor, the source/drain regions 116 may be doped in situ with N-type dopant atoms. The N-type dopant atoms may include phosphorus or other N-type dopant atoms.

Fig. 2L is an X-view of integrated circuit 100 according to some embodiments. In fig. 2L, polymer layer 182 and dielectric layer 180 have been removed. The dielectric layer 130 has been deposited using a conformal deposition process. A dielectric layer 130 is deposited on the exposed sidewalls of the semiconductor layer 127, and the dielectric layer 129, and the internal spacers 114 between the source/drain regions 116 and 117. Dielectric layer 130 is also deposited on the top surfaces of source/drain regions 117, the bottom, side and top surfaces of source/drain regions 116, and sidewall spacers 131 of dummy gate structure 156. The dielectric layer 130 may be deposited by CVD, ALD, or other suitable process. Dielectric layer 130 may include a Contact Etch Stop Layer (CESL). Dielectric layer 130 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

An interlayer dielectric layer 128 has been deposited to cover dielectric layer 130. Interlayer dielectric layer 128 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. The interlayer dielectric layer may be deposited by CVD, PVD or ALD. Other materials and dimensions may be used for dielectric layer 128 and dielectric layer 130 without departing from the scope of the present disclosure.

Fig. 2M is an X-view of integrated circuit 100 according to some embodiments. The X-view of fig. 2M is laterally expanded relative to fig. 2L, thereby showing portions of the laterally adjacent transistors. The dummy gate structure 156 has been removed. After the dummy gate structure 156 is removed, the sacrificial semiconductor nanostructure 165 is removed using an etching process that selectively removes the sacrificial semiconductor nanostructure 165 relative to the semiconductor nanostructure 106/107.

After the sacrificial semiconductor nanostructures 165 are removed, gaps remain where the sacrificial semiconductor nanostructures 165 are located. Exposing the semiconductor nanostructures 106/107. An interfacial gate dielectric layer 108 and a high-K gate dielectric layer 110 are then deposited to surround the semiconductor nanostructures 106/107. Interfacial gate dielectric layer 108 may include an interface betweenTo->Silicon oxide of a thickness therebetween. A high K gate dielectric layer 110 is deposited over the interfacial gate dielectric layer 108 and may comprise hafnium oxide. The high-K dielectric layer may have a thickness of between +.>And->And a thickness therebetween. The material of gate dielectric layers 108 and 110 may be deposited by ALD, CVD, or PVD. Other structures, materials, thicknesses, and deposition processes may be used for the gate dielectric layer without departing from the scope of the present disclosure.

After the interfacial gate dielectric layer 108 and the high-K gate dielectric layer 110 are deposited around the semiconductor nanostructures 106/107, a gate metal 113 is deposited. The gate metal 113 may be deposited by PVD, CVD, ALD or other suitable process. The material or materials of the gate metal 113 are selected to provide a desired work function relative to the semiconductor nano-structures 107 of the P-type transistor 105. In one example, the gate metal 113 comprises titanium aluminum. However, other conductive materials may be used for the gate metal 113 without departing from the scope of the present disclosure.

When the gate metal 113 is initially deposited, the gate metal 113 surrounds the semiconductor nanostructures 106 and the semiconductor nanostructures 107. However, the gate metal 113 has a material that provides a desired work function for the lower transistor 105, and the gate metal 113 may not provide the desired work function for the upper transistor 104. Accordingly, an etch back process is performed. The etch back process removes the gate metal 113 to a level well below the lowermost semiconductor nanostructure 106. In some embodiments, the etch back process removes gate metal 113 to a level approximately midway vertically of dielectric layer 129.

Because of the presence of the dielectric layer 129, the etch-back process may have a duration that reliably removes all of the gate metal 113 directly between the dielectric layer 129 and the lowermost semiconductor nanostructure 106 without removing the gate metal 113 from between the uppermost semiconductor nanostructure 107 and the dielectric layer 129. The result is that the gate metal 113 cannot interfere with the work function of the upper transistor 104.

After the etch back process of the gate metal 113, the gate metal 112 is deposited. The gate metal 112 may be deposited using ALD, PVD, CVD or other suitable deposition process. In one example, the gate metal 112 comprises titanium nitride. Alternatively, the gate metal 112 may comprise any other suitable conductive material. Gate metal 112 surrounds semiconductor nanostructure 106. Specifically, the gate metal 112 is in contact with the high-K gate dielectric 110 surrounding the semiconductor nanostructures 106. The material of the gate metal 112 is selected to provide a desired work function for the transistor 104.

After depositing the gate metal 112, an etch back process is performed to reduce the height of the gate metal 112 above the top semiconductor nanostructure 106. After the etch back process of the gate metal 112, a gate cap metal 132 is deposited over the gate metal 112. The gate cap metal 132 may comprise tungsten, fluorine-free tungsten, or other suitable conductive material. The gate cap metal 132 may be deposited by PVD, CVD, ALD or other suitable deposition process. The gate cap metal 132 may have a vertical thickness between 1nm and 10 nm. Other dimensions may be employed without departing from the scope of the present disclosure.

After depositing the gate cap metal 132, a dielectric layer 134 is deposited. Dielectric layer 134 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. Dielectric layer 134 may be deposited by PVD, CVD, ALD or other suitable deposition process.

Fig. 3A-3E are schematic cross-sectional side views of an integrated circuit 100 including a conductive TSL 250, in accordance with various embodiments. Fig. 4A-16 illustrate intermediate views of the integrated circuit 100, 100A during formation of the front side source/drain contacts 220F, the back side source/drain contacts 220B, and the conductive TSL 250, in accordance with various embodiments. Fig. 3A is a schematic cross-sectional side view of integrated circuit 100 along line A-A of fig. 1A. Fig. 3B is a schematic cross-sectional side view of integrated circuit 100 along line B-B of fig. 1A. Fig. 3C is a schematic cross-sectional side view of integrated circuit 100 along line C-C of fig. 1A. Fig. 3D is a schematic cross-sectional side view of integrated circuit 100 along line D-D of fig. 1A. Fig. 3E is a schematic cross-sectional side view of integrated circuit 100 along line E-E of fig. 1A.

Fig. 17 and 18 illustrate a flow chart of a method of forming an integrated circuit, in accordance with various embodiments. The method of fig. 17 may be used to form integrated circuit 100 and the method of fig. 18 may be used to form integrated circuit 100A, but is not limited to the structures shown in fig. 3A-16. In some embodiments, the methods 1000, 2000 of forming a semiconductor structure include a plurality of operations. Methods 1000, 2000 of forming semiconductor structures in accordance with one or more embodiments will be further described. It should be noted that the operations of the methods 1000, 2000 may be rearranged or otherwise modified within the scope of the various aspects. It should also be noted that additional processes may be provided before, during, and after the methods 1000, 2000, and that some other processes may be described only briefly herein.

Referring to fig. 3A, front side source/drain contacts 220F include silicide 120, liner or barrier layer 122, and metal layer 124. Liner layer 122 and metal layer 124 extend through interlayer dielectric (ILD) layer 140 and between adjacent gate structures 112 to contact source/drain regions 116. For example, the pad layer 122 may contact the silicide 120, and the metal layer 124 may contact the pad layer 122, as shown.

The backside source/drain contacts 220B include silicide 121, a liner or barrier layer 123, and a metal layer 125. The liner layer 123 and the metal layer 125 extend through the backside ILD layer 350 and optionally through the substrate 101 to contact the source/drain regions 117. For example, liner layer 123 may contact silicide 121, and metal layer 125 may contact liner layer 123, as shown. In some embodiments, the substrate 101 is not present, and a dielectric layer may be present between the backside ILD layer 350 and the source/drain regions 117, the internal spacers 114, and the interface dielectric 108.

Referring to fig. 3B, conductive TSL 250 electrically couples one or more front side source/drain contacts 220F to one or more back side source/drain contacts 220B. In the example shown in fig. 3B, the conductive TSL 250 extends from a front side source/drain contact 220F coupled to the source/drain region 116 of the upper transistor 104 to a back side source/drain contact 220B coupled to the source/drain region 117 of the lower transistor 105.

Further views of conductive TSL 250 are shown in fig. 3D and 3E. Front side source/drain contacts 220F coupled to conductive TSL 250 may contact an upper surface of conductive TSL 250 and may optionally contact sidewalls of conductive TSL 250. The backside source/drain contacts 220B coupled to the conductive TSL 250 may be in contact with a lower surface of the conductive TSL 250 and may optionally be in contact with sidewalls of the conductive TSL 250.

Referring again to fig. 3B, conductive TSL 250 includes a lower portion 250B and an upper portion 250T. The lower portion 250B and the upper portion 250T may be a continuous structure. In some embodiments, for example, when forming the lower portion 250B and the upper portion 250T in separate process operations, a visible interface exists between the lower portion 250B and the upper portion 250T. The lower portion 250B is wider than the upper portion 250T in the X-axis direction. Thus, conductive TSL 250 may be said to be "L-shaped". The conductive TSL 250 overlaps the first source/drain region 116L and the first source/drain region 117L in the Y-axis direction and does not substantially overlap the second source/drain region 116R and the second source/drain region 117R in the Y-axis direction, as shown by the dashed lines in fig. 3B. The lower portion 250B of the conductive TSL 250 extends below the second source/drain regions 116R, 117R, albeit offset in the Y-axis direction, to connect to the backside source/drain contacts 220B.

A dielectric layer 260 is located on the conductive TSL 250. The dielectric layer 260 and the conductive TSL 250 may be collectively referred to as an "interconnect structure". The dielectric layer 260 may be in contact with the upper surface of the lower portion 250B and may be in contact with the sidewalls of the upper portion 250T. The dielectric layer 260 overlaps the second source/drain regions 116R, 117R, which is advantageous in reducing parasitic capacitance between the conductive TSL 250 and the second source/drain regions 116R, 117R. The dielectric layer 260 overlaps the gate metal 112, 113 of one or more of the first transistor 104 and the second transistor 105, which is advantageous for reducing parasitic capacitance between the conductive TSL 250 and the gate metal 112, 113. Dielectric layer 260 may be or include SiO ₂ Nitride (e.g., siN), low-k dielectrics, etc.

Dielectric layer 260 may be adjacent to conductive TSL 250 at sidewalls 250W1 and upper surface 250W2 of conductive TSL 250. As shown, the sidewalls 250W1 may extend in the X-axis direction to be substantially coplanar with the sidewalls of the source/drain regions 116, 117. In some embodiments, the sidewall 250W1 is located between the sidewalls of the second source/drain regions 116R, 117R and the first source/drain regions 116L, 117L. In some embodiments, the sidewalls 250W1 are located between the sidewalls of the source/drain regions 116R such that the upper portion 250T only partially overlaps the source/drain regions 116R, 117R. In some embodiments, the sidewall 250W1 is substantially coplanar with a vertical sidewall of the pad layer 122 or with a vertical sidewall of the conductive layer 124. The wider upper portion 250T may reduce the resistance of the conductive TSL 250 and the narrower upper portion 250T may reduce the parasitic capacitance of the conductive TSL 250. The wider upper portion 250T may improve the positioning of the front side source/drain contacts 220F on the upper portion 250T. For example, when sidewall 250W1 does not extend beyond the vertical sidewalls of conductive layer 124 and liner layer 122, front side source/drain contact 220F may extend into dielectric layer 260 due to stack offset during a photolithographic operation used to form an opening in ILD 140 (front side source/drain contact 220F is formed in ILD 140).

The upper surface 250W2 is generally below the upper surface of the substrate 101 such that the lower portion 250B does not substantially overlap the source/drain regions 117 and the gate metal 113. The vertical distance between the upper surface 250W2 and the upper surface of the substrate 101 may be in the range of about 0nm to about 100nm, although other vertical distances greater than 100nm are within the intended scope of the embodiments. The greater height of the lower portion 250B reduces the resistance of the conductive TSL 250. In some embodiments, the width of the dielectric layer 260 is in the range of about 0nm to about 100nm, and the height of the dielectric layer 260 is in the range of about 0nm to about 150nm, although widths greater than 100nm and heights greater than 150nm are also within the intended scope of the embodiments.

The formation of conductive TSL 250 and front side source/drain contacts 220F and back side source/drain contacts 220B along with gate isolation structures 262 is shown in fig. 4A-16.

In fig. 4A to 4E, corresponding to operations 1100, 2100 of fig. 17 and 18, upper and lower transistors have been formed, and corresponding to operations 1200, 2200 of fig. 17 and 18, openings 45 have been formed. Forming opening 45 may include forming a first mask 400 over gate metal 112, high-K gate dielectric layer 110, sidewall spacers 131, and dielectric cap 128C. The first mask 400 may include a first mask layer 400A and a second mask layer 400B. One or both of the first mask layer 400A and the second mask layer 400B may be a hard mask layer, such as an inorganic dielectric material layer. A photoresist layer 410 is formed over the first mask 400, and the photoresist layer 410 may be multi-layered. An opening may be formed in the photoresist layer 410, and the first mask 400 may be patterned (e.g., etched) through the opening in the photoresist layer 410 to expose the underlying structure.

Fig. 4A and 4C to 4E show a first sacrificial layer 102 under the substrate 101 and a second sacrificial layer 103 under the first sacrificial layer 102. According to various embodiments, the first sacrificial layer 102 may be a semiconductor layer, such as a silicon germanium layer. In some embodiments, the second sacrificial layer 103 may be a silicon layer, such as an undoped silicon layer.

After forming the opening 45 in the first mask 400, the opening 45 may be extended downward until reaching the second sacrificial layer 103. The extension opening 45 may include a plurality of removal operations. For example, one or more anisotropic etching operations may be performed to remove the materials of gate metals 112, 113, high-K gate dielectric layer 110, interfacial gate dielectric layer 108, nanostructures 106, 107, and isolation structures 126, as shown in fig. 4C. The same or additional anisotropic etching operations may be performed to remove the material of the dielectric layers 128, 130, the dielectric cap 128C, and the isolation structures 36 (e.g., shallow trench isolation or "STI" regions 36), as shown in fig. 4D and 4E.

In fig. 4D and 4E, the width of the opening 45 in the Y-axis direction may be such that the dielectric layer 130 remains on the sidewalls of the source/drain regions 116, 117 when the dielectric layer 128 is etched. In some embodiments, the opening 45 may expose one or more portions of the dielectric layer 130 on the sidewalls of the source/drain regions 116, 117. Fig. 4D and 4E show fin spacer 235 and liner layer 235A that may be present between fin spacer 235 and source/drain regions 117. Fig. 4A, 4D, and 4E illustrate a semiconductor portion 117A disposed under the source/drain region 117. In some embodiments, semiconductor portion 117A is a sacrificial material structure that is replaced with backside source/drain contacts 220B in a subsequent operation. In some embodiments, semiconductor portion 117A is undoped silicon.

In fig. 5A to 5E, and corresponding to operations 1300, 2300 of fig. 17 and 18, after forming the opening 45, a gate isolation layer 262A may be formed in the opening 45, and then a conductive layer 250L may be formed in the opening 45, as shown in fig. 5C. In some embodiments, the gate isolation layer 262A is or includes a dielectric material, such as SiN, siO, siCN, siON, siOCN, combinations thereof, and the like. In some embodiments, gate isolation layer 262A is a low-K dielectric layer. The gate spacer 262A may be deposited by a suitable deposition operation such as PVD, CVD, ALD. The gate spacer 262A may be a conformal layer having a thickness in the range of about 5nm to about 30n m. Gate spacer 262A may be adjacent to or in contact with exposed sidewalls of opening 45, such as sidewalls of gate metals 112, 113, isolation region 36, and dielectric layer 128. The gate isolation layer 262A may be on the upper surface of the second sacrificial layer 103 or in contact with the upper surface of the second sacrificial layer 103.

After forming the gate isolation layer 262A, a conductive layer 250L is formed in the remaining portion of the opening 45. The conductive layer 250L may be or include one or more of W, co, cu, ru, etc., and the conductive layer 250L may be formed by PVD, CVD, ALD or other suitable deposition process. The width of the conductive layer 250L in the Y-axis direction may be in the range of about 5nm to about 100 nm.

As shown in fig. 5F and 5G, in some embodiments, an optional liner layer 262L may be formed prior to forming the gate isolation layer 262A. The liner layer 262L may be or include a low-k dielectric such as SiLK, porous dielectric, etc., and the liner layer 262L is advantageous for reducing capacitance due to the gate isolation structure 262. The liner layer 262L may be formed by PVD, CVD, ALD or other suitable deposition operation. After forming the liner layer 262L, a gate isolation layer 262A may be formed on the liner layer 262L. In embodiments including the liner layer 262L, the thickness of the gate isolation layer 262A may be thinner, such as in the range of about 3nm to about 15nm, although a thickness greater than 15nm is also within the contemplation of the embodiments. Typically, the liner layer 262L has a lower dielectric constant than the gate isolation layer 262A. In some embodiments, the gate isolation layer 262A is a low K dielectric layer and the liner layer 262L has a higher dielectric constant than the gate isolation layer 262A.

In fig. 6A-6E, a suitable removal process, such as CMP, grinding, etching, or other similar process, is performed to remove material over dielectric layer 128, including excess material of gate isolation layer 262A, excess material of conductive layer 250L, first mask 400, and dielectric cap 128C. The gate metal 112 and the sidewall spacers 131 may also be slightly recessed by a removal process. After the removal process, the upper surfaces of the gate isolation layer 262A, the conductive layer 250L, the gate metal 112, the sidewall spacers 131, and the dielectric layers 128, 130 may be substantially coplanar.

In fig. 7A to 7E, corresponding to operation 1400 of fig. 17, an opening 47 is formed in the conductive layer 250L where the conductive TSL 250 is formed. Forming the opening 47 may include forming a second mask 700 and a photoresist 710 over the second mask 700. The second mask 700 may include a first mask layer 700A and a second mask layer 700B. One or more of the first mask layer 700A and the second mask layer 700B may be a hard mask layer. The opening 47 may be formed by patterning the photoresist 710 to expose the second mask 700, and then etching the exposed portion of the second mask 700 to expose a portion of the conductive layer 250L. Portions of conductive layer 250L are then etched through second mask 700 to form openings 47. The etch may be any suitable etch operation that is selective to the material of conductive layer 250L without substantially attacking the material of gate isolation structure 262. The opening 47 may have a width in the range of about 0nm to about 100nm and a height in the range of about 0nm to about 150 nm. The opening 47 may be referred to as a "kerf region" of the conductive TSL 250.

The formation of the conductive TSL 250 in the above-described embodiments includes forming a conductive layer 250L on top of the metal gate isolation structure 262 and then removing portions thereof to form a kerf region that is replaced by a dielectric layer 260 formed therein. In some embodiments, the kerf regions may be formed without replacing portions of the conductive layer 250L with the dielectric layer 260. For example, a lower portion of the conductive TSL 250 may be formed in a first operation. The lower portion may have a height that is less than the height of the first opening in which the conductive TSL 250 will be formed. Then, in a second operation, a dielectric layer 260 may be formed in the remaining space of the first opening over the lower portion of the conductive TSL 250. After forming the dielectric layer 260, the dielectric layer 260 may be patterned to form a second opening exposing a lower portion of the conductive TSL 250, after which an upper portion of the conductive TSL 250 that is narrower than the lower portion may be deposited in the second opening. CMP may be performed to remove excess material of the upper portion over the second opening.

In fig. 8A through 8E, corresponding to operation 1500 of fig. 17, after forming the opening 47, the second mask 700 and the photoresist 710 may be removed, and the dielectric layer 260 may be formed in the opening 47, as shown. Dielectric layer 260 may follow the shape of opening 47. The dielectric layer 260 may have a width in the range of about 0nm to about 100nm and a height in the range of about 0nm to about 150 nm. Forming the dielectric layer 260 may include PVD, CVD, ALD or other suitable deposition operations. After deposition of dielectric layer 260, excess material of dielectric layer 260 over the upper surface of conductive TSL 250 may be removed by a suitable operation, such as CMP. Dielectric layer 260 can be said to be located in the kerf region of conductive TSL 250.

In fig. 9A through 9E, corresponding to operation 1600 of fig. 17, after forming the dielectric layer 260, front side source/drain contacts 220F may be formed. Forming the front side source/drain contacts 220F may include forming ILD 140, patterning ILD 140 to form openings exposing source/drain regions 116, and then forming front side source/drain contacts 220F in the openings. For example, the liner layer 122 may be formed by depositing its material in the openings over the source/drain regions 116. After deposition of the liner layer 122, a conductive layer 124 may be formed in the opening on the liner layer 122. A suitable annealing operation may be performed to form silicide 120, the annealing operation being after formation of liner layer 122, and the annealing operation may be before or after formation of conductive layer 124. Silicide 120 may comprise titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicide. The front side source/drain contacts 220F may also include a conductive or liner layer 122 disposed on the silicide 120. Conductive layer 122 may comprise titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive material. The front side source/drain contacts 220F may also include a conductive layer 124 on the conductive layer 122. Conductive layer 124 may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive material. Other materials and configurations may be used for the front side source/drain contacts 220F without departing from the scope of the present disclosure. After forming the front side source/drain contacts 220F, a Chemical Mechanical Planarization (CMP) process may be performed.

After the front side source/drain contacts 220F are formed, an etch stop layer 142 and a second ILD 360 may be formed over the front side source/drain contacts 220F. In a subsequent operation, metallization features, such as vias, wires, or traces, may be formed in the second ILD 360 to contact the front side source/drain contacts 220F to form electrical connections between the source/drain regions 116 and other transistors of the integrated circuit 100. For example, as shown in fig. 9E, source/drain vias 320 are formed through the second ILD 360 and the etch stop layer 142 to be positioned on the conductive layer 124 of the front side source/drain contacts 220F.

Fig. 9D and 9E show the front side source/drain contacts 220F in the YZ plane. Silicide 120 is omitted in fig. 9D and 9E. As shown, the front side source/drain contact 220F is positioned on one of the source/drain region 116, the gate isolation layer 262A, and the conductive TSL 250 (fig. 9D) or the dielectric layer 260 (fig. 9E). In fig. 9E, because the front side source/drain contact 220F may be positioned on the dielectric layer 260, the front side source/drain contact 220F may be larger, thereby reducing resistance, and the overlay accuracy between the front side source/drain contact 220F and the source/drain region 116 may be relaxed, thereby resulting in better yield.

The source/drain contacts 118 may include silicide 120. Silicide 120 is formed at the top of source/drain regions 116.

Fig. 9F and 9G illustrate a conductive TSL 250 having a different shape than that illustrated in fig. 9B. In some embodiments, conductive TSL 250 is formed with tapered sidewalls 250W3. The conductive TSL 250 has a pentagonal shape with five sides. As shown, among the four source/drain regions 116L, 116R, 117L, 117R corresponding to two adjacent CFETs, the conductive TSL 250 may completely overlap with two or three of the source/drain regions (e.g., the source/drain regions 116L, 117R of fig. 9F) and may partially overlap with one or two of the source/drain regions (e.g., the source/drain region 116R of fig. 9F) or not. The pentagonal shape shown in fig. 9F and 9G reduces the resistance of the conductive TSL 250 while maintaining some reduction in parasitic capacitance between the conductive TSL 250 and the source/drain regions 116R, 117R.

It should be appreciated that other shapes or contours of the conductive TSL 250 in the XZ plane are included in various embodiments. For example, the conductive TSL 250 may have curved sidewalls instead of tapered sidewalls 250W3. The curved sidewalls may allow the first source/drain regions 116R to completely overlap the conductive TSL 250 while increasing the volume of the conductive TSL 250, which reduces its resistance.

In fig. 10A-10E, corresponding to operation 1700 of fig. 17, backside source/drain contacts 220B are formed. Forming the backside source/drain contacts 220B may include flipping the integrated circuit 100 such that the bottom of the substrate 101 and the sacrificial layers 102, 103 are exposed. The sacrificial layers 103, 102 may be removed, for example, by grinding or etching, before the backside source/drain contacts 220B are formed, and then the third ILD 350 may be formed by depositing a dielectric material on the backside of the substrate 101. The third ILD 350 may comprise one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. The third ILD 350 may be deposited by CVD, PVD or ALD. A CMP process may then be performed. After forming the third ILD 350, openings may be formed in the third ILD 350 and the substrate 101 to expose the source/drain regions 117 and the bottom surface of the conductive TSL 250.

A liner layer 123 and a conductive layer 125 may then be deposited in the opening to contact the source/drain regions 117 and the conductive TSL 250. As shown in fig. 10E, backside source/drain contacts 220B contacting conductive TSL 250 may be positioned on conductive TSL 250, gate isolation structures 262, and source/drain regions 117. For example, the backside source/drain contacts 220B may be in contact with the bottom surface of the conductive TSL 250 and with the sidewalls of the conductive TSL 250. Other backside source/drain contacts 220B that do not contact the conductive TSL 250 may be separated from the conductive TSL 250 by isolation regions 36, dielectric layer 128, and gate isolation structure 262.

The backside source/drain contacts 220B may include silicide 121, with silicide 121 omitted in fig. 10D and 10E. Silicide 121 is formed at the bottom of source/drain regions 117. Silicide 121 may comprise titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicide. The backside source/drain contacts 220B may further include a conductive or liner layer 123 disposed on the silicide 121. The conductive layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive material. The backside source/drain contacts 220B may also include a conductive layer 125 on the conductive layer 123. Conductive layer 125 may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive material. Other materials and configurations may be used for the backside source/drain contacts 220B without departing from the scope of the present disclosure. After the backside source/drain contacts 220B are formed, a CMP process may be performed.

Fig. 11A-14E illustrate forming a conductive TSL 250 having an inverted shape in an integrated circuit 100A in accordance with various embodiments.

In fig. 11A to 11E, corresponding to operation 2400 of fig. 18, after the operations shown in fig. 6A to 6E, front side source/drain contacts 220F are formed similar to that described with reference to fig. 9A to 9E, but before forming openings 47 in conductive layer 250L. As shown in fig. 11B and 11E, one or more front side source/drain contacts 220F may be positioned on the conductive layer 250L and the source/drain regions 116. A detailed operation of forming the front-side source/drain contacts 220F is described with reference to fig. 9A to 9E.

In fig. 12A to 12G, after the front side source/drain contacts 220F are formed, the integrated circuit 100A may be flipped over, and the second sacrificial layer 103 may be removed to expose the first sacrificial layer 102. A fourth mask 800 and a photoresist 810 may be formed on the first sacrificial layer 102, and then the fourth mask 800 may be patterned using the photoresist 810 to form the opening 53. The fourth mask 800 may be a hard mask, and may include a first mask layer 800A and a second mask layer 800B. Corresponding to operation 2500 of fig. 18, the opening 53 may extend into the conductive layer 250L to form a conductive TSL 250 having an inverted L shape as shown in fig. 12B.

In fig. 12F and 12G, in some embodiments, openings 53A are formed instead of openings 53. As shown, opening 53A forms tapered sidewall 250W3. The openings 53, 53A are formed similarly to the openings described with reference to fig. 7A to 7E.

In fig. 13A to 13E, a dielectric layer 260 is formed in the opening 53 corresponding to operation 2600 of fig. 18. Fig. 13F and 13G illustrate the formation of a dielectric layer 260 in the opening 53A. The formation of the dielectric layer 260 is similar to that described with reference to fig. 8A-8E.

In fig. 14A-14E, corresponding to operation 2700 of fig. 18, backside source/drain contacts 220B are formed. The formation of the backside source/drain contacts 220B is similar to the formation of the backside source/drain contacts described with reference to fig. 10A-10E. Due to the presence of the dielectric layer 260, one or more backside source/drain contacts 220B may be positioned partially on the dielectric layer 260, e.g., the left bottom backside source/drain contact 220B shown in fig. 14E. This is advantageous for relaxing the overlay accuracy of forming the backside source/drain contacts 220B.

Fig. 15 shows an integrated circuit 100 having an L-shaped conductive TSL 250 and a pad layer 262L. The liner layer 262L extends vertically from the upper surface of the gate metal 112 to the bottom surface of the isolation region 36 or the top surface of the backside ILD layer 350.

Fig. 16 shows an integrated circuit 100A with an inverted L-shaped conductive TSL 250 and a pad layer 262L. The liner layer 262L extends vertically from the upper surface of the gate metal 112 to the bottom surface of the isolation region 36 or the top surface of the backside ILD layer 350.

Embodiments of the present disclosure provide integrated circuits with CFETs having improved electrical characteristics. The CFET includes a first transistor vertically stacked on a second transistor. The first transistor and the second transistor each have a plurality of semiconductor nanostructures that function as channel regions for the first transistor and the second transistor. The first gate metal surrounds the semiconductor nanostructure of the first transistor. The second gate metal surrounds the semiconductor nanostructure of the second transistor. The CFET includes an isolation structure disposed between a lowermost semiconductor nanostructure of the first transistor and an uppermost semiconductor nanostructure of the second transistor. The CFET includes a gate isolation structure with an embedded conductive Through Silicon Layer (TSL) having a cut-out region that reduces parasitic capacitance.

This helps ensure that the conductive TSL does not excessively increase the parasitic capacitance of nearby gate metal and/or source/drain regions. Furthermore, the presence of the dielectric layer in the cut-out region may relax the overlay accuracy of forming the source/drain contacts. This results in a better functioning CFET, a better functioning integrated circuit, and increased wafer yield.

In some embodiments, a device comprises: a complementary transistor, the complementary transistor comprising: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region overlapping the first source/drain region and a fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent to the first transistor and the second transistor; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnection structure comprises: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being located in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region, or both the fourth source/drain region and the second source/drain region; and a dielectric layer located in the opening and on the conductive layer in the gate isolation structure.

In some embodiments, the conductive layer comprises: a lower portion; and an upper portion located on the lower portion, the upper portion being narrower than the lower portion.

In some embodiments, the upper portion is in contact with a first source/drain contact and the lower portion is in contact with a second source/drain contact.

In some embodiments, the upper portion overlaps the first source/drain region and the third source/drain region.

In some embodiments, the conductive layer includes tapered sidewalls that contact the dielectric layer.

In some embodiments, the conductive layer has an inverted L-shaped profile.

In some embodiments, the parasitic capacitance between the conductive layer and the second and fourth source/drain regions is less than the parasitic capacitance between the conductive layer and the first and third source/drain regions.

In some embodiments, the semiconductor device further comprises: a third source/drain contact electrically coupled to the fourth source/drain region, the third source/drain contact being positioned on the dielectric layer.

In some embodiments, the first source/drain contact is positioned on the third source/drain region, the gate isolation structure, and the conductive layer.

In some embodiments, the gate isolation structure includes: a first dielectric layer; and a second dielectric layer located between the first dielectric layer and the conductive layer, the second dielectric layer having a higher dielectric constant than the first dielectric layer.

In some embodiments, a method comprises: forming a first transistor and a second transistor stacked over the first transistor; forming a first opening adjacent to the first transistor and the second transistor; forming a gate isolation layer in the first opening; forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening; forming an incision tract in the conductive layer; forming a dielectric layer on the conductive layer in the cut region; forming front side source/drain contacts in contact with the second transistor and the conductive layer; and forming backside source/drain contacts in contact with the first transistor and the conductive layer.

In some embodiments, the cutout region is rectangular.

In some embodiments, the incision tract is triangular.

In some embodiments, forming the gate spacer includes: forming a first dielectric layer in the first opening; and forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a higher dielectric constant than the first dielectric layer.

In some embodiments, forming the front side source/drain contacts includes: forming a second opening exposing the source/drain region of the second transistor, recessing a portion of the gate isolation layer, and exposing an upper surface of the conductive layer; and forming front side source/drain contacts in the second opening.

In some embodiments, the method further comprises: a second front side source/drain contact is formed positioned on the dielectric layer.

In some embodiments, a method comprises: forming a first transistor and a second transistor stacked over the first transistor; forming a first opening adjacent to the first transistor and the second transistor; forming a gate isolation layer in the first opening; forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening; forming front side source/drain contacts in contact with the upper surfaces of the second transistor and the conductive layer; forming a cut region in the conductive layer after forming the front side source/drain contacts; forming a dielectric layer on the conductive layer in the cut region; and forming backside source/drain contacts in contact with the first transistor and the conductive layer.

In some embodiments, forming the incision tract comprises: portions of the conductive layer that overlap respective gate metals of the first transistor and the second transistor are removed.

In some embodiments, forming the incision tract comprises: the conductive layer is etched from a side of the conductive layer vertically opposite the front side source/drain contacts.

In some embodiments, the conductive layer has tapered sidewalls after etching.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a complementary transistor, the complementary transistor comprising:

a first transistor having a first source/drain region and a second source/drain region; and

a second transistor stacked on the first transistor and having a third source/drain region overlapping the first source/drain region and a fourth source/drain region overlapping the second source/drain region;

a first source/drain contact electrically coupled to the third source/drain region;

A second source/drain contact electrically coupled to the second source/drain region;

a gate isolation structure adjacent to the first transistor and the second transistor; and

an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact, and comprising:

a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being located in the gate isolation structure;

an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region, or both the fourth source/drain region and the second source/drain region; and

a dielectric layer is located in the opening and on the conductive layer in the gate isolation structure.

2. The semiconductor device of claim 1, wherein the conductive layer comprises:

a lower portion; and

an upper portion located on the lower portion, the upper portion being narrower than the lower portion.

3. The semiconductor device of claim 2, wherein the upper portion is in contact with the first source/drain contact and the lower portion is in contact with the second source/drain contact.

4. The semiconductor device of claim 2, wherein the upper portion overlaps the first and third source/drain regions.

5. The semiconductor device of claim 1, wherein the conductive layer comprises tapered sidewalls in contact with the dielectric layer.

6. The semiconductor device of claim 1, wherein the conductive layer has an inverted L-shaped profile.

7. The semiconductor device of claim 1, wherein a parasitic capacitance between the conductive layer and the second and fourth source/drain regions is less than a parasitic capacitance between the conductive layer and the first and third source/drain regions.

8. The semiconductor device of claim 1, further comprising:

a third source/drain contact electrically coupled to the fourth source/drain region, the third source/drain contact being positioned on the dielectric layer.

9. A method of forming a semiconductor device, comprising:

forming a first transistor and a second transistor stacked over the first transistor;

forming a first opening adjacent to the first transistor and the second transistor;

Forming a gate isolation layer in the first opening;

forming a conductive layer on the gate isolation layer, wherein the conductive layer is positioned in the first opening;

forming an incision tract in the conductive layer;

forming a dielectric layer on the conductive layer in the kerf region;

forming front side source/drain contacts in contact with the second transistor and the conductive layer; and

backside source/drain contacts are formed in contact with the first transistor and the conductive layer.

10. A method of forming a semiconductor device, comprising:

forming a gate isolation layer in the first opening;

forming front side source/drain contacts in contact with the second transistor and an upper surface of the conductive layer;

forming a cut-out region in the conductive layer after forming the front side source/drain contacts;

forming a dielectric layer on the conductive layer in the kerf region; and