CN117276145A - Chip etching process optimization method and system - Google Patents
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Abstract
The invention discloses a chip etching process optimization method and a chip etching process optimization system, which relate to the technical field of chip manufacturing, and the method comprises the following steps: obtaining etching conditions for optimizing etching process parameters of a target chip; constructing a wet etching process parameter adjustment domain and an etching optimization function; respectively performing simulated wet etching on the target chip, and acquiring a plurality of size information sets after the simulated etching; constructing modeling information of a plurality of chip channels for simulating etching; calculating to obtain a plurality of guide fitness and a plurality of subordinate fitness; calculating to obtain a plurality of microsteps; and combining a plurality of guide step sizes and a plurality of micro step sizes, performing iterative optimization until reaching the preset optimizing times, and obtaining optimal etching process parameters as an etching process optimizing result. The invention solves the technical problems of poor etching quality and low process optimization efficiency in the prior art when the chip is manufactured by wet etching, and achieves the technical effects of improving the etching process optimization efficiency of the chip and improving the etching quality.
Description
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to a chip etching process optimization method and system.
Background
The control of parameters in the wet etching process plays a critical role in the quality of the chip. In the prior art, although an intelligent neural network model is utilized to learn etching process parameters in the process of optimizing the etching process, the process optimization period is overlong and a plurality of inferior solutions exist due to the fact that the data size to be analyzed is overlarge in the learning iteration process, and the optimization result cannot meet the requirements. In the prior art, when a chip is manufactured by wet etching, the technical problems of poor etching quality and low process optimization efficiency exist.
Disclosure of Invention
The application provides a chip etching process optimization method and system, which are used for solving the technical problems of poor etching quality and low process optimization efficiency in the prior art when a chip is manufactured by wet etching.
In view of the above problems, the present application provides a method and a system for optimizing an etching process of a chip.
In a first aspect of the present application, there is provided a method for optimizing an etching process of a chip, the method comprising:
according to design information of a target chip to be subjected to wet etching, etching conditions for optimizing etching process parameters of the target chip are obtained;
according to the wet etching process parameter adjustment range of the target chip, constructing a wet etching process parameter adjustment domain, and constructing an etching optimization function based on the purpose that the etched chip size approaches design information;
randomly generating a plurality of guide solutions in the wet etching process parameter adjustment domain, respectively generating a plurality of subordinate solutions in the range of the guide step length of the guide solutions, respectively performing simulated wet etching on the target chip, and acquiring a plurality of size information sets after the simulated etching;
constructing a plurality of chip channel modeling information for simulating etching according to the plurality of size information sets, wherein the plurality of chip channel modeling information comprises a plurality of etching depth information, and a plurality of side etching amount information sets are obtained in a dividing manner in the depth direction;
according to the etching depth information and the side etching amount information sets, combining design information, analyzing and calculating to obtain etching depth compliance information and side etching amount compliance information, and calculating to obtain guide fitness and subordinate fitness based on the etching optimization function;
according to the guiding fitness, calculating and obtaining a plurality of microsteps for updating a plurality of subordinate solutions;
and updating the plurality of guide solutions and the plurality of slave solutions by adopting a plurality of guide step sizes and a plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as an etching process optimization result.
In a second aspect of the present application, there is provided an etching process optimization system for a chip, the system comprising:
the etching condition acquisition module is used for acquiring etching conditions for optimizing etching process parameters of the target chip according to the design information of the target chip to be subjected to wet etching;
the optimization function construction module is used for constructing a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip and constructing an etching optimization function based on the purpose that the etched chip size approaches to design information;
the dimension information set acquisition module is used for randomly generating a plurality of guide solutions in the wet etching process parameter adjustment domain, generating a plurality of slave solutions in the range of the guide step length of the guide solutions respectively, respectively performing simulated wet etching on the target chip, and acquiring a plurality of dimension information sets after the simulated etching;
the side etching quantity acquisition module is used for constructing a plurality of chip channel modeling information for simulating etching according to a plurality of size information sets, wherein the plurality of chip channel modeling information comprises a plurality of etching depth information, and the plurality of chip channel modeling information sets are divided and acquired in the depth direction;
the fitness calculation module is used for obtaining a plurality of pieces of etching depth compliance information and a plurality of pieces of side etching fitness information through analysis and calculation according to a plurality of pieces of etching depth information and a plurality of pieces of side etching fitness information sets and combining design information, and obtaining a plurality of pieces of guiding fitness and a plurality of pieces of subordinate fitness through calculation based on the etching optimization function;
the micro-step calculation module is used for calculating and acquiring a plurality of micro-steps for updating a plurality of slave solutions according to the plurality of guide fitness;
the process optimization result setting module is used for updating the plurality of guide solutions and the plurality of slave solutions by adopting the plurality of guide step sizes and the plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as etching process optimization results.
One or more technical solutions provided in the present application have at least the following technical effects or advantages:
according to the method, etching conditions for optimizing etching process parameters of a target chip are obtained according to design information of the target chip to be subjected to wet etching, then a wet etching process parameter adjustment domain is constructed according to a wet etching process parameter adjustment range of the target chip, an etching optimization function is constructed based on the fact that the etched chip size is close to the design information, a plurality of guide solutions are randomly generated in the wet etching process parameter adjustment domain, a plurality of subordinate solutions are generated in the guide step length range of the plurality of guide solutions respectively, simulated wet etching of the target chip is conducted respectively, a plurality of size information sets after simulated etching are obtained, then a plurality of chip channel modeling information for simulated etching is constructed according to the plurality of size information sets, a plurality of etching depth information sets are included in the plurality of chip channel modeling information sets, a plurality of side etching amount information sets are obtained in a dividing mode in the depth direction, a plurality of etching depth information sets and a plurality of side etching amount information sets are combined, a plurality of etching depth compliance information and a plurality of side etching amount compliance information are obtained through analysis and calculation based on the optimization function, a plurality of subordinate adaptation and a plurality of subordinate adaptation degrees are obtained through calculation, and a plurality of subordinate adaptation steps are obtained through calculation according to the optimization function; and updating the plurality of guide solutions and the plurality of slave solutions by adopting a plurality of guide step sizes and a plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as an etching process optimization result. The technical effects of efficiently and accurately optimizing the chip etching process and improving the reliability of the etching process are achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of an etching process optimization method of a chip according to an embodiment of the present application;
fig. 2 is a schematic flow chart of obtaining a plurality of side etching amount information sets in an etching process optimization method of a chip according to an embodiment of the present application;
fig. 3 is a schematic flow chart of calculating and obtaining a plurality of guiding fitness and a plurality of subordinate fitness in an etching process optimization method of a chip according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an etching process optimization system for a chip according to an embodiment of the present application.
Reference numerals illustrate: the device comprises an etching condition acquisition module 11, an optimization function construction module 12, a size information set acquisition module 13, a side etching amount acquisition module 14, a fitness calculation module 15, a micro-step calculation module 16 and a process optimization result setting module 17.
Detailed Description
The application provides an etching process optimization method and system for chips, which are used for solving the technical problems of poor etching quality and low process optimization efficiency in the prior art when chips are manufactured by wet etching.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
It should be noted that the terms "comprises" and "comprising," along with any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
As shown in fig. 1, the present application provides a method for optimizing an etching process of a chip, where the method includes:
s100: according to design information of a target chip to be subjected to wet etching, etching conditions for optimizing etching process parameters of the target chip are obtained;
further, step S100 in the embodiment of the present application further includes:
obtaining design information of a target chip to be subjected to wet etching, wherein the design information comprises depth information and width information of an etched channel;
obtaining an error range of a target chip, compensating the depth information and the width information, and obtaining a depth information interval and a width information interval;
and the depth and the width of the channel etched by the target chip fall into the depth information interval and the width information interval to serve as etching conditions.
In one possible embodiment, the target chip is any chip that is ready for wet etching. According to the design information of the target chip to be subjected to wet etching, etching conditions which need to be met in the process of optimizing etching process parameters of the target chip when the wet etching is performed are determined. By determining the etching conditions, the optimization of the etching process of the target chip is constrained, and the technical effects of improving the accuracy of the optimization of the etching process and improving the optimization efficiency are achieved.
In one embodiment, the design information is obtained by retrieving order information of the target chip with the depth and the width of the etched channel of the target chip as indexes, wherein the design information comprises the depth information and the width information of the etched channel. The design information reflects the depth and width requirements that the target chip needs to reach after etching according to the design requirements. And determining the quality grade of the target chip based on the order information of the target chip, matching an allowable error range according to the quality grade of the target chip by a person skilled in the art, and compensating the depth information and the width information of the etched channel in the design information, thereby obtaining the depth information interval and the width information interval. The depth information interval is a depth range allowed by the target chip after the etching process is completed. The width information interval is the allowable width range of the target chip after the etching process is completed. And then, the depth and the width of the channel etched by the target chip fall into the depth information interval and the width information interval to serve as etching conditions.
S200: according to the wet etching process parameter adjustment range of the target chip, constructing a wet etching process parameter adjustment domain, and constructing an etching optimization function based on the purpose that the etched chip size approaches design information;
further, step S200 in the embodiment of the present application further includes:
obtaining an etching liquid proportioning range and an etching time range of wet etching process parameters;
combining the etching liquid proportioning range and the etching time range to obtain a process parameter adjustment domain;
based on the purpose that the etched chip size approaches to design information, an etching optimization function is constructed:；
wherein,for the etching fitness +.>And->Is weight(s)>For the etch depth compliance of the etch depth information after etching, T is the number of positions for testing the amount of side etching of the trench after etching, +.>And the side etching amount compliance is the side etching amount of the i-th position in the etched channel.
In one possible embodiment, the adjustable range for optimizing the etching process parameters, that is, the wet etching process parameter adjusting range, is determined according to the wet etching process parameter adjusting range of the target chip. Furthermore, the etching optimization function is constructed with the aim of approaching design information based on the etched chip size. The etching optimization function is used for quantitatively calculating the approaching degree of the etched chip size and the design information according to the technological parameters in the etching process optimization process of the target chip. The technical effect of improving the optimization efficiency of the etching process is achieved.
In one embodiment, the etching solution proportion range and the etching time range are obtained by searching the wet etching process parameters of the target chip by taking the etching solution proportion and the etching time as indexes. Exemplary etching times range from 4 to 6 minutes, or from 4 to 8 minutes, etc. And randomly combining the etching liquid proportioning range and the etching time range to obtain the process parameter adjusting domain. The process parameter adjustment domain is a parameter range which can be selected when the etching process parameter of the target chip is optimized. The etching fitness in the etching optimization function reflects the proximity degree of the chip size after etching according to the technological parameters and the design information of the target chip. The greater the fitness, the more fitting the chip size obtained after etching according to the corresponding wet etching process parameters with the design information of the target chip is. The etch depth compliance reflects how well the etch depth in the etched chip channel meets the requirements. The side etching amount compliance reflects the degree that the side etching amount of any position in the etched chip channel meets the requirement.
S300: randomly generating a plurality of guide solutions in the wet etching process parameter adjustment domain, respectively generating a plurality of subordinate solutions in the range of the guide step length of the guide solutions, respectively performing simulated wet etching on the target chip, and acquiring a plurality of size information sets after the simulated etching;
in one embodiment, each solution in the wet etching process parameter adjustment domain includes an etching solution ratio and an etching time. And randomly selecting the guide solutions in the wet etching process parameter adjustment domain, so as to obtain a plurality of guide solutions. The guide solution is used for guiding in the process of optimizing and searching the solution in the etching process of the target chip. The guiding step length is the amplitude of parameter adjustment for the wet etching process parameters in the guiding solution, and preferably, the guiding step length specifically comprises the adjustment step length of the etching liquid ratio and the adjustment step length of the etching time. Further, a plurality of slave solutions are randomly generated within a range of the pilot step sizes of the plurality of pilot solutions, respectively. That is, the etching liquid proportioning ranges and the etching times of the plurality of subordinate solutions are within the etching liquid proportioning ranges and the etching time ranges of the plurality of guide solutions.
And then, carrying out an analog wet etching experiment of the target chip in a laboratory according to the etching liquid proportioning range and the etching time in the plurality of guide solutions and the plurality of subordinate solutions, carrying out amplified scanning and measurement on a channel on the surface of the chip by utilizing an OLS4000 type laser confocal 3D microscope after etching, and obtaining a plurality of size information sets according to measurement results. The plurality of size information sets are used for describing the shape of the channel after wet etching according to a plurality of guide solutions and a plurality of subordinate solutions. The technical effect of providing basic analysis data for subsequent modeling analysis is achieved.
S400: constructing a plurality of chip channel modeling information for simulating etching according to the plurality of size information sets, wherein the plurality of chip channel modeling information comprises a plurality of etching depth information, and a plurality of side etching amount information sets are obtained in a dividing manner in the depth direction;
further, as shown in fig. 2, step S400 in the embodiment of the present application further includes:
constructing modeling information of a plurality of chip channels for simulating etching according to the plurality of size information sets, and modeling to obtain a plurality of channel models for simulating etching;
acquiring a plurality of etching depth information in a plurality of simulation etching channel models;
and in the depth direction, carrying out level division on the multiple simulated etching channel models to obtain M etching layers, and obtaining the side etching quantity in the M layers to obtain multiple side etching quantity information sets.
In one embodiment, a plurality of chip channel modeling information for simulating etching is constructed from dimensions in the plurality of sets of dimensional information. Preferably, the modeling information of the plurality of chip channels comprises a plurality of etching depth information, and a plurality of side etching amount information sets are obtained in a dividing manner in the depth direction. Wherein the etch depth information is used to describe the height of the chip channel relative to the chip surface. In the etching process, as the processing time increases, the reaction products increase, and attachments on the side wall of the chip channel increase, so that the side etching amount of the side wall is different along with the depth direction, and a plurality of side etching amount information sets corresponding to the depth direction are acquired according to each etching depth information.
Preferably, a plurality of simulated etch channel models are constructed using 3DSMAX modeling software using the plurality of sets of dimensional information. The plurality of simulated etching channel models are in one-to-one correspondence with the plurality of size information sets, and reflect channel shapes of the corresponding size information sets. Further, a plurality of etching depth information is obtained within the plurality of simulated etching channel models. And in the depth direction, carrying out level division on the plurality of simulation etching channel models according to the distribution conditions of the side etching quantities with different sizes, and taking the side wall of the chip channel with the same side etching quantity as one etching layer, thereby respectively obtaining M etching layers. Wherein M is an integer of 1 or more. And acquiring the side etching amounts in the M etching layers respectively according to the plurality of simulated etching channel models to obtain a plurality of side etching amount information sets. And the plurality of side etching amount information sets are in one-to-one correspondence with the plurality of simulated etching channel models.
S500: according to the etching depth information and the side etching amount information sets, combining design information, analyzing and calculating to obtain etching depth compliance information and side etching amount compliance information, and calculating to obtain guide fitness and subordinate fitness based on the etching optimization function;
further, as shown in fig. 3, step S500 in the embodiment of the present application further includes:
training an etching compliance identifier, wherein the etching compliance identifier comprises a depth compliance identification channel and a plurality of side etching compliance identification channels;
identifying a plurality of etching depth information and a plurality of side etching amount information sets by adopting the etching compliance identifier to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information;
based on the etching optimization function, a plurality of guiding fitness and a plurality of subordinate fitness are obtained through calculation.
Further, step S500 in the embodiment of the present application further includes:
acquiring a sample etching depth information set and a plurality of sample side etching amount information sets according to etching research and development data of a target chip;
based on depth information and width information of a channel in the design information of the target chip, evaluating and calculating the sample etching depth information set and the plurality of sample side etching amount information sets to obtain a sample etching depth compliance set and a plurality of sample side etching amount compliance sets;
constructing and training the depth compliance identification channel by adopting the sample etching depth information set and the sample etching depth compliance set;
respectively adopting the plurality of sample side etching amount information sets and the plurality of sample side etching amount compliance sets to construct and train a plurality of side etching compliance identification channels;
and combining the depth compliance recognition channel and the side corrosion compliance recognition channels to obtain the etching compliance recognizer.
In one possible embodiment, the compliance calculation is performed according to the etching depth information, the side etching quantity information sets and the design information, so as to obtain etching depth compliance and side etching quantity compliance information. And further, performing fitness calculation on the plurality of etching depth compliances and the plurality of side etching amount compliances by using an etching optimization function to obtain a plurality of guiding fitness and a plurality of subordinate fitness.
Preferably, the etching compliance identifier is a functional module for intelligently identifying the qualification degree of the etched chip size, and comprises a depth compliance identification channel and a plurality of side etching compliance identification channels. The depth compliance recognition channel is used for carrying out intelligent combination rule recognition on a plurality of etched depth information reflecting etched chip channels. The side etching amount compliance identification channels are functional channels for intelligent combination rule identification of the side etching amount information sets.
Preferably, the etching research and development data of the target chip are searched by taking the etching depth and the side etching amount as indexes, so that a sample etching depth information set and a plurality of sample side etching amount information sets are obtained. And further, based on the depth information and the width information of the channel in the design information of the target chip, evaluating and calculating the sample etching depth information set and the plurality of sample side etching amount information sets, and optionally, taking the ratio of the sample etching depth in the sample etching depth set to the depth information of the channel in the design information of the target chip as the sample etching depth compliance. Optionally, the plurality of sample width sets are calculated by collecting a plurality of sample mask width sets of the target chip in combination with the plurality of sample side etch amount information sets. The width calculation formula is: width = mask width-2 undercut amount. Further, ratios of the plurality of sample width sets to the width information of the channel in the target chip design information are calculated, respectively, and the calculated results are used as a plurality of sample side etching amount compliance sets.
In one embodiment, the depth compliance identification channel is obtained by performing supervised training on the convolutional neural network by using the sample etch depth information set and the sample etch depth compliance set until the output reaches convergence. And respectively adopting a plurality of sample side etching amount information sets and a plurality of sample side etching amount qualification degrees to supervise and train the convolutional neural network until the output reaches convergence, thereby obtaining a plurality of side etching compliance identification channels. And combining the depth compliance recognition channel and the side corrosion compliance recognition channels to obtain the etching compliance recognizer. The technical effect of efficiently and accurately identifying a plurality of etching depth information and a plurality of side etching amount information sets is achieved.
S600: according to the guiding fitness, calculating and obtaining a plurality of microsteps for updating a plurality of subordinate solutions;
further, step S600 in the embodiment of the present application further includes:
according to the plurality of guiding fitness, calculating and acquiring guiding fitness average values;
and respectively calculating and adjusting the preset microsteps according to the reciprocal of the ratio of each guiding fitness to the guiding fitness mean value, so as to obtain a plurality of microsteps after adjustment.
In one embodiment, a plurality of microsteps updating a plurality of slave solutions is determined by based on the plurality of boot fitness. The multiple microsteps are the amplitude of parameter adjustment for wet etching process parameters in multiple subordinate solutions, and specifically include adjustment step of etching solution ratio and adjustment step of etching time.
In one possible embodiment, a mean value of the plurality of boot fitness values is calculated, and a boot fitness mean value is obtained. The guiding fitness average value reflects average proximity degree of chip size and target chip design information after wet etching process is carried out according to a plurality of guiding solutions. And further, calculating the reciprocal of the ratio of each guiding fitness to the guiding fitness mean value, and respectively calculating and adjusting the preset microsteps according to the calculation result, so as to obtain a plurality of microsteps after adjustment. The preset microstep is a preset amplitude for parameter adjustment of the slave solution by a person skilled in the art. The technical effect of optimizing near the solution with high adaptability and improving optimizing quality is achieved.
S700: and updating the plurality of guide solutions and the plurality of slave solutions by adopting a plurality of guide step sizes and a plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as an etching process optimization result.
In the embodiment of the present application, updating a plurality of guide solutions and a plurality of slave solutions according to the plurality of guide steps and the plurality of micro steps, and continuing iterative optimization after updating until a preset optimizing frequency is reached, where the preset optimizing frequency is a optimizing frequency set by a person skilled in the art. And when the preset optimizing times are reached, taking the etching process parameter corresponding to the solution with the maximum adaptability as the optimal etching process parameter. And then taking the optimal etching process parameters as an etching process optimization result. The technical effect of efficiently and accurately optimizing the etching process of the chip and improving the etching quality of the chip is achieved.
In summary, the embodiments of the present application have at least the following technical effects:
according to the method, the etching conditions required to be met in the optimization process are obtained according to design information of target information to be subjected to wet etching, the aim of restricting the etching process optimization process is achieved, then a process parameter optimization range is constructed, a wet etching process parameter adjustment domain is generated, an etching optimization function is constructed, the parameter in the process optimization process is subjected to fitness quantitative calculation, further, a plurality of guide solutions are randomly generated in the wet etching process parameter adjustment domain, a plurality of dependent solutions are obtained based on the plurality of guide solutions, the wet etching is simulated, basic analysis data for follow-up compliance analysis are obtained, then the calculation result is analyzed according to the obtained plurality of etching depth information and the plurality of side etching amount information sets and by combining with the design information, a plurality of guide fitness and a plurality of dependent fitness are obtained by utilizing the etching optimization function, further, a plurality of micro-step sizes updated according to the plurality of guide fitness are obtained, and after a plurality of iteration optimization times are achieved, the optimal etching process parameter is obtained as an etching process optimization result. The technical effects of improving the etching process optimization efficiency of the chip and improving the etching quality are achieved.
Example two
Based on the same inventive concept as the etching process optimization method of a chip in the foregoing embodiments, as shown in fig. 4, the present application provides an etching process optimization system of a chip, and the system and method embodiments in the embodiments of the present application are based on the same inventive concept. Wherein the system comprises:
the etching condition acquisition module 11 is used for acquiring etching conditions for optimizing etching process parameters of the target chip according to design information of the target chip to be subjected to wet etching;
the optimization function construction module 12 is configured to construct a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip, and construct an etching optimization function based on the purpose that the etched chip size approaches the design information;
the dimension information set obtaining module 13 is configured to randomly generate a plurality of guide solutions in the wet etching process parameter adjustment domain, generate a plurality of slave solutions in the range of guide step sizes of the plurality of guide solutions, respectively perform simulated wet etching on the target chip, and obtain a plurality of dimension information sets after the simulated etching;
the side etching amount obtaining module 14 is configured to construct a plurality of chip channel modeling information for simulating etching according to a plurality of size information sets, wherein the plurality of chip channel modeling information includes a plurality of etching depth information, and in a depth direction, the plurality of chip channel modeling information sets are obtained by dividing;
the fitness calculation module 15 is configured to obtain, according to a plurality of etching depth information and a plurality of side etching amount information sets, by combining design information, a plurality of etching depth compliance information and a plurality of side etching amount compliance information by analysis and calculation, and obtain, based on the etching optimization function, a plurality of guiding fitness and a plurality of subordinate fitness by calculation;
a micro-step calculation module 16, configured to calculate and obtain a plurality of micro-steps for updating a plurality of slave solutions according to the plurality of guide fitness;
the process optimization result setting module 17 is configured to update the plurality of guide solutions and the plurality of slave solutions by using the plurality of guide steps and the plurality of micro steps, and perform iterative optimization until reaching a preset optimization frequency, obtain an optimal etching process parameter, and use the optimal etching process parameter as an etching process optimization result.
Further, the etching condition obtaining module 11 is configured to execute the following steps:
obtaining design information of a target chip to be subjected to wet etching, wherein the design information comprises depth information and width information of an etched channel;
obtaining an error range of a target chip, compensating the depth information and the width information, and obtaining a depth information interval and a width information interval;
and the depth and the width of the channel etched by the target chip fall into the depth information interval and the width information interval to serve as etching conditions.
Further, the optimization function construction module 12 is configured to perform the following steps:
obtaining an etching liquid proportioning range and an etching time range of wet etching process parameters;
combining the etching liquid proportioning range and the etching time range to obtain a process parameter adjustment domain;
based on the purpose that the etched chip size approaches to design information, an etching optimization function is constructed:；
wherein,for the etching fitness +.>And->Is weight(s)>For the etch depth compliance of the etch depth information after etching, T is the number of positions for testing the amount of side etching of the trench after etching, +.>And the side etching amount compliance is the side etching amount of the i-th position in the etched channel.
Further, the undercut-obtaining module 14 is configured to perform the following steps:
constructing modeling information of a plurality of chip channels for simulating etching according to the plurality of size information sets, and modeling to obtain a plurality of channel models for simulating etching;
acquiring a plurality of etching depth information in a plurality of simulation etching channel models;
and in the depth direction, carrying out level division on the multiple simulated etching channel models to obtain M etching layers, and obtaining the side etching quantity in the M layers to obtain multiple side etching quantity information sets.
Further, the fitness calculating module 15 is configured to perform the following steps:
training an etching compliance identifier, wherein the etching compliance identifier comprises a depth compliance identification channel and a plurality of side etching compliance identification channels;
identifying a plurality of etching depth information and a plurality of side etching amount information sets by adopting the etching compliance identifier to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information;
based on the etching optimization function, a plurality of guiding fitness and a plurality of subordinate fitness are obtained through calculation.
Further, the fitness calculating module 15 is configured to perform the following steps:
acquiring a sample etching depth information set and a plurality of sample side etching amount information sets according to etching research and development data of a target chip;
based on depth information and width information of a channel in the design information of the target chip, evaluating and calculating the sample etching depth information set and the plurality of sample side etching amount information sets to obtain a sample etching depth compliance set and a plurality of sample side etching amount compliance sets;
constructing and training the depth compliance identification channel by adopting the sample etching depth information set and the sample etching depth compliance set;
respectively adopting the plurality of sample side etching amount information sets and the plurality of sample side etching amount compliance sets to construct and train a plurality of side etching compliance identification channels;
and combining the depth compliance recognition channel and the side corrosion compliance recognition channels to obtain the etching compliance recognizer.
Further, the micro-step calculation module 16 is configured to perform the following steps:
according to the plurality of guiding fitness, calculating and acquiring guiding fitness average values;
and respectively calculating and adjusting the preset microsteps according to the reciprocal of the ratio of each guiding fitness to the guiding fitness mean value, so as to obtain a plurality of microsteps after adjustment.
It should be noted that the sequence of the embodiments of the present application is merely for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
The foregoing description of the preferred embodiments of the present application is not intended to limit the invention to the particular embodiments of the present application, but to limit the scope of the invention to the particular embodiments of the present application.
The specification and drawings are merely exemplary of the application and are to be regarded as covering any and all modifications, variations, combinations, or equivalents that are within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the present application and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (8)
1. The method for optimizing the etching process of the chip is characterized by comprising the following steps of:
according to design information of a target chip to be subjected to wet etching, etching conditions for optimizing etching process parameters of the target chip are obtained;
according to the wet etching process parameter adjustment range of the target chip, constructing a wet etching process parameter adjustment domain, and constructing an etching optimization function based on the purpose that the etched chip size approaches design information;
randomly generating a plurality of guide solutions in the wet etching process parameter adjustment domain, respectively generating a plurality of subordinate solutions in the range of the guide step length of the guide solutions, respectively performing simulated wet etching on the target chip, and acquiring a plurality of size information sets after the simulated etching;
constructing a plurality of chip channel modeling information for simulating etching according to the plurality of size information sets, wherein the plurality of chip channel modeling information comprises a plurality of etching depth information, and a plurality of side etching amount information sets are obtained in a dividing manner in the depth direction;
according to the etching depth information and the side etching amount information sets, combining design information, analyzing and calculating to obtain etching depth compliance information and side etching amount compliance information, and calculating to obtain guide fitness and subordinate fitness based on the etching optimization function;
according to the guiding fitness, calculating and obtaining a plurality of microsteps for updating a plurality of subordinate solutions;
and updating the plurality of guide solutions and the plurality of slave solutions by adopting a plurality of guide step sizes and a plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as an etching process optimization result.
2. The method according to claim 1, characterized in that the method comprises:
obtaining design information of a target chip to be subjected to wet etching, wherein the design information comprises depth information and width information of an etched channel;
obtaining an error range of a target chip, compensating the depth information and the width information, and obtaining a depth information interval and a width information interval;
and the depth and the width of the channel etched by the target chip fall into the depth information interval and the width information interval to serve as etching conditions.
3. The method according to claim 1, characterized in that the method comprises:
obtaining an etching liquid proportioning range and an etching time range of wet etching process parameters;
combining the etching liquid proportioning range and the etching time range to obtain a process parameter adjustment domain;
based on the purpose that the etched chip size approaches to design information, an etching optimization function is constructed:
；
wherein,for the etching fitness +.>And->Is weight(s)>For the etch depth compliance of the etch depth information after etching, T is the number of positions for testing the amount of side etching of the trench after etching, +.>And the side etching amount compliance is the side etching amount of the i-th position in the etched channel.
4. A method according to claim 3, characterized in that the method comprises:
constructing modeling information of a plurality of chip channels for simulating etching according to the plurality of size information sets, and modeling to obtain a plurality of channel models for simulating etching;
acquiring a plurality of etching depth information in a plurality of simulation etching channel models;
and in the depth direction, carrying out level division on the multiple simulated etching channel models to obtain M etching layers, and obtaining the side etching quantity in the M layers to obtain multiple side etching quantity information sets.
5. The method according to claim 1, characterized in that the method comprises:
training an etching compliance identifier, wherein the etching compliance identifier comprises a depth compliance identification channel and a plurality of side etching compliance identification channels;
identifying a plurality of etching depth information and a plurality of side etching amount information sets by adopting the etching compliance identifier to obtain a plurality of etching depth compliance information and a plurality of side etching amount compliance information;
based on the etching optimization function, a plurality of guiding fitness and a plurality of subordinate fitness are obtained through calculation.
6. The method according to claim 5, characterized in that the method comprises:
acquiring a sample etching depth information set and a plurality of sample side etching amount information sets according to etching research and development data of a target chip;
based on depth information and width information of a channel in the design information of the target chip, evaluating and calculating the sample etching depth information set and the plurality of sample side etching amount information sets to obtain a sample etching depth compliance set and a plurality of sample side etching amount compliance sets;
constructing and training the depth compliance identification channel by adopting the sample etching depth information set and the sample etching depth compliance set;
respectively adopting the plurality of sample side etching amount information sets and the plurality of sample side etching amount compliance sets to construct and train a plurality of side etching compliance identification channels;
and combining the depth compliance recognition channel and the side corrosion compliance recognition channels to obtain the etching compliance recognizer.
7. The method according to claim 1, characterized in that the method comprises:
according to the plurality of guiding fitness, calculating and acquiring guiding fitness average values;
and respectively calculating and adjusting the preset microsteps according to the reciprocal of the ratio of each guiding fitness to the guiding fitness mean value, so as to obtain a plurality of microsteps after adjustment.
8. An etching process optimization system for a chip, the system comprising:
the etching condition acquisition module is used for acquiring etching conditions for optimizing etching process parameters of the target chip according to the design information of the target chip to be subjected to wet etching;
the optimization function construction module is used for constructing a wet etching process parameter adjustment domain according to the wet etching process parameter adjustment range of the target chip and constructing an etching optimization function based on the purpose that the etched chip size approaches to design information;
the dimension information set acquisition module is used for randomly generating a plurality of guide solutions in the wet etching process parameter adjustment domain, generating a plurality of slave solutions in the range of the guide step length of the guide solutions respectively, respectively performing simulated wet etching on the target chip, and acquiring a plurality of dimension information sets after the simulated etching;
the side etching quantity acquisition module is used for constructing a plurality of chip channel modeling information for simulating etching according to a plurality of size information sets, wherein the plurality of chip channel modeling information comprises a plurality of etching depth information, and the plurality of chip channel modeling information sets are divided and acquired in the depth direction;
the fitness calculation module is used for obtaining a plurality of pieces of etching depth compliance information and a plurality of pieces of side etching fitness information through analysis and calculation according to a plurality of pieces of etching depth information and a plurality of pieces of side etching fitness information sets and combining design information, and obtaining a plurality of pieces of guiding fitness and a plurality of pieces of subordinate fitness through calculation based on the etching optimization function;
the micro-step calculation module is used for calculating and acquiring a plurality of micro-steps for updating a plurality of slave solutions according to the plurality of guide fitness;
the process optimization result setting module is used for updating the plurality of guide solutions and the plurality of slave solutions by adopting the plurality of guide step sizes and the plurality of micro step sizes, and performing iterative optimization until the preset optimization times are reached, so as to obtain optimal etching process parameters as etching process optimization results.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369638A (en) * | 2017-07-12 | 2017-11-21 | 上海华力微电子有限公司 | Etch managing and control system and its management-control method and etching machine bench |
| CN109165400A (en) * | 2018-07-06 | 2019-01-08 | 东南大学 | A kind of design method of focused-ion-beam lithography working process parameter |
| CN112685993A (en) * | 2021-03-17 | 2021-04-20 | 武汉大学 | Simulation method for wet chemical etching process of flexible PCB |
| CN112966467A (en) * | 2021-03-17 | 2021-06-15 | 武汉大学 | Flexible PCB structure design method based on wet chemical etching combined simulation |
| CN115935779A (en) * | 2022-08-01 | 2023-04-07 | 先进半导体材料(安徽)有限公司 | Method for constructing etching simulation model |
| CN116467994A (en) * | 2022-08-01 | 2023-07-21 | 先进半导体材料(安徽)有限公司 | Construction method of three-dimensional simulation etching model |
-
2023
- 2023-11-23 CN CN202311567969.2A patent/CN117276145B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369638A (en) * | 2017-07-12 | 2017-11-21 | 上海华力微电子有限公司 | Etch managing and control system and its management-control method and etching machine bench |
| CN109165400A (en) * | 2018-07-06 | 2019-01-08 | 东南大学 | A kind of design method of focused-ion-beam lithography working process parameter |
| CN112685993A (en) * | 2021-03-17 | 2021-04-20 | 武汉大学 | Simulation method for wet chemical etching process of flexible PCB |
| CN112966467A (en) * | 2021-03-17 | 2021-06-15 | 武汉大学 | Flexible PCB structure design method based on wet chemical etching combined simulation |
| CN115935779A (en) * | 2022-08-01 | 2023-04-07 | 先进半导体材料(安徽)有限公司 | Method for constructing etching simulation model |
| CN116467994A (en) * | 2022-08-01 | 2023-07-21 | 先进半导体材料(安徽)有限公司 | Construction method of three-dimensional simulation etching model |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118588605A (en) * | 2024-08-05 | 2024-09-03 | 江苏永鼎股份有限公司 | Chip etching process optimization method and system |
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