CN117275555A

CN117275555A - EEPROM circuit

Info

Publication number: CN117275555A
Application number: CN202311093791.2A
Authority: CN
Inventors: 杨光军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2023-12-22

Abstract

The invention discloses an EEPROM circuit, which comprises a memory unit, wherein an array unit is formed by a plurality of memory units, and an array structure is formed by a plurality of array units. The memory cell is a split gate floating gate device. The array structure is provided with a selection tube, a main word line, a selection signal line and a body electrode line. The source electrode of the selection tube is connected with the corresponding local word line, the drain electrode is connected with the corresponding main word line of the same row, the grid electrode is connected with the corresponding selection signal line of the same column, and the body electrode is connected with the corresponding body electrode line of the same column. When erasing a selected cell: selecting signals are added to the columns of the selected units corresponding to the selecting signal lines, and 0V voltage is added to each selecting signal line with different columns; adding positive erasing voltage to the main word line corresponding to the row of the selected unit; the columns of the selected cells are supplied with a positive bias voltage, less than the positive erase voltage, corresponding to the body electrode lines, and the different body electrode lines of the columns are supplied with a 0V voltage. A positive bias voltage is applied to the main word line that is different from the row of selected cells. The invention can increase the voltage of the local word line of the selected cell and thereby increase the erase effect.

Description

EEPROM circuit

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an EEPROM circuit.

Background

As shown in fig. 1, a schematic circuit structure of a memory cell 101 of a conventional EEPROM is shown; as shown in fig. 2, a schematic cross-sectional structure of a memory cell 101 of a conventional EEPROM is shown; as shown in fig. 3, an array structure diagram of the conventional EEPROM; the conventional EEPROM comprises a plurality of memory cells 101, wherein an array unit is formed by the plurality of memory cells 101, and an array structure of the EEPROM is formed by arranging the plurality of array units.

Each of the memory cells 101 employs a split gate floating gate device.

As shown in fig. 2, the split gate floating gate device includes: a source region 205 and a drain region 206, a plurality of separate first gate structures having floating gates 104 located between said source region 205 and said drain region 206, a second gate structure 103 located between said first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The split gate floating gate device is a dual split gate floating gate device, and the number of first gate structures is two, indicated by reference numerals 102a and 102b, respectively.

The split gate floating gate device is an N-type device, and the source region 205 and the drain region 206 are both composed of n+ regions.

A P-doped channel region is located between the source region 205 and the drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The source region 205 and the drain region 206 are both formed on the P-type semiconductor substrate 201 and self-aligned with the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the source region 205 and the drain region 206 or further formed by doping on the P-type semiconductor substrate 201.

The drain region 206 of the memory cell 101 is connected to drain D.

The source region 205 of the memory cell 101 is connected to a source S.

Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.

Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.

The control gate 105 is connected to a control gate line CG and the word line gate 106 is connected to a word line WL.

When the memory cell 101 is erased (Erase):

the control gate line CG is connected to a negative erase voltage.

The word line WL is connected to a positive erase voltage.

The drain electrode D and the source electrode S are both connected with 0V.

The voltage difference between the negative erase voltage and the positive erase voltage causes stored charge in each floating gate 104 to be erased.

The specific parameters of the existing memory when operating the memory unit 101 are given in table one:

list one

Operation of	CG(V)	WL(V)	S(V)	D
					Erasing	-7	8	0	0

In Table one, the negative erase voltage is equal to-7V and the positive erase voltage is equal to 8V.

In the array unit: each of the memory cells 101 is arranged in a row, and the second gate structure 103 of each of the memory cells 101 is connected to a corresponding Local Word Line (LWL); the local word lines of each of the array cells are independently disposed. In fig. 3, 4 of the local word lines are shown, denoted LWL00, LWL10, LWL01 and LWL11, respectively.

Typically, the number of memory cells 101 in the array unit includes 8, i.e., one byte (byte).

The array structure comprises: the array units are arranged to form rows and columns, the array units in the same row are arranged to form array unit rows, and the array units in the same column are arranged to form array unit columns.

The array structure is provided with a selection tube, a Main Word Line (MWL) and a selection signal line (CSL). In fig. 3, 4 of said selection tubes are shown, denoted by the reference numerals 302a, 302b, 302c and 302d, respectively; two of the main word lines are shown, denoted by the labels MWL0 and MWL1, respectively; two of the selection signal lines are shown, denoted by the marks CSL0 and CSL1, respectively.

The main word line is a row line, the number of rows of the main word line is the same as the number of rows of the array unit line, and each row of the main word line is shared by each array unit in the array unit line of the same row, for example: the main word line MWL0 is common to the array cells 301a and 301c of the first row, and the main word line MWL1 is common to the array cells 301b and 301d of the second row.

The selection signal lines are column lines, the column numbers of the selection signal lines are the same as the column numbers of the array unit columns, and the selection signal lines of all columns are shared by all array units in the array unit columns of the same column. For example: the selection signal line CSL0 is common to the array cells 301a and 301b of the first column, and the selection signal line CSL1 is common to the array cells 301c and 301d of the second column.

The number of the selection tubes is the same as that of the array units, and each array unit corresponds to one selection tube. For example: the selection tube 302a corresponds to the array unit 301a, the selection tube 302b corresponds to the array unit 301b, the selection tube 302c corresponds to the array unit 301c, and the selection tube 302d corresponds to the array unit 301 d.

The local word lines of each array unit are respectively connected to the corresponding main word lines through the corresponding selection tubes; each selection tube is an NMOS tube, a first channel region of the selection tube consists of a first P-type body region, and the first P-type body region is connected with a body electrode. The source of each of the select transistors is connected to the local word line of the corresponding array cell.

The main word lines are row lines, and the selection signal lines and the body electrode lines are column lines.

The drain electrodes of the selection transistors of the same row are connected to the main word lines corresponding to the same row.

The gates of the selection transistors of the same column are connected to the selection signal lines corresponding to the same column.

And making the selected array units be selected units, and making the unselected array units be unselected units.

The selected cell is erased with the following voltage settings:

adding a selection signal to the column of the selected unit corresponding to the selection signal line to conduct the selection tube corresponding to the selected unit; and applying a voltage of 0V to each of the selection signal lines different from the columns of the selected cells to turn off the selection transistors corresponding to the non-selected cells of the different columns of the selected cells.

Adding positive erasing voltage to the main word line corresponding to the row of the selected unit; the voltage of the select signal is greater than the positive erase voltage, for example: the voltage of the selection signal is 10V, and the positive erase voltage is 8V.

In fig. 3, the body electrode of each of the selection tubes is grounded.

Each of the main word lines, which is different from the row of the selected cell, is added with 0V.

In the array unit, the control gate of each memory cell 101 is connected to a corresponding control gate line. In the array structure, the array units of the same row share the control grid lines of the same row. Two of the control gate lines are shown in fig. 3, denoted CGL0 and CGL1, respectively. In the erasing process, the control grid line corresponding to the selected unit is connected with negative erasing voltage.

As shown in fig. 3, taking the array cell 301a as the selected cell as an example, the voltage applied during erasing is:

MWL0 adds the positive erase voltage, e.g. 8V.

Both MWL1 and CSL1 are added with 0V.

CSL0 is added to the select signal, e.g., 10V.

CSL0 turns on the select transistor of the first column, and the select transistor 302a turns on, but the source voltage of the select transistor 302a drops to 7.5V due to the grounded body electrode of the select transistor 302a, because there is a large voltage difference between the source and the body electrode, which corresponds to the reverse bias voltage of the diode formed by the n+ source region and the P-type body region, and the conduction performance of the select transistor 302a is affected due to the large reverse bias voltage, so that the source-drain voltage increases, and the source voltage drops. Therefore, the source voltage of the selection tube 302 cannot reach 8V of the drain, so LWL00 is only 7.5V, and cannot reach the set 8V, and thus the erase efficiency is reduced.

Since CSL1 is 0V, each of the select transistors of the second column is turned off, and the corresponding source is in a floating (floating) state, such as the sources of the select transistors 302c and 302d are in a floating state.

Since MWL1 is 0V, even if the select tube 302b of the second row of the first column is turned on, the source of the select tube 302b is 0V.

Disclosure of Invention

The invention aims to provide an EEPROM circuit which can carry out bias control on the body electrode of a selection tube and can eliminate the source voltage which is too low due to the too large voltage difference between the source electrode of the selection tube and the body electrode by carrying out bias control on the body electrode of the selection tube during erasure, thereby improving the voltage of the local word line of a selected unit and further improving the erasure effect.

Therefore, the EEPROM circuit provided by the invention comprises a plurality of storage units, wherein an array unit is formed by the plurality of storage units, and an array structure of the EEPROM is formed by arranging the plurality of array units.

Each of the memory cells employs a split gate floating gate device.

The split gate floating gate device includes: a source region and a drain region, a plurality of separated first gate structures having floating gates between the source region and the drain region, and a second gate structure between the first gate structures; the first grid structure is provided with a control grid positioned on the top of the floating gate.

In the array unit: each memory cell is arranged in a row, and the second grid structure of each memory cell is connected with a corresponding local word line; the local word lines of each of the array cells are independently disposed.

The array structure is provided with a selection tube, a main word line, a selection signal line and a body electrode line.

Each array unit corresponds to one selection tube, and the local word line of each array unit is connected to the corresponding main word line through the corresponding selection tube; each selection tube is an NMOS tube, a first channel region of the selection tube consists of a first P-type body region, and the first P-type body region is connected with a body electrode.

The source of each of the select transistors is connected to the local word line of the corresponding array cell.

The body electrodes of the selection tubes of the same column are connected to the corresponding body electrode lines of the same column.

The selected cell is erased with the following voltage settings:

Adding positive erasing voltage to the main word line corresponding to the row of the selected unit; the voltage of the selection signal is greater than the positive erase voltage.

And applying a positive bias voltage to the body electrode line corresponding to the column of the selected cell, wherein the positive bias voltage is smaller than the positive erase voltage, and applying a voltage of 0V to each body electrode line different from the column of the selected cell, and reducing the bias voltage between the first P-type body region and the first source region of N+ of the selection tube corresponding to the selected cell through the arrangement of the positive bias voltage, so that the voltage of the local word line corresponding to the selected cell is improved.

The positive bias voltage is applied to each of the main word lines different from the row of the selected cell.

In a further improvement, in the array unit, the control gate of each memory cell is connected to a corresponding control gate line.

A further improvement is that the positive bias voltage employs a supply voltage of the EEPROM.

A further improvement is that the voltage of the selection signal is provided by a corresponding charge pump; the positive erase voltage is provided by a corresponding charge pump.

Further improvement is that the positive erase voltage is above 8V.

Further improvement is that the voltage of the selection signal is more than 10V.

A further improvement is that the number of memory cells in the array unit comprises 8.

The separation gate floating gate device is a double separation gate floating gate device, and the number of the first gate structures is two.

In a further improvement, the split gate floating gate device is an N-type device, and the source region and the drain region are both composed of an N+ region.

A P-doped channel region is located between the source region and the drain region and is covered by each of the first gate structure and the second gate structure.

In a further improvement, during said erasing, both the source and drain regions of each of said memory cells are grounded.

In the array structure, the array units in the same row share the control grid lines in the same row.

In the erasing process, the control grid line corresponding to the selected unit is connected with negative erasing voltage.

The further improvement is that each first gate structure is formed by superposing a tunneling dielectric layer, the floating gate, a control gate dielectric layer and the control gate.

Each second grid structure is formed by overlapping a word grid medium layer and a word grid.

A further improvement is that the material of the floating gate comprises polysilicon, the material of the control gate comprises polysilicon, and the material of the word line gate comprises polysilicon.

In a further improvement, the material of the tunneling dielectric layer comprises an oxide layer, the material of the control gate dielectric layer comprises an oxide layer, and the material of the word line gate dielectric layer comprises an oxide layer.

In the prior art, the body electrode of the selection tube of the selected unit is directly grounded, the drain electrode of the selection tube is connected with higher positive erasing voltage, and the source electrode voltage is transmitted by the drain electrode voltage, so that the source electrode and the drain electrode voltage of the selection tube are both much larger than the voltage of the body electrode, and the body region of the selection tube is reversely biased to be larger, namely, the body region, the source region and the drain region are reversely biased to be larger, so that the source electrode voltage is increased, the source electrode voltage is greatly reduced relative to the drain electrode voltage, and the positive erasing voltage provided by the source electrode of the selection tube to the local word line is reduced, thereby influencing the erasing efficiency; in the invention, the row-arranged body electrode wires are added in the array structure, the body electrode of each row of selection tubes, namely the back gate electrode, is connected to the body electrode wires, the voltage of the body electrode wires is also specially set when the body electrode wires are erased, the voltage of the body electrode wires corresponding to the row where the selected unit is positioned is set to be positive bias voltage, the positive bias voltage is larger than 0V and smaller than the positive erase voltage provided by the main word line, and the voltage of the local word line of the selected unit needs to be transmitted from the positive erase voltage of the main word line through the selection tube, after the positive bias voltage is set, the pressure difference between the first source region and the first P-shaped body region of the selection tube can be reduced, so that the source electrode voltage of the selection tube is improved, and the positive erase voltage connected with the drain electrode of the selection tube can be well transmitted to the local word line, thereby improving the erase efficiency.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a schematic circuit diagram of a memory cell of a conventional EEPROM;

FIG. 2 is a schematic cross-sectional structure of a memory cell of a conventional EEPROM;

FIG. 3 is a diagram of an array structure of a conventional EEPROM;

fig. 4 is a diagram showing an array structure of an EEPROM according to an embodiment of the present invention.

Detailed Description

FIG. 4 is a diagram showing an array structure of an EEPROM according to an embodiment of the present invention; referring to fig. 2 and the structure of the memory cell 101 in the embodiment of the present invention, the EEPROM in the embodiment of the present invention includes a plurality of memory cells 101, an array unit is formed by a plurality of the memory cells 101, and an array structure of the EEPROM is formed by arranging a plurality of the array units. In fig. 4, 4 of said array elements are shown, marked with the marks 301a, 301b, 301c and 301d, respectively.

Each of the memory cells 101 employs a split gate floating gate device.

The drain region 206 of the memory cell 101 is connected to drain D.

The source region 205 of the memory cell 101 is connected to a source S.

When the memory cell 101 is erased (Erase):

the control gate line CG is connected to a negative erase voltage.

The word line WL is connected to a positive erase voltage.

The drain electrode D and the source electrode S are both connected with 0V.

In the array unit: each of the memory cells 101 is arranged in a row, and the second gate structure 103 of each of the memory cells 101 is connected to a corresponding local word line; the local word lines of each of the array cells are independently disposed. In fig. 4, 4 of the local word lines are shown, denoted LWL00, LWL10, LWL01 and LWL11, respectively.

In some embodiments, the number of memory cells 101 in the array unit includes 8, i.e., one byte.

The array structure is provided with a selection tube, a main word line, a selection signal line and a body electrode line. In fig. 4, 4 of said selection tubes are shown, denoted by the reference numerals 302a, 302b, 302c and 302d, respectively; two of the main word lines are shown, denoted by the labels MWL0 and MWL1, respectively; two of the selection signal lines are shown, denoted by the marks CSL0 and CSL1, respectively; two of said body electrode lines are shown, denoted by the labels PW0 and PW1, respectively.

The array unit comprises an array unit column, a plurality of array units and a plurality of body electrode lines, wherein the body electrode lines are column lines, the column number of the body electrode lines is the same as that of the array unit column, and the body electrode lines in each column are shared by the array units in the same array unit column. For example: the body electrode line PW0 is common to the array cells 301a and 301b of the first column, and the body electrode line PW1 is common to the array cells 301c and 301d of the second column.

The local word lines of each array unit are respectively connected to the corresponding main word lines through the corresponding selection tubes; each selection tube is an NMOS tube, a first channel region of the selection tube consists of a first P-type body region, and the first P-type body region is connected with a body electrode.

The selected cell is erased with the following voltage settings:

The column of the selected cell applies a positive bias voltage to the body electrode line, the positive bias voltage is smaller than the positive erase voltage, and each body electrode line different from the column of the selected cell applies a voltage of 0V, and the bias voltage between the first P-type body region and the first source region 205 of n+ of the selection tube corresponding to the selected cell is reduced by setting the positive bias voltage, so that the voltage of the local word line corresponding to the selected cell is increased.

In the embodiment of the present invention, in the array unit, the control gate of each memory cell 101 is connected to a corresponding control gate line. In the array structure, the array units of the same row share the control grid lines of the same row. Two of the control gate lines are shown in fig. 4, denoted CGL0 and CGL1, respectively. In the erasing process, the control grid line corresponding to the selected unit is connected with negative erasing voltage.

In the embodiment of the invention, the positive bias voltage adopts the power supply voltage (Vdd) of the EEPROM.

The voltage of the selection signal is provided by a corresponding charge pump; the positive erase voltage is provided by a corresponding charge pump.

The voltage of the selection signal reaches more than 10V. The positive erase voltage is above 8V.

Taking the array cell 301a as the selected cell as an example, the voltage applied during erase is:

MWL0 adds the positive erase voltage, e.g. 8V.

Both PW0 and MWL1 add the positive bias voltage, e.g., vdd.

CSL0 is added to the select signal, e.g., 10V.

CSL1 and PW1 are both plus 0V.

For the array unit 301a, the voltage between the source and the body electrode of the selection tube 302a is reduced when the p 0 is Vdd, so that the voltage difference between the source and the drain can be reduced after the selection tube 302a is completely turned on, and the source voltage can be approximately 8V and greater than 7.5V in the prior art of fig. 3, so that the erasing efficiency can be improved.

Meanwhile, after MWL1 is set to Vdd, the source voltage of the selection tube 302b is less than or equal to Vdd of the bulk electrode, so that the source-drain voltage difference of the selection tube 302b is small and is basically non-conductive.

In the prior art, the body electrode of the selection tube of the selected cell is directly grounded, the drain electrode of the selection tube is connected with higher positive erase voltage, and the source voltage is transmitted by the drain voltage, so that the source voltage and the drain voltage of the selection tube are both much greater than the voltages of the body electrode, and the body region of the selection tube is reversely biased to be larger, namely, the body region and the source region 205 and the body region and the drain region 206 are reversely biased, which increases the source drain voltage, so that the source voltage drops more relative to the drain voltage, and the positive erase voltage provided by the source electrode of the selection tube to the local word line is reduced, thereby influencing the erase efficiency; in the embodiment of the invention, the body electrode wires arranged in columns are added in the array structure, the body electrode of each column of selection tube, namely the back gate electrode, is connected to the body electrode wires, the voltage of the body electrode wires is also specially set when erasing, the voltage of the body electrode wires corresponding to the columns where the selected units are located is set to be positive bias voltage, the positive bias voltage is greater than 0V and smaller than the positive erase voltage provided by the main word line, and the voltage of the local word line of the selected unit needs to be transmitted from the positive erase voltage of the main word line through the selection tube, after the positive bias voltage is set, the voltage difference between the first source region 205 and the first P-shaped body region of the selection tube can be reduced, so that the source drain voltage of the selection tube is improved, and the positive erase voltage connected with the drain electrode of the selection tube can be well transmitted to the local word line, thereby improving the erase efficiency.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. An EEPROM circuit is characterized by comprising a plurality of storage units, wherein an array unit is formed by the storage units, and an array structure of the EEPROM is formed by arranging the array units;

each storage unit adopts a split gate floating gate device;

the split gate floating gate device includes: a source region and a drain region, a plurality of separated first gate structures having floating gates between the source region and the drain region, and a second gate structure between the first gate structures; the first grid structure is provided with a control grid positioned at the top of the floating gate;

in the array unit: each memory cell is arranged in a row, and the second grid structure of each memory cell is connected with a corresponding local word line; the local word lines of each array unit are independently arranged;

the array structure comprises: the array units are arranged to form rows and columns, the array units in the same row are arranged to form array unit rows, and the array units in the same column are arranged to form array unit columns;

the array structure is provided with a selection tube, a main word line, a selection signal line and a body electrode line;

each array unit corresponds to one selection tube, and the local word line of each array unit is connected to the corresponding main word line through the corresponding selection tube; each selection tube is an NMOS tube, a first channel region of each selection tube consists of a first P-type body region, and the first P-type body regions are connected with a body electrode;

the source electrode of each selection tube is connected to the local word line of the corresponding array unit;

the main word lines are row lines, and the selection signal lines and the body electrode lines are column lines;

the drain electrode of each selection tube of the same row is connected to the main word line corresponding to the same row;

the grid electrode of each selection tube of the same column is connected to the corresponding selection signal line of the same column;

the body electrode of each selection tube in the same column is connected to the corresponding body electrode wire in the same column;

making the selected array units be selected units, and making the unselected array units be unselected units;

the selected cell is erased with the following voltage settings:

adding a selection signal to the column of the selected unit corresponding to the selection signal line to conduct the selection tube corresponding to the selected unit; applying a voltage of 0V to each of the selection signal lines different from the columns of the selected cells to turn off the selection tube corresponding to each of the non-selected cells of the different columns of the selected cells;

adding positive erasing voltage to the main word line corresponding to the row of the selected unit; the voltage of the selection signal is greater than the positive erase voltage;

applying a positive bias voltage to the body electrode line corresponding to the column of the selected cell, wherein the positive bias voltage is smaller than the positive erase voltage, and applying a voltage of 0V to each body electrode line different from the column of the selected cell, and reducing bias voltage between the first P-type body region and the first source region of N+ of the selection tube corresponding to the selected cell through setting of the positive bias voltage, so that the voltage of the local word line corresponding to the selected cell is improved;

2. The EEPROM circuit of claim 1, wherein: in the array unit, the control gate of each memory cell is connected to a corresponding control gate line.

3. The EEPROM circuit of claim 1, wherein: the positive bias voltage employs a supply voltage of the EEPROM.

4. The EEPROM circuit of claim 3, wherein: the voltage of the selection signal is provided by a corresponding charge pump; the positive erase voltage is provided by a corresponding charge pump.

5. The EEPROM circuit of claim 4, wherein: the positive erase voltage is above 8V.

6. The EEPROM circuit of claim 5, wherein: the voltage of the selection signal reaches more than 10V.

7. The EEPROM circuit of claim 1, wherein: the number of the memory cells in the array unit includes 8.

8. The EEPROM circuit of claim 1, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.

9. The EEPROM circuit of claim 8, wherein: the separation gate floating gate device is an N-type device, and the source region and the drain region are both composed of an N+ region;

10. The EEPROM circuit of claim 2, wherein: during the erasing process, the source region and the drain region of each memory cell are grounded.

11. The EEPROM circuit of claim 10, wherein: in the array structure, the array units of the same row share the control grid lines of the same row.

12. The EEPROM circuit of claim 11, wherein: in the erasing process, the control grid line corresponding to the selected unit is connected with negative erasing voltage.

13. The EEPROM circuit of claim 7, wherein: each first gate structure is formed by superposing a tunneling dielectric layer, the floating gate, a control gate dielectric layer and the control gate;

14. The EEPROM circuit of claim 13, wherein: the material of the floating gate comprises polysilicon, the material of the control gate comprises polysilicon, and the material of the word line gate comprises polysilicon.

15. The EEPROM circuit of claim 13, wherein: the tunneling dielectric layer is made of a material comprising an oxide layer, the control gate dielectric layer is made of a material comprising an oxide layer, and the word line gate dielectric layer is made of a material comprising an oxide layer.