CN117271397A - General input/output circuit, general input/output circuit control method and chip - Google Patents

General input/output circuit, general input/output circuit control method and chip Download PDF

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Publication number
CN117271397A
CN117271397A CN202311272329.9A CN202311272329A CN117271397A CN 117271397 A CN117271397 A CN 117271397A CN 202311272329 A CN202311272329 A CN 202311272329A CN 117271397 A CN117271397 A CN 117271397A
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CN
China
Prior art keywords
input
selection unit
channel selection
module
output
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Pending
Application number
CN202311272329.9A
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Chinese (zh)
Inventor
张吉红
刘夏聪
孙万里
陈亮
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Zhuhai Geehy Semiconductor Co Ltd
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Zhuhai Geehy Semiconductor Co Ltd
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Priority to CN202311272329.9A priority Critical patent/CN117271397A/en
Publication of CN117271397A publication Critical patent/CN117271397A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a general input/output circuit, a control method of the general input/output circuit and a chip, wherein the general input/output circuit is used for connecting external equipment and an internal circuit of the chip, and comprises the following steps: the device comprises a channel selection unit, a first trigger, an input module and an output module; the first end of the channel selection unit is connected with the pin, the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is connected with the wake-up module in the chip internal circuit through the first trigger; the pin is used for being connected with external equipment, receiving an external interrupt signal sent by the external equipment when the internal circuit of the chip is in a stop mode, and transmitting the external interrupt signal to the first end of the channel selection unit; in the stop mode, a clock module in the internal circuit of the chip stops generating a clock signal; the first end of the channel selection unit is connected with the third end of the channel selection unit when the first end of the channel selection unit receives an external interrupt signal.

Description

General input/output circuit, general input/output circuit control method and chip
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a general input/output circuit, a control method for the general input/output circuit, and a chip.
Background
A micro controller chip is a kind of microcomputer chip, which is widely used in various applications such as control operation circuits, data acquisition processing, embedded systems, communication, and the like. Power consumption is a major consideration in chip design, and the higher the power consumption, the shorter the lifetime. Therefore, in the design of the micro-controller chip, the power consumption is reduced by powering off the chip or closing the clock, but the micro-controller chip can respond to the chip in real time for waking up due to the application requirement, so that the design of waking up the chip with low power consumption is very important.
The General-purpose input/output (GPIO) is a pin of a chip, and is connected with external equipment, so that the functions of communication, control and data acquisition between the chip and the outside are realized, but in the prior art, when the microcontroller chip is in a low-power consumption state, peripheral wakeup sources for waking up the microcontroller chip by receiving external signals input to external interrupts are fewer, and only certain special peripheral wakeup sources can be used, so that the chip in a low-power consumption mode cannot be woken up by using the General peripheral wakeup sources.
Therefore, due to the application requirement of the chip for real-time wake-up response, a design for waking up the chip by using a general peripheral wake-up source is needed.
Disclosure of Invention
The application provides a general input/output circuit, a control method of the general input/output circuit and a chip, which are used for solving the problem that a peripheral wake-up source cannot be used universally when a chip in a low power consumption mode is waken up.
In a first aspect, the present application provides a general purpose input output circuit, the general purpose input output circuit is used for connecting external equipment, the general purpose input output circuit is also used for connecting chip internal circuit, the general purpose input output circuit includes: the device comprises a channel selection unit, a first trigger, an input module and an output module;
the first end of the channel selection unit is connected with the pin, the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is connected with the wake-up module in the chip internal circuit through the first trigger;
the pin is used for being connected with external equipment, receiving an external interrupt signal sent by the external equipment when the internal circuit of the chip is in a stop mode, and transmitting the external interrupt signal to the first end of the channel selection unit; in the stop mode, a clock module in the internal circuit of the chip stops generating a clock signal;
the first end of the channel selection unit is connected with the third end of the channel selection unit when the first end of the channel selection unit receives an external interrupt signal.
In one embodiment, the pin is further configured to receive an external input signal sent by the external device when the internal circuit of the chip exits the stop mode;
when the first end of the channel selection unit receives an external input signal, the first end of the channel selection unit is communicated with the second end of the channel selection unit, so that the external input signal is transmitted to the input module and the output module.
In one embodiment, the first terminal of the channel selection unit and the second terminal of the channel selection unit are turned on when the second terminal of the channel selection unit receives the output signal, so that the output signal is transmitted to the pin.
In one embodiment, the channel selection unit includes a first selection register and a second selection register;
the first end of the first selection register is connected with the pin, and the second end of the first selection register is connected with the output module; the third end of the first selection register is suspended; when the first end of the first selection register receives an external interrupt signal, the pin is connected with the third end of the first selection register;
the first end of the second selection register is connected with the pin, the second end of the second selection register is connected with the input module, and the third end of the second selection register is connected with the wake-up module through the first trigger; when the first end of the second selection register receives the external interrupt signal, the pin is connected with the third end of the second selection register, so that the external interrupt signal is transmitted to the wake-up module.
In one embodiment, when the first end of the second selection register receives an external input signal, the first end of the second selection register is connected with the second end of the second selection register, so that the external input signal is transmitted to the input module;
when the second end of the first selection register receives the output signal, the second end of the first selection register is communicated with the first end of the first selection register, so that the output signal is transmitted to an external pin.
In one embodiment, the input module includes an input driver and an input data register;
the input end of the input driver is connected with the pin, and the output end of the input driver is connected with the input end of the input data register;
the input driver comprises an input mode circuit and a second trigger; the input end of the input mode circuit is connected with the pin, and the output end of the input mode circuit is connected with the first end of the second selection register;
the input end of the second trigger is connected with the second end of the second selection register, and the output end of the second trigger is used as the output end of the input driver.
In a second aspect, the present application further provides a control method of a general input output circuit, where the general input output circuit is used for connecting with an external device, and the general input output circuit is further used for connecting with an internal circuit of a chip, and the general input output circuit includes: the device comprises a channel selection unit, a first trigger, an input module and an output module; the first end of the channel selection unit is connected with a pin, and the pin is used for being connected with external equipment; the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is connected with the wake-up module in the chip internal circuit through the first trigger;
when detecting that an external interrupt signal sent by external equipment is received on a pin when an internal circuit of a chip is in a stop mode, generating a first control signal of a channel selection unit;
the first control signal is used for enabling the first end of the channel selection unit to be communicated with the third end of the channel selection unit, enabling the external interrupt signal to be transmitted to the wake-up module, enabling the external interrupt signal to be used for controlling the wake-up module to generate a wake-up signal, and enabling the wake-up signal to be used for controlling the clock module to generate a clock signal; in the stop mode, the clock module in the chip internal circuit stops generating the clock signal.
In one embodiment, the method further comprises:
when the internal circuit of the chip is in the exit stop mode, the external input signal sent by the external equipment is detected to be received by the pin, and a second control signal is generated;
the second control signal is used for enabling the first end of the channel selection unit to be communicated with the second end of the channel selection unit, and enabling the external input signal to be transmitted to the input module and the output module.
In one embodiment, the third control signal is generated when the second end of the channel selection unit receives the output signal when the internal circuit of the chip is in the exit stop mode;
the third control signal is used for enabling the first end of the channel selection unit to be communicated with the second end of the channel selection unit, and enabling the output signal to be transmitted to the pin.
In a third aspect, the present application further provides a chip, including a chip internal circuit and a pin, where the chip internal circuit and the pin are connected by the above-mentioned universal input/output circuit.
The application provides a general input output circuit, this general input output circuit is used for connecting external equipment, and general input output circuit still is used for connecting chip internal circuit, and this general input output circuit includes: the device comprises a channel selection unit, a first trigger, an input module and an output module; the first end of the channel selection unit is used for being connected with the pin, the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is used for being connected with the wake-up module in the internal circuit of the chip; the pin is used for being connected with external equipment, receiving an external interrupt signal sent by the external equipment when the internal circuit of the chip is in a stop mode, and transmitting the external interrupt signal to the first end of the channel selection unit; in the stop mode, a clock module in the internal circuit of the chip stops generating a clock signal; when the first end of the channel selection unit receives an external interrupt signal, the first end of the channel selection unit is communicated with the third end of the channel selection unit, so that the external interrupt signal is transmitted to the wake-up module. The clock module of the internal circuit of the chip stops generating clock signals in the stop mode, the pins of the general input/output circuit receive external interrupt signals, the channel selection unit is communicated with the pins, namely the first end and the third end, so that the external interrupt signals can be transmitted to the wake-up module, the clock module is further controlled to generate clock signals to wake up the chip, and the general input/output circuit provided by the application is applicable to various peripheral wake-up sources, so that the number of the wake-up sources for waking up the chip in the stop mode is greatly increased.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a general purpose input/output circuit in the prior art;
FIG. 2 is a schematic diagram of a general purpose input/output circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a general purpose input/output circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a general purpose input/output circuit according to another embodiment of the present application;
fig. 5 is a flowchart of a control method of a general purpose input/output circuit according to an embodiment of the present application.
Reference numerals:
general input output circuit: 100; external device: 300; chip internal circuit: 200; a channel selection unit: 120; an input module and an output module: 110; a first trigger: 130; an input module: 112; and an output module: 111; a first selection register: 121; a second selection register: 122, a step of; and (3) a wake-up module: 220.
specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It is to be understood that in the following description, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not necessarily for indicating or implying a relative importance or order.
MCU Micro Control Unit, called micro control unit, also called single chip microcomputer (Single Chip Microcomputer) or single chip microcomputer, refers to integrating CPU, RAM, ROM, timer counter and multiple I/O interfaces of computer on a chip to form chip-level computer for controlling common memory device for different application occasions.
GPIOs (General Purpose I/O Ports) mean general purpose input/output Ports, or more commonly pins, through which high or low levels can be output or through which the state of a pin is read-whether high or low.
CPU (Center Process Unit, central processing unit): the chip is used for processing instructions, data, controlling other peripheral equipment and the like, and is a core component of the chip.
USART (Universal Synchronous/Asynchronous Receiver/Transmitter, universal synchronous/asynchronous serial receiver/Transmitter) USART is a serial communication protocol that can be used for data transfer in both synchronous and asynchronous modes for transferring data from one device to another.
The I2C (Inter-Integrated Circuit Bus) bus is a simple, bi-directional two-wire synchronous serial bus. It requires only two wires to transfer information between devices connected to the bus.
SDA (serialdata) is also the data signal line of the I2C bus. CLK clock.
SPI is an abbreviation for serial peripheral interface (Serial Peripheral Interface), a high-speed, full duplex, synchronous communication bus.
EINT (external interrupt controller): managing external interrupts enables the generation of corresponding interrupt requests to the CPU/interrupt controller and wake-up requests to the power management.
As shown in fig. 1, fig. 1 is a schematic diagram of a general input/output circuit in the prior art. General-purpose input/output (GPIO) is a pin of a chip, and is connected to an external device, so that functions of communication, control and data acquisition between the chip and the outside are realized.
At present, when a microcontroller chip is in a stop mode (low power consumption), a clock is turned off, the chip is powered off to reduce power consumption, at the moment, peripheral wakeup sources capable of waking up the chip through an external signal are fewer, and when the chip is in the stop mode, the chip can only be waken up through a special peripheral wakeup source, so that the limitation is quite large.
In view of this, the present application provides a general purpose input output circuit 100, as shown in fig. 2, the general purpose input output circuit 100 being used for connecting to an external device 300, the general purpose input output circuit 100 also being used for connecting to an internal chip circuit 200, the general purpose input output circuit 100 comprising: a channel selection unit 120, a first trigger 130, an input module, and an output module 110;
the first end of the channel selection unit 120 is used for being connected with a pin, the second end of the channel selection unit 120 is connected with the input module and the output module 110, and the third end of the channel selection unit 120 is connected with the wake-up module 220 in the chip internal circuit 200 through the first trigger 130;
the pin is used for being connected with the external device 300, and is used for receiving an external interrupt signal sent by the external device 300 when the chip internal circuit 200 is in a stop mode and transmitting the external interrupt signal to the first end of the channel selection unit 120; in the stop mode, the clock module 210 in the chip internal circuit 200 stops generating the clock signal;
when the first end of the channel selection unit 120 receives the external interrupt signal, the first end of the channel selection unit 120 is connected to the third end of the channel selection unit 120, so that the external interrupt signal is transmitted to the wake-up module 220, the external interrupt signal is used for controlling the wake-up module 220 to generate a wake-up signal, and the wake-up signal is used for controlling the clock module 210 to generate a clock signal.
The clock module of its internal circuit stops producing clock signal under the stop mode, general input output circuit's pin receives external interrupt signal, the passageway select element is put through pin i.e. first end and third end for external interrupt signal can transmit to the awakening module, and then control clock module produces clock signal awakening chip, and the general input output circuit that this application provided can be suitable for various peripheral hardware awakening sources, greatly increased the awakening source quantity of chip when stopping mode, make general input output circuit possess the function that supports peripheral hardware awakening, and then improve the flexibility and the adaptability of chip.
Alternatively, the external terminal signal may be a level change signal; an input voltage signal which can be the RX pin of USART, CLK or SDA of I2C, CLK of SPI, ADC; but also a timer or a signal value on a switch pin (e.g. a button is pressed), etc.
In one embodiment, as shown in fig. 2, the pin is further used to receive an external input signal sent by the external device 300 when the chip internal circuit 200 exits the stop mode;
when the first end of the channel selection unit 120 receives an external input signal, the first end of the channel selection unit 120 and the second end of the channel selection unit 120 are connected, so that the external input signal is transmitted to the input module and the output module 110.
The first end and the second end of the channel selection unit are communicated, so that the external equipment can transmit data to the chip through the input module and the output module, and the communication function of the chip and the external equipment is ensured.
In one embodiment, the first terminal of the channel selection unit and the second terminal of the channel selection unit are turned on when the second terminal of the channel selection unit receives the output signal, so that the output signal is transmitted to the pin.
Therefore, the chip can transmit data to the external equipment through the input module and the output module in the general input/output circuit, and the communication function of the chip and the external equipment is ensured.
In one embodiment, as shown in fig. 3, the channel selection unit includes a first selection register 121 and a second selection register 122; the input and output modules include an input module 112 and an output module 111;
a first end of the first selection register 121 is connected with a pin, and a second end of the first selection register 121 is connected with the output module 111; the third terminal of the first selection register 121 is suspended; when the first end of the first selection register 121 receives the external interrupt signal, the first end of the channel selection unit is connected with the third end of the first selection register 121, and the external interrupt signal cannot pass through the output module because the third end of the first selection register is suspended;
the first end of the second selection register 122 is connected with a pin, the second end of the second selection register 122 is connected with the input module 112, and the third end of the second selection register 122 is connected with the wake-up module; when the first end of the second selection register 122 receives the external interrupt signal, the first end of the second selection register 122 is connected to the third end of the second selection register 122, so that the external interrupt signal is transmitted to the wake-up module 220 through the first trigger.
After the pin receives an external interrupt signal sent by external equipment, the first end and the third end of the second selection register are communicated, so that the external interrupt signal received by the pin can be transmitted to the wake-up module to wake-up the chip.
In one embodiment, the first selection register includes a high level terminal 1 and a low level terminal 0, a third terminal of the first selection register is a high level terminal, and a second terminal of the first selection register is a low level terminal; the second selection register comprises a high level end 1 and a low level end 0, the third end of the second selection register is a high level end, and the second end of the second selection register is a low level end; or the first selection register comprises a high level end 1 and a low level end 0, the second end of the first selection register is a high level end, and the third end of the first selection register is a low level end; the second selection register includes a high-level end and a low-level end, the second end of the second selection register is the high-level end, the third end of the second selection register is the low-level end, and specifically, the setting can be determined according to practical situations, and the illustration of the application is only one embodiment.
In one embodiment, when the first end of the second selection register receives an external input signal, the first end of the second selection register is connected with the second end of the second selection register, so that the external input signal is transmitted to the input module;
when the second end of the first selection register receives the output signal, the second end of the first selection register is communicated with the first end of the first selection register, so that the output signal is transmitted to an external pin.
The chip and the external equipment can carry out communication such as data transmission and the like through the input module and the output module in the general input/output circuit.
The general purpose input/output circuit is suitable for various peripheral equipment awakening sources, can solve the problem that the original GPIO structure cannot directly receive external signals under a stop mode and input the external interrupt, greatly improves the number of the awakening sources capable of awakening chips under the stop mode, ensures low power consumption, and can awaken the chips in real time, thereby meeting application requirements.
In one embodiment, as shown in fig. 4, the general purpose input output circuit further includes a first flip-flop;
the input end of the first trigger is connected with the third end of the second selection register, and the output end of the first trigger is connected with the wake-up module.
In one embodiment, the trigger is a schottky trigger or a TTL schmitt trigger, the response speed is extremely high, the trigger can be used in a high-speed digital circuit, and meanwhile, the trigger has the advantages of stable output signal, simple structure, high reliability and lower power consumption, and can be used in a low-power-consumption circuit.
In one embodiment, the wake-up module is an external interrupt controller (EINT).
In one embodiment, the input module includes an input driver and an input data register;
the input end of the input driver is connected with the pin, the output end of the input driver is connected with the input end of the input data register, and the output end of the input data register is connected;
the input driver comprises an input mode circuit and a second trigger; the input end of the input mode circuit is used as the input end of the input driver, the output end of the input mode circuit is connected with the first end of the second selection register, the second end of the second selection register is connected with the input end of the second trigger, the output end of the second trigger is used as the output end of the input driver, and the third end of the second selection register is connected with the input end of the first trigger.
Optionally, the input mode circuit includes a pull-up resistor and a pull-down resistor.
In a second aspect, the present application further provides a control method of a general input output circuit, where the general input output circuit is used for connecting with an external device, and the general input output circuit is further used for connecting with an internal circuit of a chip, and the general input output circuit includes: the device comprises a channel selection unit, an input module and an output module; the first end of the channel selection unit is used for being connected with a pin, and the pin is used for being connected with external equipment; the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is used for being connected with the wake-up module in the internal circuit of the chip; the method comprises the following steps:
step S510, when detecting that the external interrupt signal sent by the external device is received on the pin when the internal circuit of the chip is in the stop mode, generating a first control signal of the channel selection unit;
the first control signal is used for enabling the first end of the channel selection unit to be communicated with the third end of the channel selection unit, enabling the external interrupt signal to be transmitted to the wake-up module, enabling the external interrupt signal to be used for controlling the wake-up module to generate a wake-up signal, and enabling the wake-up signal to be used for controlling the clock module to generate a clock signal; in the stop mode, the clock module in the chip internal circuit stops generating the clock signal.
In one embodiment, the method further comprises:
step S520, when detecting that the external input signal sent by the external device is received on the pin when the internal circuit of the chip is in the exit stop mode, generating a second control signal;
the second control signal is used for enabling the first end of the channel selection unit to be communicated with the second end of the channel selection unit, and enabling the external input signal to be transmitted to the input module and the output module.
In one embodiment, the method further comprises the steps of:
step S530, when the second end of the channel selection unit receives the output signal when the internal circuit of the chip is in the stop mode, generating a third control signal;
the third control signal is used for enabling the first end of the channel selection unit to be communicated with the second end of the channel selection unit, and enabling the output signal to be transmitted to the pin.
The application also provides a control method of the general input/output circuit, as shown in fig. 5, the method comprises the following steps:
step S510, when detecting that the external interrupt signal sent by the external device is received on the pin when the internal circuit of the chip is in the stop mode, generating a first control signal of the channel selection unit;
step S520, when detecting that the external input signal sent by the external device is received on the pin when the internal circuit of the chip is in the exit stop mode, generating a second control signal;
step S530, when the second end of the channel selection unit receives the output signal when the internal circuit of the chip is in the stop mode, a third control signal is generated.
The general input/output circuit control method is suitable for various peripheral wake-up sources, can solve the problem that the original GPIO structure cannot directly receive external signals in a stop mode and input the external interrupt, greatly improves the number of wake-up sources capable of waking up chips in the stop mode, ensures low power consumption, and can wake up the chips in real time, thereby meeting application requirements.
In a third aspect, the present application further provides a chip, including a chip internal circuit and a pin, where the chip internal circuit and the pin are connected by the above-mentioned universal input/output circuit.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A universal input output circuit for connecting to an external device, the universal input output circuit further for connecting to an internal chip circuit, the universal input output circuit comprising: the device comprises a channel selection unit, a first trigger, an input module and an output module;
the first end of the channel selection unit is connected with a pin, the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is connected with a wake-up module in the chip internal circuit through the first trigger;
the pin is used for being connected with the external equipment, receiving an external interrupt signal sent by the external equipment when the internal circuit of the chip is in a stop mode, and transmitting the external interrupt signal to the first end of the channel selection unit; the clock module in the chip internal circuit stops generating the clock signal in the stop mode;
and when the first end of the channel selection unit receives the external interrupt signal, the first end of the channel selection unit is communicated with the third end of the channel selection unit.
2. The universal input output circuit of claim 1, wherein the pin is further configured to receive an external input signal sent by the external device when the chip internal circuit exits a stop mode;
and when the first end of the channel selection unit receives the external input signal, the first end of the channel selection unit is communicated with the second end of the channel selection unit, so that the external input signal is transmitted to the input module and the output module.
3. The universal input-output circuit according to claim 2, wherein the first terminal of the channel selection unit and the second terminal of the channel selection unit are turned on when the second terminal of the channel selection unit receives an output signal, and the output signal is transmitted to the pin.
4. A universal input output circuit according to any one of claims 1 to 3, wherein the channel selection unit comprises a first selection register and a second selection register;
the first end of the first selection register is connected with the pin, and the second end of the first selection register is connected with the output module; the third end of the first selection register is suspended; when the first end of the first selection register receives the external interrupt signal, the pin is communicated with the third end of the first selection register;
the first end of the second selection register is connected with the pin, the second end of the second selection register is connected with the input module, and the third end of the second selection register is connected with the wake-up module through the first trigger; and when the first end of the second selection register receives the external interrupt signal, the pin is communicated with the third end of the second selection register, so that the external interrupt signal is transmitted to the wake-up module through the first trigger.
5. The universal input-output circuit of claim 4, wherein the first terminal of the second select register is turned on when the first terminal of the second select register receives the external input signal, causing the external input signal to be transmitted to the input module;
when the second end of the first selection register receives the output signal, the second end of the first selection register is communicated with the first end of the first selection register, so that the output signal is transmitted to the external pin.
6. The universal input output circuit of claim 4, wherein the input module comprises an input driver and an input data register;
the input end of the input driver is connected with the pin, and the output end of the input driver is connected with the input end of the input data register;
the input driver includes an input mode circuit and a second flip-flop; the input end of the input mode circuit is connected with the pin, and the output end of the input mode circuit is connected with the first end of the second selection register;
the input end of the second trigger is connected with the second end of the second selection register, and the output end of the second trigger is used as the output end of the input driver.
7. A control method of a general input output circuit, wherein the general input output circuit is used for connecting an external device, the general input output circuit is also used for connecting an internal circuit of a chip, and the general input output circuit comprises: the device comprises a channel selection unit, a first trigger, an input module and an output module; the first end of the channel selection unit is connected with a pin, and the pin is used for being connected with the external equipment; the second end of the channel selection unit is connected with the input module and the output module, and the third end of the channel selection unit is connected with the wake-up module in the chip internal circuit through the first trigger;
when the internal circuit of the chip is in a stop mode and the external interrupt signal sent by the external equipment is detected to be received on the pin, a first control signal of the channel selection unit is generated;
the first control signal is used for enabling the first end of the channel selection unit and the third end of the channel selection unit to be communicated, enabling the external interrupt signal to be transmitted to the wake-up module, wherein the external interrupt signal is used for controlling the wake-up module to generate a wake-up signal, and the wake-up signal is used for controlling the clock module to generate a clock signal; in the stop mode, the clock module in the chip internal circuit stops generating the clock signal.
8. The method for controlling a universal input output circuit according to claim 7, further comprising:
when the internal circuit of the chip is in the exit stop mode, the pin is detected to receive an external input signal sent by the external equipment, and a second control signal is generated;
the second control signal is used for enabling the first end of the channel selection unit to be communicated with the second end of the channel selection unit, so that the external input signal is transmitted to the input module and the output module.
9. The method for controlling a universal input/output circuit according to claim 7, wherein,
when the second end of the channel selection unit receives an output signal when the internal circuit of the chip is in the exit stop mode, a third control signal is generated;
the third control signal is used for enabling the first end of the channel selection unit and the second end of the channel selection unit to be connected, so that the output signal is transmitted to the pin.
10. A chip comprising an internal chip circuit and a pin, wherein the internal chip circuit and the pin are connected through the universal input-output circuit according to any one of claims 1 to 6.
CN202311272329.9A 2023-09-27 2023-09-27 General input/output circuit, general input/output circuit control method and chip Pending CN117271397A (en)

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CN202311272329.9A CN117271397A (en) 2023-09-27 2023-09-27 General input/output circuit, general input/output circuit control method and chip

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