CN117270921A - Multi-core embedded system based on serial port IAP and firmware program online updating method thereof - Google Patents

Abstract

The invention relates to a multi-core embedded system based on serial port IAP and a firmware program online updating method thereof. The off-chip memory chip of the system is divided into at least 5 areas and is used for storing program programming identification data frames, equipment delivery ARM and FPGA firmware programs and ARM and FPGA firmware programs to be upgraded respectively, and the contents in the areas 2-5 are written into the appointed area in the off-chip memory chip through ARM serial ports. When the ARM receives the programming instruction, the appointed part of the content in the corresponding partition of the off-chip memory chip is automatically read to the appointed position of the FLASH inside the ARM and the configuration chip of the FPGA to finish upgrading or recovering, and after the updating is finished, the system is restarted and a new firmware program is automatically operated. After the product is released, the firmware programs of the ARM and the FPGA can be upgraded or recovered on line through the reserved communication interface conveniently and rapidly, and the method has the advantages of being high in efficiency, low in cost, convenient to operate and the like.

Description

Multi-core embedded system based on serial port IAP and firmware program online updating method thereof

Technical Field

The invention relates to the technical field of embedded equipment control and software, in particular to a multi-core embedded system based on serial port IAP and a firmware program online updating method thereof.

Background

With the development of serial IAP technology, it has been gradually applied to online upgrade of separate ARM or FPGA firmware programs. However, in most embedded control systems, ARM and FPGA embedded technologies are often combined. In the prior art, ARM and FPGA programming interfaces reserved by the system are traditional SWD interfaces and JTAG interfaces, so that when a product is tested in an outfield or after a user is handed over, if related software is required to be updated, a professional can only carry a designated simulator to go to the site of the product for updating, and the system has high cost, low efficiency and various limitations and inconveniences. More importantly, the professional may need to disassemble the product (e.g., remove the cap) during field updates, and similar operations greatly destroy the air tightness and water resistance of the product, resulting in some of its properties being compromised.

In order to ensure the performance of the embedded product and the convenience of use and maintenance, it is important to develop a method which can be applied to online upgrading of the multi-core embedded firmware program.

Disclosure of Invention

The invention aims to provide a multi-core embedded system based on serial port IAP, which comprises an ARM part, an FPGA part, an off-chip memory chip and a serial port box. The ARM part, the FPGA part and the off-chip memory chip are packaged together to form equipment with certain functions. The ARM part is respectively and electrically connected with the serial port box, the FPGA part and the off-chip storage chip and performs one-way or two-way communication, so that data, instructions and the like are transmitted.

Furthermore, the system also comprises a PC end, and the PC end can be electrically connected with the ARM part through the serial port box and can carry out one-way or two-way communication when needed.

Further, the ARM part stores firmware programs, wherein the firmware programs comprise Bootloader programs and user application programs (APP). The Bootloader program is mainly used for self-checking whether related firmware programs (including ARM firmware programs and FPGA firmware programs) need to be updated after a product or equipment is powered on, and the user application program is mainly used for receiving instructions and bin files sent by a PC (personal computer) end.

Further, the FPGA part comprises an FPGA main chip and a configuration chip which are electrically connected and in bidirectional communication, and the configuration chip stores an FPGA firmware program.

Furthermore, the off-chip memory chip can be FLASH or EEPROM, wherein ARM firmware programs and FPGA firmware programs required for upgrading or recovering are stored or backed up.

Furthermore, the off-chip memory chip is divided into at least 5 areas according to the address range, and each area is respectively used for storing different contents, including program programming identification data frames, multi-core embedded equipment factory ARM user application programs and FPGA firmware programs, and ARM user application programs and FPGA firmware programs which need to be upgraded according to user requirements.

Furthermore, the interface communication form of the serial port box and the ARM is a serial port DMA mode, and the serial port box and ARM interface communication form is mainly used for receiving upgrade instructions and bin files of upgrade programs. By adopting the serial port DMA mode, the advantages of DMA receiving completion interrupt, serial port idle interrupt and the like are combined, and compared with common serial port communication, the scheme greatly reduces the interrupt times and improves the working efficiency of the MCU.

The second purpose of the invention is to provide a multi-core embedded system firmware program on-line updating method based on serial port IAP, which mainly comprises the following steps: after the equipment is powered on, the ARM part firstly runs a Bootloader program and automatically checks whether the ARM part and the FPGA part need to upgrade firmware programs, if so, the firmware programs in the appointed address of the chip stored outside the chip are automatically added to the ARM or FPGA configuration chip through the communication interface, and the recovery or upgrade of the system ARM and the FPGA programs is realized; if not, the user application program is jumped to normally run, and in the running process of the user application program, if the firmware program file required by updating the ARM part or the FPGA part is received, the firmware program file is stored in an off-chip storage chip for standby.

Further, after the ARM part receives an update (upgrade or recovery) instruction, corresponding firmware program files stored in the off-chip storage chip are automatically added to a FLASH user application program area built in the ARM part or a configuration chip of the FPGA part for updating, the system is automatically restarted and operates the updated program after the firmware program of the ARM part is updated, and the system does not need to be restarted to directly operate the updated program after the firmware program of the FPGA part is independently updated.

The invention can simultaneously update or restore the firmware programs of ARM and FPGA on line through the reserved communication interface after the release of the product, does not need special personnel to perform on-site operation, does not damage the sealing structure of the product, and has the advantages of high efficiency, low maintenance cost and the like. In addition, the invention does not need an emulator, and improves the convenience and maintainability of product production debugging, engineering maintenance and software recovery or upgrading. The system and the method have the advantages of strong anti-interference capability, less interface signals and the like, and can also use other communication interfaces (such as SPI, IIC and the like) according to the requirements of users.

Drawings

FIG. 1 is a schematic diagram of a multi-core embedded system;

FIG. 2 is a schematic diagram of a firmware program upgrade process of the ARM portion;

FIG. 3 is a schematic diagram of a firmware program upgrade process of the FPGA portion;

fig. 4 is a serial communication protocol.

Detailed Description

In order to fully understand the technical scheme and the advantages of the present invention for those skilled in the art, the following more detailed description is given with reference to specific embodiments and the accompanying drawings.

The multi-core embedded system based on the serial IAP shown in fig. 1 mainly comprises a PC end, an ARM part, an FPGA part, an off-chip memory chip and a serial box, wherein other elements except the PC end and the serial box are packaged together. The ARM part is electrically connected with the FPGA part and the off-chip memory chip at the same time, and is in bidirectional communication with the FPGA part, and is in bidirectional communication with the off-chip memory chip, so that the transmission and execution of data and instruction sets are realized. When the system needs to be upgraded or recovered, the PC end is electrically connected with the ARM part through the serial port box and performs bidirectional communication and data exchange in a serial port DMA mode. The ARM part is an execution main body, an operation starting instruction is directly issued to the ARM part through the serial port box by the PC end, and an ending instruction is issued after the ARM part is operated.

The FLASH in the ARM part is divided into two parts, the initial part is used for storing a Bootloader program, and the later part is used for storing a user application program. The FPGA part comprises an FPGA main chip and a configuration chip, and the FPGA main chip is mainly used for storing FPGA firmware programs. The off-chip memory chip (FLASH or EEPROM) is divided into at least 5 areas according to the address range, and the specific functions of each area are as follows: zone 1 is used for storing identifiers, zone 2 is used for storing ARM firmware program delivery version V1.00.00, zone 3 is used for storing FPGA firmware program delivery version V1.00.00, zone 4 is used for storing ARM firmware programs to be updated later, and zone 5 is used for storing FPGA firmware programs to be updated later. Of these 5 partitions, the content stored in sections 2 and 3 prohibits user modification, while the content stored in sections 4 and 5 may be modified by the user because sections 2 and 3 are used primarily for recovery and sections 4 and 5 are used primarily for update iterations.

After the system is powered on, the ARM part firstly runs a Bootloader program, the Bootloader program reads an identifier in a designated address in a region 1 of an off-chip storage chip, if the identifier is detected to be updated, corresponding content is read from the designated region (region 2-region 5) of the off-chip storage chip into a user application program region in an ARM built-in FLASH and a configuration chip of an FPGA, and then jumps to the user application program part to finish updating of the ARM program, and resets the FPGA chip by controlling the high and low levels of nConfig and nCE pins of the FPGA chip, so that updating of the FPGA program is realized. If the updating identifier is not detected, the user application program running to the ARM is directly jumped, and the FPGA chip is reset and the main circulation part of the ARM user program is run.

As shown in fig. 2-4, the method for upgrading the system firmware program specifically includes the following steps:

1. inputting ARM firmware program (or FPGA firmware program) in a serial port DMA mode through a reserved external communication port to prepare a transmission instruction;

2. the content of the off-chip storage chip area 4 (the area 5 for the FPGA) is erased, so that the off-chip storage chip can be written. After the erasure is completed, feeding back an erasure completion result to wait for writing the identification state;

3. after receiving the mark waiting for writing, writing the prepared ARM user program bin file into a region 4 in the off-chip storage chip in a DMA mode through a reserved serial port communication port, and waiting for prompting the completion of writing;

4. after writing is completed, CRC (except for the last 2 check bytes) check is carried out on the written content, if the CRC check is correct, a writing completion identification is sent, an ARM (or FPGA) to-be-updated identification is written in the area 1, and otherwise, the steps 1-3 are carried out again;

5. repeating the steps 1-4 after the correct writing is completed, starting to write the bin file of the FPGA firmware program, and waiting for the correct writing to complete the feedback identification state;

6. and sending a program starting instruction to start burning through the communication port, and resetting and rerun the ARM program to the starting section of the Bootloader program.

7. And detecting the identification to be updated of the off-chip storage chip area 1 by using a Bootloader program, automatically reading the content of the appointed area in the off-chip storage chip into the ARM user application program area (such as area 4) and the configuration chip of the FPGA (such as area 5), waiting for the completion of the burning, feeding back the identification to be updated, and clearing the corresponding identification to be updated in the area 1.

8. And after the updating is finished, the ARM program jumps and moves to the user application section from the Bootloader section.

9. And after the hardware is powered down and restarted, running the updated ARM and FPGA programs to finish the updating of the programs.

10. If the FPGA program is updated, the ARM firmware program does not need to be subjected to step 9, and the FPGA firmware program can be reset through controlling the high and low levels of the nConfig pins and the nCE pins of the FPGA chip, so that the FPGA firmware program can be updated.

As shown in fig. 2-4, the recovery method of the system firmware program is specifically as follows:

1. and sending a program preparation restoration instruction in a serial port DMA mode through a reserved communication port, writing an ARM firmware program and an FPGA firmware program to-be-restored identifier in a corresponding address section of the off-chip memory chip area 1, and feeding back the waiting program restoration identifier.

2. And sending a program start recovery instruction in a serial port DMA mode through a reserved communication port, closing all interrupts by the ARM program, resetting by the software, and jumping to a program start address to run a Bootloader program.

And 3. The bootloader program detects the program to-be-restored identification in the appointed address section in the off-chip storage chip area 1, automatically reads the content in the off-chip storage chip area 2 into the ARM user application program address section and the content in the area 4 into the configuration chip of the FPGA, clears the program to-be-restored identification and feeds back the restoration completion state.

4. Program jump goes to ARM user program.

5. And (5) restarting the hardware to finish the restoration of the program.

6. If the FPGA firmware program is only recovered, the ARM firmware program does not need to carry out step 5, and the reset of the FPGA firmware program can be finished through the control of the high and low levels of the nConfig pins and the nCE pins of the FPGA chip, so that the recovery of the FPGA firmware program is finished.

The method for simultaneously upgrading or recovering the ARM user program and the FPGA program can also be used for independently upgrading or recovering the ARM or the FPGA firmware program, wherein the updating of the ARM firmware program is related to the need of restarting the system, and the updating of the FPGA firmware program is not needed to restart the system.

Claims (10)

1. The utility model provides a multicore embedded system based on serial ports IAP which characterized in that: the system comprises an ARM part, an FPGA part, an off-chip memory chip and a serial port box, wherein the ARM part, the FPGA part and the off-chip memory chip are packaged together to form hardware equipment, and the ARM part is electrically connected with the serial port box, the FPGA part and the off-chip memory chip respectively and performs unidirectional or bidirectional communication.

2. The system of claim 1, wherein: the system also comprises a PC end, wherein the PC end is electrically connected with the ARM part through the serial port box and performs one-way or two-way communication.

3. The system of claim 1, wherein: the ARM part stores firmware programs, and the firmware programs comprise Bootloader programs and user application programs.

4. A system as claimed in claim 3, wherein: the Bootloader program automatically checks whether the ARM firmware program or the FPGA firmware program needs to be updated after the device is powered on, and the user application program can receive instructions and bin files sent by the PC end.

5. The system of claim 1, wherein: the FPGA part comprises an FPGA main chip and a configuration chip which are electrically connected and in bidirectional communication, and the configuration chip stores an FPGA firmware program.

6. The system of claim 1, wherein: the off-chip memory chip is FLASH or EEPROM, and ARM firmware programs and FPGA firmware programs required for upgrading and recovering are stored or backed up.

7. The system of claim 6, wherein: the off-chip memory chip is divided into at least 5 areas according to the address range, and each area stores different contents, including a program programming identification data frame, a multi-core embedded device factory ARM user application program, a multi-core embedded device factory FPGA firmware program, an ARM user application program to be upgraded and an FPGA firmware program to be upgraded.

8. The system of claim 1, wherein: the interface communication form of the serial port box and the ARM is a serial port DMA mode.

9. The method for online updating of the firmware program of the multi-core embedded system based on the serial port IAP as claimed in any one of claims 1 to 8, wherein the method comprises the following steps: after the equipment is powered on, the ARM part firstly runs a Bootloader program and automatically checks whether the ARM part and the FPGA part need to upgrade firmware programs, if so, the firmware programs in the appointed address of the chip stored outside the chip are automatically added to the ARM or FPGA configuration chip through the communication interface, and the recovery or upgrade of the system ARM and the FPGA programs is realized; if not, the user application program is jumped to normally run, and in the running process of the user application program, if the firmware program file required by updating the ARM part or the FPGA part is received, the firmware program file is stored in an off-chip storage chip for standby.

10. The method of claim 9, wherein: after the ARM part receives the upgrade or recovery instruction, the corresponding firmware program file stored in the chip outside the slide is automatically added to a FLASH user application program area built in the ARM part or a configuration chip of the FPGA part for updating, the system is automatically restarted and operates the updated program after the firmware program of the ARM part is updated, and the system does not need to restart the updated program directly after the firmware program of the FPGA part is independently updated.