CN117270858A - Front-end solution method and device for parallel compiling of hardware description language - Google Patents

Abstract

The embodiment of the application provides a front-end solution method and device for HDL parallel compiling. Wherein the method comprises the following steps: obtaining a first AST equivalent to the original design according to the original design; obtaining M sub designs according to the first AST; m HDL file groups corresponding to the M sub designs one by one are obtained according to the M sub designs, the M HDL file groups are independent of each other, each HDL file group in the M HDL file groups comprises one or more HDL files, the M HDL file groups correspond to K compilers, each compiler is used for compiling the corresponding one or more HDL file groups, M is a positive integer greater than or equal to 2, and K is a positive integer greater than or equal to 1 and less than or equal to M. The M HDL file groups obtained by the method can be independently transmitted to a back-end compiling tool, so that the back-end compiling tool can compile the M HDL file groups in parallel.

Description

Front-end solution method and device for parallel compiling of hardware description language

Technical Field

The embodiment of the application relates to the technical field of hardware design, and more particularly relates to a front-end solution method and device for parallel compiling of hardware description languages.

Background

Hardware description languages (Hardware Description Language, HDL), e.g., verilog HDL, VHDL, etc., are languages for electronic system hardware behavioral description, structural description, dataflow description. With this language, the design of digital circuitry can describe its design ideas layer by layer from top to bottom (from abstract to concrete), representing extremely complex digital systems with a series of hierarchical modules. With the development of science and technology, the scale of hardware design is continuously increased, so that the compiling time of HDL language is gradually prolonged, and parallel compiling becomes the best way for solving the problems.

However, HDL languages are essentially different from traditional software languages (e.g., C, C ++, etc.), and the syntax of the HDL language itself does not guarantee that a single file or several files in an original input file can be compiled separately, and thus cannot be split directly on the original input file for parallel compilation, as in traditional software.

Therefore, how to implement parallel compilation of HDL languages is a technical problem that needs to be solved.

Disclosure of Invention

The embodiment of the application provides a front-end solution method and device for hardware description language HDL parallel compiling, which can realize the parallel compiling of HDL.

In a first aspect, a front-end solution for hardware description language HDL parallel compilation is provided, comprising: obtaining a first abstract syntax tree AST equivalent to the original design according to the original design; obtaining M sub-designs according to the first AST; according to the M sub designs, M HDL file groups corresponding to the M sub designs one by one are obtained, the M HDL file groups are independent of each other, each HDL file group in the M HDL file groups comprises one or more HDL files, the M HDL file groups correspond to K compilers, each compiler is used for compiling the corresponding one or more HDL file groups, M is a positive integer greater than or equal to 2, and K is a positive integer greater than or equal to 1 and less than or equal to M.

Optionally, the method may further include: an HDL file of a native design is obtained, which may include one HDL file as well as a plurality of HDL files.

Alternatively, the M sub-designs are obtained according to the first AST, which may also be described as splitting the first AST to obtain the M sub-designs.

It should be understood that the M HDL file groups are independent of each other, so that the M HDL file groups are independent of each other, and cannot be affected with each other in the compiling process, and can be compiled independently.

Alternatively, the M HDL file groups corresponding to the M sub-designs one by one are obtained according to the M sub-designs, or the M HDL file groups corresponding to the M sub-designs one by one can be output by decompiling according to the M sub-designs.

According to the front-end solution provided by the embodiment of the application, the original design is split to obtain M sub-designs, and M HDL file groups which are independent of each other are obtained according to the M sub-designs, so that the M HDL file groups can be independently transmitted to a back-end compiling tool, and further the back-end compiling tool can compile the HDL files in parallel.

Optionally, in the back-end compiling process, the M HDL file groups may correspond to K compilers, so that parallel compiling of the M HDL file groups is implemented by the K compilers. Optionally, each of the K compilers may compile one or more HDL file groups, and the distribution manner of the back-end compiler is not limited in this application. Optionally, when m=k, the M HDL file groups may correspond to M compilers, so that parallel compiling of the M HDL file groups is implemented by the M compilers.

With reference to the first aspect, in certain implementations of the first aspect, the first AST includes a plurality of nodes, a first node of the plurality of nodes having cross-module reference XMR access exists, and deriving M sub-designs according to the first AST includes: rewriting the first AST to obtain a second AST, wherein the second AST does not have XMR access; the M sub-designs are obtained according to the second AST.

Optionally, there may or may not be any node accessed by XMR among the multiple nodes of the actual first AST, which needs to be determined according to whether XMR access is designed in the original design, which is not limited in this application.

In the embodiment of the present application, if a first node accessed by XMR exists among a plurality of nodes of a first AST, the first AST may be rewritten to obtain a second AST without XMR access, and M sub-designs are obtained according to the second AST, so that dependencies between sub-designs due to XMR access are eliminated, and a precondition is created for parallel compilation.

With reference to the first aspect, in certain implementations of the first aspect, the overwriting the first AST includes: obtaining a second node referenced by the first node; obtaining a module spanned on a path from the first node to the second node; adding ports to all modules spanned on the path; rewriting XMR access of the first node into port access; obtaining a minimum common parent node from the first node to the second node; adding local variable on the minimum public father node and completing functional port connection.

With reference to the first aspect, in some implementations of the first aspect, instantiating the module that does not belong to the first sub-design in a first sub-design of the M sub-designs, the obtaining M HDL file groups that are in one-to-one correspondence with the M sub-designs according to the M sub-designs includes: creating a forward declaration of the instantiated module based on the inputs and outputs of the instantiated module in the first sub-design; and obtaining the HDL file group corresponding to the first sub-design according to the first sub-design and the forward declaration of the instantiated module in the first sub-design.

It should be understood that the forward declaration includes the input and output of the instantiated module and does not include the implementation of the module specific content.

In this embodiment of the present application, if a module that does not belong to a first sub-design is instantiated in a first sub-design of the M sub-designs, an HDL file set corresponding to the first sub-design may be obtained according to the first sub-design and a forward declaration of the instantiated module in the first sub-design, so that the HDL file set corresponding to the first sub-design may be compiled independently in a black-box mode.

With reference to the first aspect, in certain implementation manners of the first aspect, the first AST includes a global element therein, and the method further includes: a common HDL file is obtained from the first AST, the common HDL file including global elements, one or more of the M HDL file groups referencing the common HDL file.

It should be understood that a global element refers to an element that is accessible to all modules in the current design.

Optionally, the global element may or may not be included in the actual first AST, which needs to be determined according to whether the global element is designed in the original design, which is not limited in this application.

In this embodiment of the present application, if the first AST includes a global element, a common HDL file may be obtained according to the first AST, and one or more of the M HDL file groups may refer to the common HDL file, thereby creating a precondition for parallel compilation of the M HDL file groups.

With reference to the first aspect, in certain implementations of the first aspect, the global element includes one or more of a global structure, a global task, a global interface, and a global function.

With reference to the first aspect, in some implementations of the first aspect, if the originally designed module specifies an instantiation parameter at the time of instantiation, the M sub-designed modules use actual values to replace the instantiation parameter at the time of instantiation.

In the embodiment of the application, if the originally designed module specifies the instantiation parameter during instantiation, the actual values of the M sub-designed modules may be used to replace the instantiation parameter during instantiation, thereby creating preconditions for parallel compilation of the M HDL file groups.

With reference to the first aspect, in certain implementations of the first aspect, each HDL file in the M groups of HDL files adopts a target format, which includes target indentation and linefeed.

In the embodiment of the application, each HDL file in M HDL file groups also needs to meet a target format, so that relevant personnel can be helped to debug the HDL file in the using process.

In a second aspect, a front-end solution apparatus for parallel compilation of hardware description language HDL is provided, comprising means for performing the front-end solution as in the first aspect or in any of the possible implementations of the first aspect.

In a third aspect, a front-end solution for parallel compilation of hardware description language HDL is provided, comprising at least one processor for coupling with a memory, reading and executing instructions in said memory to implement a front-end solution as in the first aspect or in any of the possible implementations of the first aspect.

In a fourth aspect, a computer readable storage medium is provided, the computer readable storage medium storing computer instructions that, when run on a computer, implement a front-end solution as in the first aspect or any one of the possible implementations of the first aspect.

Drawings

FIG. 1 is a diagram showing an example of a system architecture for HDL parallel compilation according to an embodiment of the present application.

FIG. 2 is an exemplary diagram of a front-end solution for HDL parallel compilation provided in an embodiment of the present application.

FIG. 3 is an exemplary diagram of another front-end solution for HDL parallel compilation provided in an embodiment of the present application.

Fig. 4 is a flowchart illustrating a first AST rewriting process according to an embodiment of the present application.

Fig. 5 is an exemplary diagram for rewriting XMR access into port access provided in an embodiment of the present application.

FIG. 6 is another exemplary diagram for rewriting XMR access to port access provided by an embodiment of the present application.

Fig. 7 is a flowchart illustrating an example of an AST decompilation module according to an embodiment of the present application.

FIG. 8 is a diagram of an exemplary design without XMR access provided by an embodiment of the present application.

FIG. 9 is an exemplary diagram of a common HDL file output based on the design shown in FIG. 8.

FIG. 10 is an exemplary diagram of HDL files for sub-design 1 based on the design output shown in FIG. 8.

FIG. 11 is an exemplary diagram of HDL files for sub-design 2 based on the design output shown in FIG. 8.

FIG. 12 is an exemplary diagram of HDL files for sub-design 3 based on the design output shown in FIG. 8.

FIG. 13 is a front-end solution for HDL parallel compilation provided by embodiments of the present application.

FIG. 14 is an exemplary block diagram of a hardware architecture of a front-end solution for HDL parallel compilation provided in an embodiment of the present application.

Detailed Description

For ease of understanding, the background art to which embodiments of the present application relate will be further described first.

Currently, some commercial companies have successfully implemented parallel compilation of HDL language, for example, commercial companies provide a compilation type Verilog simulator (Verilog Compile Simulator, VCS) that provides a-j compilation option to support parallel compilation. However, the electronic design automation (Electronic Design Automation, EDA) provided by these commercial companies is a front-end and back-end integrated closed environment and does not provide an intermediate result acquisition interface, so that other EDA tools cannot be compiled in parallel with these commercial EDA tools.

Although the HDL front end analysis tool Verific commonly used in the industry provides a front end access interface, the HDL files output by the access interface have dependence, and can only be used for debugging of an EDA tool, and cannot be used for parallel compiling of a back end EDA tool chain.

Based on this, the embodiments of the present application provide a front-end solution for HDL parallel compilation, by processing an original design at the front-end, outputting multiple independent HDL file sets, which can be independently transferred to a back-end EDA tool, so that the back-end EDA tool can compile these file sets in parallel.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing an example of a system architecture for HDL parallel compilation according to an embodiment of the present application. As shown in FIG. 1, N HDL files (where N is a positive integer greater than or equal to 1) related to an original design (design) are first input to a processing module; then the processing module performs splitting, decompiling and other treatments on the original design, outputs M HDL file groups corresponding to M sub designs (M is a positive integer greater than or equal to 2), and the M HDL file groups are independent from each other and have no dependence; inputting M HDL file groups into an EDA compiler at the back end in parallel, so that the back end EDA compiler can compile the file groups in parallel; and finally, merging the compiling results of the M HDL file groups to obtain the compiling results corresponding to the original design. It should be understood that the number of EDA compilers at the back end is merely an example, and in actual operation, if resources are tensed, a smaller number of EDA compilers may be used, where each EDA compiler may correspond to one or more HDL file groups, which is not limited in this application.

FIG. 2 is an exemplary diagram of a front-end solution for HDL parallel compilation provided in an embodiment of the present application. It should be appreciated that the method 200 may be applied to the processing modules of FIG. 1 described above. As shown in fig. 2, the method 200 includes steps S210 to S230, which are described in detail below.

S210, obtaining a first abstract syntax tree (Abstract Syntax Tree, AST) equivalent to the original design according to the original design.

It should be understood that, where an AST is a syntax structure that represents source code using a tree structure, an AST may include multiple nodes, each of which represents a structure in the source code, which may include modules, expressions, and the like.

Optionally, before performing step S210, the method 200 may further include: an HDL file of a native design is obtained, which may include one HDL file as well as a plurality of HDL files.

Alternatively, the first AST equivalent to the original design may be obtained according to the original design, specifically, the first AST equivalent to the original design may be obtained by performing syntax analysis and interpretation (animation) on the input original design.

S220, obtaining M sub-designs according to the first AST.

Alternatively, the M sub-designs are obtained according to the first AST, which may also be described as splitting the first AST to obtain the M sub-designs.

Alternatively, there may or may not be a node accessed across module references (Cross Module Reference, XMR) in the actual first AST, which need to be determined according to whether XMR access was designed in the original design, which is not limited by the present application.

Where a module (module) is the basic unit of HDL language, which represents a basic block of units that describe the function or structure of a design, as well as external ports for communication with other modules.

Optionally, if there is a first node accessed by XMR among the plurality of nodes of the first AST, obtaining M sub-designs according to the first AST may include: rewriting the first AST to obtain a second AST, wherein the second AST does not have XMR access; the M sub-designs are obtained according to the second AST.

In the embodiment of the present application, if a first node accessed by XMR exists among a plurality of nodes of a first AST, the first AST may be rewritten to obtain a second AST without XMR access, and M sub-designs are obtained according to the second AST, so that dependencies between sub-designs due to XMR access are eliminated, and a precondition is created for parallel compilation.

Optionally, rewriting the first AST includes: obtaining a second node referenced by the first node; obtaining a module spanned on a path from a first node to a second node; adding ports to modules spanned on the path; obtaining the smallest public father node from the first node to the second node; rewriting XMR access of the first node into port access; and adding local variables on the smallest public father node, and completing functional port connection. It should be understood that the overwriting with respect to the first AST may be found in the relevant description of fig. 4 to 6 sections below.

It should be understood that the above manner of rewriting the first AST is merely an example, and other manners are possible in practice, which is not limited in this application.

S230, M HDL file groups corresponding to the M sub designs one by one are obtained according to the M sub designs, and the M HDL file groups are independent of each other.

Wherein M is a positive integer greater than or equal to 2.

It should be understood that the M HDL file groups are independent of each other, so that the M HDL file groups are independent of each other, and cannot be affected with each other in the compiling process, and can be compiled independently.

Alternatively, the M HDL file groups corresponding to the M sub-designs one by one are obtained according to the M sub-designs, or the M HDL file groups corresponding to the M sub-designs one by one can be output by decompiling according to the M sub-designs. It should be understood that each of the M HDL file groups includes one or more HDL files, meaning that each of the M sub-designs may decompil out one or more HDL files, as determined in connection with the contents of the sub-design without limitation.

Optionally, if a first sub-design of the M sub-designs instantiates a module not belonging to the first sub-design, obtaining M HDL file groups corresponding to the M sub-designs one-to-one according to the M sub-designs may include: creating a forward declaration of the instantiated module based on the inputs and outputs of the instantiated module in the first sub-design; and obtaining the HDL file group corresponding to the first sub-design according to the first sub-design and the forward declaration of the instantiated module in the first sub-design, see FIG. 10. It should be understood that the forward declaration includes the input and output of the instantiated module and does not include the implementation of the module specific content.

In this embodiment of the present application, if a module that does not belong to a first sub-design is instantiated in a first sub-design of the M sub-designs, an HDL file set corresponding to the first sub-design may be obtained according to the first sub-design and a forward declaration of the instantiated module in the first sub-design, so that the HDL file set corresponding to the first sub-design may be compiled independently in a black-box mode.

Optionally, the global element may or may not be included in the actual first AST, which needs to be determined according to whether the global element is designed in the original design, which is not limited in this application.

Optionally, if the first AST includes a global element, the method 200 may further include: a common HDL file is obtained according to the first AST, the common HDL file including global elements to which one or more of the M HDL file groups can refer.

In this embodiment of the present application, if the first AST includes a global element, a common HDL file may be obtained according to the first AST, and one or more of the M HDL file groups may refer to the common HDL file, thereby creating a precondition for parallel compilation of the M HDL file groups.

It should be understood that a global element refers to an element that is accessible to all modules in the current design. Alternatively, in actual operation, the M HDL file groups may all refer to the common HDL file, or only the HDL file group that needs to access the global element may refer to the common HDL file, which is not limited in this application.

Optionally, the global element may include one or more of a global structure struct, a global task, a global interface, a global function, and so on.

Alternatively, if the module of the original design specifies the instantiation parameter at the time of instantiation, the module of the M sub-designs replaces the instantiation parameter with the actual value at the time of instantiation, and at the same time, the generated code of the related generation Block (generation Block) or the like is expanded, which can be seen in the sub-designs 1 to 3 shown in fig. 10 to 12 below.

In the embodiment of the application, if the originally designed module specifies the instantiation parameter during instantiation, the actual values of the M sub-designed modules may be used to replace the instantiation parameter during instantiation, thereby creating preconditions for parallel compilation of the M HDL file groups.

Optionally, each HDL file in the M HDL file groups may be in a target format including target indentation and linefeed to facilitate debugging thereof by the relevant personnel during use.

In the embodiment of the application, by the front-end solution method for parallel compiling of HDL, the original design is split to obtain M sub-designs, and then M HDL file groups which are independent of each other are obtained according to the M sub-designs, so that the M HDL file groups can be independently transmitted to a back-end compiling tool, and further the back-end compiling tool can compile the HDL file groups in parallel.

Optionally, in the back-end compiling process, the M HDL file groups may correspond to K compilers, where K is a positive integer greater than or equal to 1 and less than or equal to M, and each compiler is configured to compile the corresponding one or more HDL file groups, so that parallel compiling of the M HDL file groups is achieved by the K compilers. Optionally, when m=k, the M HDL file groups may correspond to M compilers, so that parallel compiling of the M HDL file groups is implemented by the M compilers.

Referring to fig. 3 to 12, descriptions will be given below of the contents of AST rewriting and decompiling of the set of HDL files corresponding to the output common HDL and sub-design according to the present embodiment.

FIG. 3 is an exemplary diagram of another front-end solution for HDL parallel compilation provided in an embodiment of the present application. As shown in FIG. 3, for an input raw design HDL file, the processing module may perform the following steps:

1) The HDL file of the original design is first parsed and described to obtain a first AST equivalent to the original design.

2) The first AST is then input to an AST rewrite module to rewrite the XMR access in the first AST to a port access, and after the rewrite is completed, a new second AST is output to an AST decompilation module. It should be appreciated that the overwriting with respect to XMR access can be seen from the relevant description of the parts of fig. 4 to 6 below.

3) The AST decompilation module splits the second AST into a plurality of sub-designs, and decompiles each sub-design to output corresponding HDL file groups which can be independently compiled.

It should be understood that each of the sub-design decompiled output HDL file groups may include one HDL file or may include multiple HDL files, which need to be determined according to practical situations, and are not limited.

Optionally, if there is a global element in the second AST, then the AST decompilation module also needs to output a common HDL file that includes the global element and one or more of the set of HDL files for all sub-designs can reference the file.

It should be appreciated that if modules not belonging to the sub-design are instantiated within the sub-design, then a copy of the forward declaration of those instantiated modules needs to be output simultaneously for black box schema compilation.

It should be appreciated that if the originally designed module specifies instantiation parameters at instantiation, then after conversion to AST, these parameters are replaced by actual values, so that in the split sub-designs these parameters are replaced by actual values as well, and at the same time the generated code of the involved generation block etc. is expanded.

It should be appreciated that the contents of the decompiled output HDL file need to be kept in a certain indentation and line feed for debugging.

It should be appreciated that reference is made to the relevant descriptions referred to in the sections of FIGS. 7-12 below with respect to obtaining a common HDL file and M groups of HDL files independent of each other through decompilation.

It should be understood that the rewriting of the first AST mainly refers to sequentially accessing each AST node on the first AST, and if there is a node accessed by XMR, the XMR access of the node is rewritten into a port access, and corresponding ports are added to all the modules involved. The following describes the first AST rewrite flow 400 in detail with reference to fig. 4. As shown in fig. 4, the flow 400 mainly includes steps S410 to S490, and these steps are described below.

S410, it is determined whether the next node is available on the first AST.

In the process of sequentially accessing the nodes on the first AST, when the current node is accessed, whether the next node can be obtained is judged. If the next node is available, continuing to execute step S420 for the next node; if the next node is not available, meaning that the current node is already the last node on the first AST, step S490 is performed ending the access.

S420, judging whether the node has XMR access.

If the node does not have XMR access, returning to step S410, and continuing to access the next node; if there is XMR access for the node, steps S430 to S480 are continued.

S430, obtaining the node (namely the second node) referenced by the node (namely the first node).

S440, obtaining the modules crossed on the paths from the node to the referenced node.

S450, adding ports to all modules crossing on the path.

S460, modifying XMR access into port access.

S470, the smallest common parent node between the node and the referenced node is obtained.

And S480, adding local variables on the smallest public parent node, and completing functional port connection.

S490, the access is ended.

For ease of understanding, the following description will exemplarily describe the overwriting of XMR access to port access in conjunction with fig. 5 and 6. It should be understood that the presentation forms and contents of the first AST and the second AST in fig. 5 and 6 are merely examples, and do not constitute limitations of the present application.

Fig. 5 is an exemplary diagram for rewriting XMR access into port access provided in an embodiment of the present application. Fig. 5 (a) is an example diagram of a first AST, fig. 5 (b) is an example diagram of an equivalent flying trace of XMR access in the first AST, and fig. 5 (c) is an example diagram of a rewritten second AST. FIG. 6 is another exemplary diagram for rewriting XMR access to port access provided by an embodiment of the present application. The first AST in fig. 6 is another presentation of (a) in fig. 5, and the second AST in fig. 6 is another presentation of (c) in fig. 5.

As shown in fig. 5 (a) and the first AST in fig. 6, in this example, the first AST includes 4 modules in total: top module, A module, B module and C module. Wherein, a A module and a C module are instantiated in the Top module, and a B module is instantiated in the A module. In the B module, the statement y=top.c.x is the XMR access node. Also, it is apparent that the node referenced by the XMR access node is x within the C module.

It is understood that XMR access may be equivalent to a fly line in an actual circuit, as shown in (b) of fig. 5. The flying lead is also called a jumper, and refers to a method for directly connecting two nodes on a printed circuit board by wires due to design defects, test purposes or other design considerations. It can be seen that the flying lead shown in fig. 5 (b) crosses three modules in total: module B, module a and module C, that is to say XMR access node to referenced node, traverse three modules altogether: module B, module a and module C.

In this embodiment, one port may be added to all modules traversed by the fly line, the XMR access of the intra-B-module statement y=top.c.x is rewritten to access the B-module port (e.g., y=top.c.x in the first AST in fig. 6 is rewritten to y=z in the second AST in fig. 6; int x in the first AST in fig. 6 is rewritten to int x in the second AST in fig. 6; assuzx=x; fig.) and the smallest common parent node (i.e., top node) of the XMR access node to the referenced node is obtained, a local variable is added on the Top node (i.e., see inter z in fig. 6), and the functional port connection is completed as shown in (c) in fig. 5 and as the second AST in fig. 6. Thus, XMR access in the first AST is eliminated, and preconditions are created for parallel compiling.

The workflow of the AST decompilation module is exemplarily described below in connection with fig. 7. As shown in FIG. 7, a second AST completing XMR rewrite is split into a plurality of sub-designs, and all of the elements accessible to the sub-designs, such as global functions, tasks, structures, interfaces, etc., are decompiled into a common HDL file that may be referenced by one or more of the plurality of sub-designs. And then decompiling each sub-design in turn and outputting the decompiled sub-designs into independent HDL file groups. It should be appreciated that if modules not belonging to the sub-design are instantiated within the sub-design, then a forward declaration of these instantiated modules is also required to be included in the decompiled HDL file set for black box mode compilation.

For ease of understanding, the particular form of HDL files of a common element and HDL files corresponding to multiple sub-designs (it being understood that in this example, the decompilation of a sub-design to produce an HDL file is described in the example) of the design of FIG. 8 as output after splitting and decompilation is described below in connection with FIGS. 8 through 12. It should be understood that HDL files corresponding to the multiple sub-designs are independent of each other and can be compiled independently. It should be understood that the design shown in fig. 8 is merely an example and is not limiting of the embodiments of the present application.

FIG. 8 is a diagram of an exemplary design without XMR access provided by an embodiment of the present application. It should be understood that the design without XMR access may refer to the original design without XMR access, or may refer to a design that eliminates XMR access in the original design (i.e., a rewritten design). As shown in fig. 8, the design includes 2 modules in total: the top module is a top module, and 2 add modules are instantiated by designating different parameters (8 and 16) in the top module. It should be appreciated that the add module is a simple add module that can implement an add operation by invoking the global function add_f.

FIG. 9 is an exemplary diagram of a common HDL file output based on the design shown in FIG. 8. As shown in FIG. 9, in this embodiment, global function add_f is included in the common HDL file.

FIG. 10 is an exemplary diagram of HDL files for sub-design 1 based on the design output shown in FIG. 8. As shown in FIG. 10, the sub-design contains only the top module, and further because two module add and module __ prefx_add that do not belong to the sub-design are instantiated within the top module, the HDL file of sub-design 1 also contains a forward declaration file (i.e., the// top_bb.v portion of FIG. 10) for these 2 modules that includes the inputs and outputs of module add and module __ prefx_add for EDA back-end black box mode compilation.

In the design shown in fig. 8, add0 and add1 in the top module each specify an instantiation parameter at the time of instantiation, but in the top module in the sub-design 1 shown in fig. 10, add0 and add1 are each directly instantiated with actual values at the time of instantiation.

FIG. 11 is an exemplary diagram of HDL files for sub-design 2 based on the design output shown in FIG. 8. As shown in FIG. 11, the sub-design contains the contents of the add module in the design shown in FIG. 8, and specifies a value of 8 for the module parameter LENGTH to instantiate the add0 instance in sub-design 1.

FIG. 12 is an exemplary diagram of HDL files for sub-design 3 based on the design output shown in FIG. 8. As shown in FIG. 12, similar to sub-design 2, this sub-design also contains the contents of the add module in the design shown in FIG. 8, but unlike sub-design 2, a value of 16 for the module parameter LENGTH is specified for instantiating the add1 instance in sub-design 1.

It should be understood that the global function add_f is referenced in each of the sub-designs 1 to 3 in this example, but it should be understood that the global function add_f may not be referenced in the actual sub-design 1, and is not limited thereto.

According to fig. 9 to 12, it can be seen that the design shown in fig. 8 is split and outputs 3 HDL files corresponding to 3 sub designs and one HDL file of a common element, where the HDL files of the sub designs are independent of each other and can be compiled in parallel, so that the compiling efficiency can be improved. And, the compiling results of the 3 sub-designs are combined, so that the compiling result of the design shown in fig. 8 can be obtained.

FIG. 13 is a front-end solution for HDL parallel compilation provided by embodiments of the present application. As shown in fig. 13, the apparatus 1300 includes a processing module 1310, where the processing module 1310 is configured to obtain, according to an original design, a first AST equivalent to the original design; obtaining M sub designs according to the first AST; obtaining M HDL file groups corresponding to the M sub designs one by one according to the M sub designs, wherein the M HDL file groups are independent of each other, each HDL file group in the M HDL file groups comprises one or more HDL files, the M HDL file groups correspond to K compilers, each compiler is used for compiling the corresponding one or more HDL file groups, M is a positive integer greater than or equal to 2, K is a positive integer greater than or equal to 1 and less than or equal to M

Optionally, if there is a first node accessed by XMR in the plurality of nodes of the first AST, the processing module 1310 may be further configured to rewrite the first AST to obtain a second AST, where the second AST does not have XMR access; m sub-designs are obtained according to the second AST.

Optionally, the processing module 1310 may be further configured to obtain a second node referenced by the first node; obtaining a module spanned on a path from a first node to a second node; adding ports to modules spanned on the path; rewriting XMR access of the first node into port access; obtaining the smallest public father node from the first node to the second node; and adding local variables on the smallest public father node, and completing functional port connection.

Optionally, if a first sub-design of the M sub-designs instantiates a module that does not belong to the first sub-design, the processing module 1310 may be further configured to create a forward declaration of the instantiated module based on the inputs and outputs of the instantiated module in the first sub-design; and obtaining the HDL file group corresponding to the first sub-design according to the first sub-design and the forward declaration of the instantiated module in the first sub-design.

Alternatively, if a global element is included in the first AST, processing module 1310 may be further configured to obtain, according to the first AST, a common HDL file, where the common HDL file includes the global element, and one or more of the M HDL file groups respectively reference the common HDL file.

Optionally, the global elements may include one or more of global structures, global tasks, global interfaces, global functions, and the like.

Alternatively, if the originally designed module specifies the instantiation parameters at instantiation, the M sub-designed modules may take the actual values instead of the instantiation parameters at instantiation.

Alternatively, each HDL file in the M HDL file groups may be in a target format including target indentation and linefeed.

FIG. 14 is an exemplary block diagram of a hardware architecture of a front-end solution for HDL parallel compilation provided in an embodiment of the present application. Alternatively, the apparatus 1400 may be a computer device in particular. The apparatus 1400 includes a memory 1410, a processor 1420, a communication interface 1430, and a bus 1440. Wherein the memory 1410, the processor 1420, and the communication interface 1430 implement communication connection therebetween through a bus 1440.

The Memory 1410 may be a Read-Only Memory (ROM), a static storage device, a dynamic storage device, or a random access Memory (Random Access Memory, RAM). The memory 1410 may store a program, and the processor 1420 is configured to perform various steps of the front-end solution of the embodiment of the present application when the program stored in the memory 1410 is executed by the processor 1420.

The processor 1420 may employ a general-purpose central processing unit (Central Processing Unit, CPU), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), graphics processor (Ggraphics Processing Unit, GPU) or one or more integrated circuits for executing associated programs to implement the front-end solutions of the method embodiments of the present application.

Processor 1420 may also be an integrated circuit chip with signal processing capabilities. In implementation, the front-end solutions of the present application may be implemented by integrated logic circuitry of hardware in processor 1420 or instructions in the form of software.

The processor 1420 may also be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an ASIC, an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 1410, and the processor 1420 reads the information in the memory 1410, and in combination with its hardware, performs functions required to be performed by the modules included in the apparatus of the embodiments of the present application, or performs the front-end solutions of the embodiments of the methods of the present application.

Communication interface 1430 enables communication between apparatus 1400 and other devices or communication networks using transceiving apparatus such as, but not limited to, transceivers.

Bus 1440 may include a path for transferring information between components of device 1400 (e.g., memory 1410, processor 1420, communication interface 1430).

Embodiments of the present application also provide a computer readable storage medium storing computer instructions that, when executed on a computer, implement the front-end solution described above.

The embodiment of the application also provides a computer program product, which is characterized by comprising: a computer program which, when run, causes a computer to perform the front-end solution described above.

The embodiment of the application also provides a computing device, which comprises: at least one processor and a memory, the at least one processor coupled with the memory, for reading and executing instructions in the memory to perform the front-end solution described above.

The embodiment of the application also provides a chip, which comprises a processor and a data interface, wherein the processor reads instructions stored in a memory through the data interface, and the front-end solution is executed.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A front-end solution for parallel compilation of hardware description language, HDL, comprising:

obtaining a first abstract syntax tree AST equivalent to the original design according to the original design;

obtaining M sub-designs according to the first AST;

m HDL file groups corresponding to the M sub designs one by one are obtained according to the M sub designs, the M HDL file groups are independent of each other, each HDL file group in the M HDL file groups comprises one or more HDL files, the M HDL file groups correspond to K compilers, each compiler is used for compiling the corresponding one or more HDL file groups, M is a positive integer greater than or equal to 2, and K is a positive integer greater than or equal to 1 and less than or equal to M.

2. The front-end solution of claim 1, wherein the first AST comprises a plurality of nodes, there being a first node of the plurality of nodes accessed across module references XMR, the deriving M sub-designs from the first AST comprising:

rewriting the first AST to obtain a second AST, wherein the second AST does not have XMR access;

and obtaining the M sub-designs according to the second AST.

3. The front-end solution of claim 2, wherein the overwriting the first AST comprises:

obtaining a second node referenced by the first node;

obtaining a module spanned on a path from the first node to the second node;

adding ports to all modules spanned on the path;

rewriting XMR access of the first node into port access;

obtaining a minimum common parent node from the first node to the second node;

and adding local variables on the smallest public father node, and completing functional port connection.

4. The front-end solution according to any one of claims 1 to 3, wherein a first sub-design of the M sub-designs instantiates a module not belonging to the first sub-design, and wherein obtaining M HDL file groups in one-to-one correspondence with the M sub-designs from the M sub-designs comprises:

creating a forward declaration of an instantiated module in the first sub-design based on the input and output of the instantiated module;

and obtaining the HDL file group corresponding to the first sub-design according to the first sub-design and the forward declaration of the instantiated module in the first sub-design.

5. The front-end solution according to any of claims 1 to 4, wherein a global element is included in the first AST, the method further comprising:

and obtaining a common HDL file according to the first AST, wherein the common HDL file comprises a global element, and one or more of the M HDL file groups refer to the common HDL file.

6. The front-end solution of claim 5, wherein the global elements comprise one or more of global structures, global tasks, global interfaces, global functions.

7. The front-end solution according to any of claims 1 to 6, characterized in that if the originally designed module specifies an instantiation parameter at instantiation, the M sub-designed modules take the actual value instead of the instantiation parameter at instantiation.

8. The front-end solution according to any one of claims 1 to 7, wherein each HDL file in the M groups of HDL files is in a target format, the target format comprising target indentation and linefeed.

9. Front-end solution for parallel compilation of hardware description language HDL, characterized by comprising means for performing the front-end solution according to any one of claims 1 to 8.

10. Front-end solution for parallel compilation of hardware description language HDL, characterized by comprising at least one processor for coupling with a memory, reading and executing instructions in said memory to implement the front-end solution according to any one of claims 1 to 8.

11. A computer readable storage medium storing computer instructions which, when run on a computer, implement the front-end solution of any one of claims 1 to 8.