CN117270625A - Optical digital multiplier with expandable bit width - Google Patents
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Abstract
The invention discloses an optical digital multiplier with expandable bit width, and belongs to the field of optical logic calculation. Includes a partial product generation and accumulation region and a binarization region. The partial product generation and accumulation area is used to generate and mix-accumulate the partial products corresponding to the two multipliers. The binarization area is used for converting part of accumulated addition signals from decimal signals to binary signals, feeding back high-order output after bit delay to the mixed signals to realize the transmission of carry signals, and the lowest-order output is used as the result of multiplication operation. The above structures are combined to realize an optical digital multiplier with expandable bit width. According to the invention, the information of the two multipliers is respectively loaded to two dimensions of time and space, so that the number of hardware required by the multipliers is in a linear relation with the bit width of the multipliers, and the expansibility of the photon multipliers is greatly improved. In addition, the multiplier architecture of the invention supports silicon-based integration and can realize a logic photon operation circuit on a large-scale die.
Description
Technical Field
The invention belongs to the field of optical logic computation, and particularly relates to an optical digital multiplier with expandable bit width.
Background
In the context of the rapid growth of the artificial intelligence and communications industries, the demand for computing resources has increased dramatically. Because of the natural limitations of electronics in terms of signal transmission speed, parallel processing capability, and energy consumption, conventional electronic hardware has not met significant computational demands. While light has the fastest signal transmission speed in physical space, multiple dimensions that can be multiplexed (wavelength, mode and polarization) and lower energy consumption, which makes photonic computing a very promising electrical alternative.
Photon computing can be divided into two areas: photon analog computation and digital computation. While photon simulation computing has made a remarkable breakthrough, problems remain in high-precision computing scenarios. The analog nature and noise in the optical link and surrounding environment cause relatively inaccurate calculation results, severely affecting calculation performance and efficiency. In contrast, photon-digital computing has higher noise tolerance and is compatible with common electronic computer architectures. However, most existing works only support some simple logic functions such as AND, XOR operations, one or two bit adders, comparators AND multipliers, etc. The limitations of optical nonlinear functions and the inevitable power consumption pose a significant challenge for performing large-scale digital calculations, such as additions and multiplications. While a practical way to implement a scalable adder has been recently proposed by scholars, the large bit-width computing architecture remains blank for multipliers.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an optical digital multiplier with expandable bit width, which aims to realize expandable large bit width optical digital multiplication operation.
To achieve the above object, the present invention provides an optical digital multiplier with expandable bit width, comprising a partial product generation and accumulation region and a binarization region, wherein the partial product generation and accumulation region has optical input of n wavelengths corresponding to continuous light, and the electrical input is two binary multipliers (a=a n …A 2 A 1 ，B＝B n …B 2 B 1 ) Outputting a mixed signal which is obtained by accumulating partial products corresponding to the two multipliers; the input of the binarization area is the mixed signal of the partial product generation and the accumulation area output, and the output is the multiplication result.
Preferably, the partial product generation and accumulation region is used to generate and mixedly accumulate partial products corresponding to two multipliers in the multiplier. The binarization area is used for converting the mixed signal after the partial product generation and the partial product accumulation generated by the accumulation area into a binary signal by a decimal signal, feeding back the high-order output to the mixed signal after bit delay to realize the transmission of a carry signal, and the lowest-order output is used as the result of multiplication operation.
Further, the partial product generating and accumulating region comprises a multi-wavelength laser source, n+1 intensity modulators, two wavelength division multiplexers and n-1 delay lines, wherein the multi-wavelength laser source is used for generating n wavelengths and respectively inputting the n wavelengths to the intensity modulators for loading A signals, the intensity modulators for loading A signals are used for loading multiplier A signals on the n wavelengths output by the multi-wavelength laser source in a time sequence form, the output is divided into n paths (corresponding to the n wavelengths) by a first wavelength division multiplexer and is input into subsequent intensity modulators, and the n intensity modulators for loading B signals are respectively used for loading B in multiplier B signals 1 ，B 2 ，B 3 ，…，B n Since two intensity modulators in series can perform a logical AND function, the outputs of the n intensity modulators loading the B signal are B in the multiplier B signal, respectively 1 ，B 2 ，B 3 ，…，B n And the n-1 delay lines are used for delaying the generated partial product according to bits to realize carry on time sequence, and the output result is input to a second wavelength division multiplexer so as to realize mixed superposition of the partial product signals.
Further, the binarization area comprises m delay lines, an m+1- & gt 1 beam combiner and a binary converter, wherein the binary converter is used for converting an input signal from a decimal signal to a binary signal, the m delay lines are used for delaying the high-order output of the binary converter according to bits so as to realize the transmission of a carry signal, and the m+1- & gt 1 beam combiner is used for mixing and accumulating the carry signal output by the m delay lines and a partial product accumulation signal output by the partial product generation and accumulation area, so that the feedback of the carry signal is realized, and the carry signal is input into the binary converter. By the mode, accumulation summation of the partial product signals under a binary system can be realized, and the lowest bit of the binary converter outputs the operation result of the multiplier.
Further, the multiplier a signal and the multiplier B signal are loaded into the optical domain in a temporal and spatial form, respectively, and generate corresponding partial product results. The information of the two multipliers is respectively loaded to two dimensions of time and space, so that the number of hardware needed by the multipliers is in linear relation with the bit width of the multipliers, and the expansibility of the photon multipliers is greatly improved.
Further, the system converter can be realized by an all-optical scheme or an optical-electrical-optical two scheme, the all-optical scheme can be obtained by combining an optical linear matrix with an optical nonlinear material to form an optical neural network and training, the optical-electrical scheme can be realized by driving an electrically tunable micro-ring resonance peak to move to a designated wavelength position and introducing an optical signal with a corresponding wavelength after an optical detector is used for converting an optical signal into an electrical signal, or can be directly input into an electrical ADC (analog-to-digital converter), and an intensity modulator is driven by a quantized electrical signal result to realize the system conversion function of an optical domain.
Further, the advance number m of the binary converter and the bit width n of the multiplier need to satisfy: n+1 is less than or equal to 2 m+1 -m。
Further, the delays of the n-1 delay lines are respectively tau, 2 tau and …, (n-1) tau, and the delays of the m delay lines are respectively tau, and tau corresponds to the code length of one code element of the multiplier signal.
Further, the multi-wavelength laser source is an optical frequency comb, or is realized by combining laser beams with different wavelengths output by a multi-path laser.
In view of the great difficulty of directly realizing the m-bit wide binary converter, a step-by-step accumulation mode can also be adopted, and the n-bit wide multiplier is realized by using n-1 binary converters with 2bit widths in cascade connection. The invention also provides an optical digital multiplier with expandable bit width, which comprises 1 multi-wavelength laser source, n+1 intensity modulators, a wavelength division multiplexer, 2 (n-1) delay lines, 2 (n-1) 2- & gt 1 couplers and (n-1) 2bit system converters, wherein the multi-wavelength laser source is used for generatingGenerating n wavelengths and inputting the n wavelengths to an intensity modulator for loading multiplier A signals in a time sequence form on the n wavelengths, dividing the n wavelengths into corresponding n paths by a wavelength division multiplexer and inputting the n paths into B signals of the multiplier B 1 ，B 2 ，B 3 ，…，B n Other n intensity modulators of (a) output B 1 ，B 2 ，B 3 ，…，B n Partial product with multiplier A signal, n-1 delay lines are used for bit delay of the generated partial product to realize carry in time sequence, B 1 And B 2 The corresponding partial product results are combined by the 2-1 coupler to obtain a mixed signal of two partial products, and then the mixed signal is input into the 2bit system converter, and the high order C 1 The output of the (B) is delayed by tau through the delay line, namely after one bit is advanced in time sequence, the 2-to-1 coupler is combined with the mixed signals of the two partial products to realize the transmission of carry signals, thereby completing the binary addition of the partial product results corresponding to B1 and B2, and the output result is then combined with B 3 Binary addition is carried out on the corresponding partial product results, and the like, so that the binary addition of all partial products is finally completed, and the lowest bit C of the n-1 2bit binary converter is obtained 0 And outputting the final result of the multiplier operation, thereby realizing an n-bit digital multiplier.
Furthermore, the delays of the (n-1) delay lines are respectively tau, 2 tau and …, (n-1) tau, and the delays of the (n-1) delay lines are respectively tau, wherein tau corresponds to the code length of one code element of the multiplier signal.
Further, the intensity modulator is a Mach-Zehnder modulator or an electric micro-ring, and the delay line is a spiral waveguide.
Furthermore, all devices involved in the multiplier support the existing mature silicon photofabrication process, can realize a logic photon operation circuit on a large-scale die, and has the potential of commercial application.
By the above technical scheme, compared with the prior art, the invention can obtain the following
The beneficial effects are that:
1. the optical digital multiplier with expandable bit width provided by the invention loads two multipliers to time dimension and space dimension respectively, realizes delay carry in the time dimension and realizes a photon multiplier with large bit width.
2. The optical digital multiplier with expandable bit width provided by the invention has low loss compared with the traditional electric multiplication operation because most operation processes are carried out in an optical domain.
3. The optical digital multiplier with expandable bit width has extremely strong expansibility due to the linear relation between the number of devices and the bit width of the multiplier.
4. All devices related to the optical digital multiplier with expandable bit width provided by the invention support the existing mature silicon photofabrication technology, can realize a logic photon operation circuit on a large-scale die, and has the potential of commercial application.
Drawings
FIG. 1 is a schematic diagram of a system architecture of an optical digital multiplier with a scalable bit width according to the present invention.
FIG. 2 is a schematic diagram of the operation of a 4bit width multiplier in an optical digital multiplier with a scalable bit width.
FIG. 3 is a graph of experimental results related to an optical digital multiplier with expandable bit width.
Fig. 4 is an all-optical implementation of a binary converter in an optical digital multiplier with a scalable bit width provided by the present invention.
Fig. 5 is an optoelectronic implementation of a binary converter in an optical digital multiplier with a scalable bit width provided by the present invention.
FIG. 6 is a schematic diagram of progressive accumulation in an optical digital multiplier with a scalable bit width according to the present invention.
Fig. 7 is a schematic diagram of an optical structure based on a progressive accumulation principle in an optical digital multiplier with expandable bit width according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not interfere with each other.
As shown in fig. 1, an optical digital multiplier with expandable bit width according to an embodiment of the present invention includes a partial product generation and accumulation area 1 and a binarization area 2. In the partial product generation and accumulation region 1, the multi-wavelength laser source 11 is used for generating n wavelengths and respectively inputting the n wavelengths to the intensity modulators 12 for loading A signals, the intensity modulators 12 for loading A signals are used for loading multiplier A signals on n wavelengths output by the multi-wavelength laser source in a time sequence form, the output is divided into n paths (corresponding to n wavelengths) by the first wavelength division multiplexer 131 and is input to the subsequent intensity modulators, and the n intensity modulators 141, 142, 143, … and 14n for loading B signals are respectively used for loading B in multiplier B signals 1 ，B 2 ，B 3 ，…，B n Since two intensity modulators in series can perform a logical AND function, the outputs of the intensity modulators 141, 142, 143, …,14n are B in the multiplier B signal, respectively 1 ，B 2 ，B 3 ，…，B n The n-1 delay lines 151, 152, 15 (n-1) are used for bit-delaying the generated partial product result to realize carry on time sequence, and the output result is input to the second wavelength division multiplexer 132 to realize mixed superposition of the partial product signals. The mixed signal is then input to the binarization section 2. Wherein the binary converter 23 is used for converting an input signal from a decimal signal to a binary signal, the delay lines 211, 212, …,21m are used for delaying the high-order output of the binary converter 23 by bits so as to realize the transmission of a carry signal, the m+1- & gt 1 beam combiner 22 is used for mixing and accumulating the carry signal output by the m delay lines 211, 212, …,21m and the partial product accumulated signal output by the accumulation area 1 to realize the feedback of the carry signal, and inputting the feedback of the carry signal into the binary converter 23, and the method is implemented byAn accumulated sum of the partial product signal under a binary system can be realized, and the lowest order of the binary converter 23 is the operation result of the output multiplier. Fig. 2 shows a schematic diagram of the operation of a 4bit wide multiplier, as shown in (a), where two serially connected intensity modulators may form a logic and gate. Only when A i ，B j When all of them are 1, the light output is 1, and the output level is 0. FIG. 2 (B) shows the partial product distribution in both the temporal and spatial dimensions, due to the delay line of FIG. 1, associated with B 2 ，B 3 ，…，B n The relevant sections are delayed by 1, 2, …, (n-1) τ, respectively, where τ corresponds to the code length of one symbol of the multiplier signal. The generation of carry of the partial product signal is realized in a delayed manner in the partial product generation and accumulation area 1. Fig. 2 (c) shows a process of accumulating and summing the partial product signals in binary form in the accumulation area. It can be seen that the mixed signal is output as the multiplication result by the least significant bit after being input into the binary conversion device, and the high order output is delayed by the bit to realize the transmission of the carry signal. By the method, the whole binary multiplication operation process is completed. Fig. 3 shows experimental results of 32bit binary numbers and the binary numbers 11,101,1001, respectively, which completely coincide with theoretical calculation results.
Fig. 4 shows a pure optical implementation of the binary conversion device, where the binary conversion function is implemented by forming an optical neural network by combining an optical linear matrix with an optical nonlinear material and training to obtain a specified target output. Fig. 5 shows an implementation manner of an optoelectronic 2bit system converter, firstly, an optical signal detector 91 is used for converting an input optical signal into an electrical signal, then the electrical signal is used for driving electrically tunable micro-rings 92 and 93 to enable the positions of resonance peaks to move, and continuous light at a specified wavelength position is input to control the output of a corresponding signal. As shown in (c), there are 4 different levels of inputs to the 2bit binary converter. For electrically tunable micro-ring 92, its target output is C 1 Bit, then input is lambda as shown in (b) of the figure 3 、λ 4 Only when the levels are 2 and 3, there is a light output corresponding to binary 10 and 11, and likewise, the target output for the electrically tunable ring 92 is C 1 Bit, then input is lambda as shown in (d) of the figure 2 、λ 4 When the levels are 1 and 3, there is an optical output at the download end of the micro-ring, corresponding to binary 01 and 11.
In view of the great difficulty of directly realizing the m-bit wide binary converter, the binary summation of all partial products can be realized by carrying out the two-by-two summation n-1 times in a step-by-step accumulation mode as shown in fig. 6. In this way, an n-bit wide multiplier can be implemented using only n-1 2-bit wide binary converters. The specific on-chip implementation scheme is shown in fig. 7, and the first half structure is unchanged from the original architecture. In a silicon-based chip, the intensity modulator 41 may be implemented as a mach-zehnder modulator, the intensity modulators 42, 43, 44, …,4 (n+1) as mach-zehnder modulators or as electrically tunable micro-rings, and the delay line may be implemented as a helical waveguide. The multiplier B, B 1 And B 2 The corresponding partial product results are combined by the 2-to-1 coupler 711 to obtain a mixed signal of two partial products, and then input to the 2-bit system converter 81, high-order C 1 The output of the (B) is delayed by tau through the delay line 521, namely, after one bit is advanced in time sequence, the mixed signal of the two partial products is combined through the 2-to-1 coupler 721 to realize the transmission of a carry signal, and the output result is then combined with B 3 And (3) binary addition is carried out on the corresponding partial product results, and the binary addition of all partial products is finally completed by analogy. In this way, an n-bit wide digital multiplier can also be implemented.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. An optical digital multiplier with expandable bit width is characterized by comprising a partial product generation and accumulation area (1) and a binary valueA dividing section (2), the partial product generating and accumulating section (1) comprises a multi-wavelength laser source (11), n+1 intensity modulators (12, 141, 142, 143, … n), two wavelength division multiplexers (131, 132), n-1 delay lines (151, 152, 15 (n-1)), the multi-wavelength laser source (11) is used for generating n wavelengths and inputting the n wavelengths to the intensity modulator (12), the intensity modulator (12) is used for loading multiplier A signals onto the n wavelengths in a time sequence form, and dividing B signals which are input into corresponding n paths of loading multiplier B signals through the first wavelength division multiplexer (131) 1 ，B 2 ，B 3 ，…，B n N intensity modulators (141, 142, 143, …,14 n) of (B) output B 1 ，B 2 ，B 3 ，…，B n The n-1 delay lines (151, 152, 15 (n-1)) are used for bit delay of the generated partial product to realize carry on time sequence, and finally the carry is input to the second wavelength division multiplexer (132) to realize mixed superposition of the partial product signals;
the binarization area (2) comprises m delay lines (211, 212, …,21 m), m+1- > 1 beam combiners (22), a binary converter (23), the binary converter (23) being used for converting an input signal from a decimal signal to a binary signal, the delay lines (211, 212, …,21 m) being used for converting the high order bits (C) of the binary converter (23) m ，…，C 2 ，C 1 ) The output is delayed according to the bit, thereby realizing the transmission of a carry signal, the m+1- & gt 1 combiner (22) is used for carrying out mixed accumulation on the carry signal output by the m delay lines (211, 212, …,21 m) and the mixed superposition signal output by the partial product generation and accumulation area (1), realizing the feedback of the carry signal and inputting the feedback into the binary converter (23), and the lowest bit C of the binary converter (23) 0 I.e. the result of the operation of the multiplier is output.
2. An optical digital multiplier with expandable bit width according to claim 1, characterized in that said partial product generates continuous light corresponding to n wavelengths of light input to the accumulation zone (1), the electrical input being the two binary multipliers a=a of the multiplier n …A 2 A 1 ，B＝B n …B 2 B 1 Outputting a mixed signal which is obtained by accumulating partial products corresponding to the two multipliers; the input of the binarization area (2) is the mixed signal generated by the partial product and output of the accumulation area (1), and the output is the multiplication result;
the partial product generating and accumulating area (1) is used for generating and mixedly accumulating partial products corresponding to two multipliers in the multiplier, the binarization area (2) is used for converting a partial product accumulating signal generated by the partial product generating and accumulating area (1) from a decimal signal into a binary signal, and outputting high-order bits (C m ，…，C 2 ，C 1 ) After bit delay, feeding back to the mixed signal to realize the transmission of carry signal, and outputting C at the lowest bit 0 As a result of the multiplication operation.
3. An optical digital multiplier with expandable bit width according to claim 1, characterized in that the advance number m of the binary converter (23) and the bit width n of the multiplier are such that: n+1 is less than or equal to 2 m+1 -m。
4. The scalable bit-width optical digital multiplier of claim 1, wherein the n-1 delay lines (151, 152, …,15 (n-1)) have respective delays τ,2τ, …, (n-1) τ, and the m delay lines (211, 212, …,21 m) have respective delays τ, τ corresponding to the code length of one symbol of the multiplier signal.
5. The bit-width-expandable optical digital multiplier according to claim 1, wherein the multi-wavelength laser source (11) is an optical frequency comb or is realized by combining laser beams with different wavelengths output by a multi-path laser.
6. An optical digital multiplier with expandable bit width, characterized by comprising 1 multi-wavelength laser source (31), n+1 intensity modulators (41, 42, 43, 44, …,4 (n+1)), wavelength division multiplexer (5), 2 (n-1) delay lines (611, 612, …,61 (n-1), 621, 622, …,62 (n-1)), 2 (n-1) 2- > 1 couplers (711, 712, …,71 (n-1), 721,722, …,72 (n-1)), (n-1) 2bit binary converters (81, 82,8 (n-1)), the multi-wavelength laser source (31) for generating n wavelengths and inputting to an intensity modulator (41), the intensity modulator (41) for loading the multiplier a signal onto n wavelengths in time series, dividing by a wavelength division multiplexer (5) into corresponding n paths of B input into the loaded multiplier B signal 1 ，B 2 ，B 3 ，…，B n N intensity modulators (42, 43, 44, …,4 n) outputting B 1 ，B 2 ，B 3 ，…，B n Partial product of multiplier A signal, n-1 delay lines (611, 612, 61 (n-1)) are used for bit delay of the generated partial product to realize carry in time sequence, B 1 And B 2 The corresponding partial product results are combined by the 2-to-1 coupler (711) to obtain a mixed signal of two partial products, and then the mixed signal is input to the 2-bit system converter (81), and the high order C 1 The output of the (B) is delayed by tau through the delay line (521), namely, after one bit is advanced in time sequence, the mixed signal of two partial products is combined through the 2-to-1 coupler (721) to realize the transmission of a carry signal, thereby completing the binary addition of the partial product results corresponding to B1 and B2, and the output result is then combined with B 3 Binary addition is carried out on the corresponding partial product results, and the like, so that the binary addition of all partial products is finally completed, and the lowest bit C of the n-1 th 2-bit binary converter 8 (n-1) 0 And outputting the final result of the multiplier operation, thereby realizing an n-bit digital multiplier.
7. The scalable bit-width optical digital multiplier of claim 6, wherein the (n-1) delay lines (611, 612, …,61 (n-1)) have respective delays τ,2τ, …, (n-1) τ, and the (n-1) delay lines (621, 622, …,62 (n-1)) have respective delays τ corresponding to a code length of one symbol of the multiplier signal.
8. The scalable bit-width optical digital multiplier of claim 6, wherein the intensity modulator (41) is a mach-zehnder modulator, the intensity modulator (42, 43, 44, …,4 (n+1)) is a mach-zehnder modulator or an electrical micro-ring, and the delay line (611, 612, …,61 (n-1), 621, 622, …,62 (n-1)) is a helical waveguide.
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