CN117270625A - Optical digital multiplier with expandable bit width - Google Patents

Abstract

The invention discloses an optical digital multiplier with expandable bit width, belonging to the field of optical logic computing. Including partial product generation and accumulation area and binarization area. The partial product generation and accumulation area is used to generate partial products corresponding to two multipliers and mix and accumulate them. The binarization area is used to convert part of the accumulated addition signal from a decimal signal to a binary signal. The high-bit output is delayed by bits and fed back to the mixed signal to realize the transmission of the carry signal. The lowest-bit output is used as the result of the multiplication operation. The above structures are combined to realize an optical digital multiplier with scalable bit width. By loading the information of the two multipliers into the two dimensions of time and space respectively, the present invention makes the number of hardware required for the multiplier have a linear relationship with the multiplier bit width, which greatly improves the scalability of the photon multiplier. In addition, the multiplier architecture involved in the present invention supports silicon-based integration and can realize large-scale on-chip logical photonic computing circuits.

Description

A bit-width scalable optical digital multiplier

Technical field

The present invention belongs to the field of optical logic computing, and more specifically, relates to an optical digital multiplier with expandable bit width.

Background technique

Against the backdrop of rapid growth in the artificial intelligence and communications industries, the demand for computing resources has increased dramatically. Due to the natural limitations of electronics in terms of signal transmission speed, parallel processing capabilities and energy consumption, traditional electronic hardware can no longer meet the huge demand for computing power. Light has the fastest signal transmission speed in physical space, multiple reusable dimensions (wavelengths, modes and polarizations) and low energy consumption, which makes photonic computing a promising electrical alternative.

Photon computing can be divided into two areas: photon analog computing and digital computing. Although photon simulation computing has made impressive breakthroughs, there are still many problems faced in high-precision computing scenarios. Its analog characteristics and the noise in the optical link and surrounding environment lead to relatively inaccurate calculation results, seriously affecting computing performance and efficiency. In contrast, photonic digital computing has higher noise tolerance and is compatible with common electronic computer architectures. However, most existing works can only support some simple logic functions, such as AND, XOR operations, one- or two-bit adders, comparators, and multipliers, etc. The limitations of optical nonlinear capabilities and the unavoidable power consumption pose a huge challenge to perform large-scale numerical calculations, such as addition and multiplication. Although some scholars have recently proposed a feasible method to implement scalable adders, for multipliers, a large bit-width computing architecture is still blank.

Contents of the invention

In view of the shortcomings of the existing technology, the purpose of the present invention is to provide an optical digital multiplier with scalable bit width, aiming to realize scalable large bit-width optical digital multiplication operations.

In order to achieve the above object, the present invention provides an optical digital multiplier with scalable bit width, including a partial product generation and accumulation area and a binarization area. The light input of the partial product generation and accumulation area corresponds to n wavelengths. Continuous light, the electrical input is the two binary multipliers of the multiplier (A=A _n ...A ₂ A ₁ , B=B _n ...B ₂ B ₁ ), and the output is the cumulative addition of the parts corresponding to the two multipliers. Mixed signal; the input to the binarization area is the mixed signal generated by the partial product and the output of the accumulation area, and the output is the result of the multiplication operation.

Preferably, the partial product generation and accumulation area is used to generate partial products corresponding to two multipliers in the multiplier and mix and accumulate them. The binarization area is used to convert the mixed signal after partial accumulation and addition generated by the partial product generation and accumulation area from a decimal signal into a binary signal. The high-bit output is delayed by bits and fed back to the mixed signal to realize the transmission of the carry signal. The lowest bit The output is the result of the multiplication operation.

Further, the partial product generation and accumulation area includes a multi-wavelength laser source, n+1 intensity modulators, two wavelength division multiplexers, and n-1 delay lines. The multi-wavelength laser source is used for n wavelengths are generated and respectively input to the intensity modulator for loading the A signal. The intensity modulator for loading the A signal is used to load the multiplier A signal to the multi-wavelength laser source output in the form of time series. On n wavelengths, the output is divided into n channels (corresponding to n wavelengths) through the first wavelength division multiplexer and input to subsequent intensity modulators. The n intensity modulators used to load the B signal are respectively used to load the multiplier. B ₁ , B ₂ , B ₃ ,..., B _n in the B signal. Since two series-connected intensity modulators can perform logical AND functions, the outputs of the n intensity modulators loading the B signal are multipliers respectively. The partial product result of B ₁ , B ₂ , B ₃ ,..., B _n in the B signal and the multiplier A signal. The n-1 delay lines are used to delay the generated partial products bit by bit to implement timing. carry, and its output result is input to the second wavelength division multiplexer to achieve the mixed superposition of partial product signals.

Further, the binarization area includes m delay lines, m+1→1 combiners, and a binary converter. The binary converter is used to convert the input signal from a decimal signal to a binary signal, so The m delay lines are used to delay the high-bit output of the hexadecimal converter bit by bit, thereby realizing the transmission of the carry signal, and the m+1→1 combiner is used to output the m delay lines The carry signal is mixed and accumulated with the partial product generation and partial accumulation addition signal output from the accumulation area to realize feedback of the carry signal and input it into the hexadecimal converter. Through the above method, the accumulation and summation of partial product signals in the binary system can be realized, and the lowest bit of the binary converter outputs the operation result of the multiplier.

Further, the multiplier A signal and the multiplier B signal are loaded into the optical domain in the form of time and space respectively, and corresponding partial product results are generated. By loading the information of the two multipliers into the two dimensions of time and space respectively, the number of hardware required for the multiplier is linearly related to the multiplier bit width, which greatly improves the scalability of the photon multiplier.

Further, the binary converter can be realized by an all-optical scheme or an optical-electro-optical scheme. The all-optical scheme can be obtained by forming an optical neural network by combining an optical linear matrix with optical nonlinear materials and training it. The opto-electro-optical scheme can use light detection. After the optical signal is converted into an electrical signal by the device, the resonant peak of the electronically controlled microring is driven to move to the specified wavelength position, and the optical signal of the corresponding wavelength is passed in to achieve this. The electrical signal can also be directly input into the electrical ADC, and the quantized The electrical signal results drive the intensity modulator to realize the binary conversion function in the optical domain.

Further, the carry number m of the decimal converter and the bit width n of the multiplier need to satisfy: n+1≤2 ^m+1 -m.

Further, the delays of the n-1 delay lines are respectively τ, 2τ,..., (n-1)τ, the delays of the m delay lines are all τ, and τ corresponds to one symbol of the multiplier signal. code length.

Further, the multi-wavelength laser source is an optical frequency comb, or is implemented by multiple lasers outputting lasers of different wavelengths and then combining the beams.

In view of the difficulty of directly implementing an m-bit-wide hexadecimal converter, a step-by-step accumulation method can also be used to implement an n-bit-wide multiplier by using n-1 2-bit wide hexadecimal converters in cascade. . The invention also provides an optical digital multiplier with scalable bit width, including a multi-wavelength laser source, n+1 intensity modulators, a wavelength division multiplexer, 2 (n-1) delay lines, 2 (n-1) 2→1 couplers, (n-1) 2-bit binary converters, the multi-wavelength laser source is used to generate n wavelengths and input to the intensity modulator, the intensity modulator is used to Load the multiplier A signal to n wavelengths in the form of a time series, and divide it into n-channels corresponding to B ₁ , B ₂ , B ₃ ,..., B _n in the loaded multiplier B signal through the wavelength division multiplexer. The other n intensity modulators output partial products of B ₁ , B ₂ , B ₃ ,..., B _n and the multiplier A signal. The n-1 delay lines are used to delay the generated partial products bit by bit. , to realize the carry in the timing, the partial product results corresponding to B ₁ and B ₂ are first combined by the 2→1 coupler to obtain the mixed signal of the two partial products, and then input to the 2-bit hexadecimal converter, the high bit The output of C ¹ is delayed by τ through the delay line, that is, after one bit is carried forward in the timing, it is combined with the mixed signal of the two partial products through the 2→1 coupler to realize the transmission of the carry signal, thus completing the The binary addition of the partial product results corresponding to B1 and B2, the output result is then binary added to the partial product result corresponding to _B3 , and so on, and finally the binary addition of all partial products is completed, and the n-1th 2-bit addition The lowest bit C ⁰ of the system converter outputs the final result of the multiplier operation, thereby realizing an n-bit wide digital multiplier.

Further, the delays of the (n-1) delay lines are respectively τ, 2τ,..., (n-1)τ, and the delays of the (n-1) delay lines are all τ, τ. Corresponds to the code length of one symbol of the multiplier signal.

Further, the intensity modulator is a Mach-Zehnder modulator or an electrically tuned microring, and the delay line is a spiral waveguide.

Furthermore, all the devices involved in the multiplier support the existing mature silicon photonics technology, can realize large-scale on-chip logical photonic computing circuits, and have the potential for commercial application.

Through the above technical solutions conceived by the present invention, compared with the existing technology, the following can be achieved:

Beneficial effects:

1. The invention provides an optical digital multiplier with scalable bit width, which loads two multipliers into the time and space dimensions respectively, realizes delayed carry in the time dimension, and realizes a large bit-width photon multiplier.

2. The invention provides an optical digital multiplier with scalable bit width. Since most of the operation processes are performed in the optical domain, the operation loss is lower than that of traditional electrical multiplication operations.

3. The invention provides an optical digital multiplier with scalable bit width. Since the number of required devices and the bit width of the multiplier are linearly related, the photon multiplier has extremely strong scalability.

4. All the components involved in the optical digital multiplier with scalable bit width provided by the present invention support the existing mature silicon photonics technology, can realize large-scale on-chip logical photonic computing circuits, and has the potential for commercial application.

Description of the drawings

Figure 1 is a schematic system structure diagram of an optical digital multiplier with scalable bit width provided by the present invention.

Figure 2 is a working principle diagram of a 4-bit bit-width multiplier in an optical digital multiplier with scalable bit-width provided by the present invention.

Figure 3 is a diagram showing relevant experimental results of an optical digital multiplier with scalable bit width provided by the present invention.

Figure 4 is an all-optical implementation scheme of a binary converter in an optical digital multiplier with scalable bit width provided by the present invention.

Figure 5 is an optoelectronic and optical implementation scheme of a binary converter in an optical digital multiplier with scalable bit width provided by the present invention.

FIG. 6 is a schematic diagram of step-by-step accumulation in an optical digital multiplier with scalable bit width provided by the present invention.

FIG. 7 is a schematic diagram of the optical structure based on the step-by-step accumulation principle in an optical digital multiplier with scalable bit width provided by the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

As shown in Figure 1, an optical digital multiplier with scalable bit width in an example of the present invention includes a partial product generation and accumulation area 1, and a binarization area 2. In the partial product generation and accumulation area 1, the multi-wavelength laser source 11 is used to generate n wavelengths and input them respectively into the intensity modulator 12 for loading the A signal. The intensity modulator 12 for loading the A signal 12 is used to load the multiplier A signal to the n wavelengths output by the multi-wavelength laser source in the form of time series, and the output is divided into n channels (corresponding to n wavelengths) through the first wavelength division multiplexer 131 for subsequent input. Among the intensity modulators, the n intensity modulators 141, 142, 143,..., 14n used to load the B signal are respectively used to load B ₁ , B ₂ , B ₃ ,..., B _n in the multiplier B signal , since two series-connected intensity modulators can perform a logical AND function, the outputs of the intensity modulators 141, 142, 143,..., 14n are respectively B ₁ , B ₂ , B ₃ ,..., in the multiplier B signal. The partial product result of B _n and the multiplier A signal. The n-1 delay lines 151, 152, 15(n-1) are used to delay the generated partial product result bit by bit to realize carry in the timing. The output result is input to the second wavelength division multiplexer 132 to achieve mixing and superposition of partial product signals. The mixed signal is then input to binarization area 2. Among them, the hex converter 23 is used to convert the input signal from a decimal signal into a binary signal, and the delay lines 211, 212, ..., 21m are used to delay the high-bit output of the hex converter 23 bit by bit. , thereby realizing the transmission of the carry signal. The m+1→1 combiner 22 is used to combine the carry signals output by the m delay lines 211, 212,..., 21m with the partial product generation and accumulation area 1 The output partial accumulation signal is mixed and accumulated to realize the feedback of the carry signal, and is input to the binary converter 23. Through the above method, the accumulation and summation of the partial product signal in the binary system can be realized. The lowest bit of the format converter 23 outputs the operation result of the multiplier. Figure 2 shows the working principle diagram of a 4-bit wide multiplier. As shown in (a) in the figure, two series-connected intensity modulators can form a logic AND gate. Only when A _i and B _j are all 1, there will be light output, and the output level can be considered to be 1. In other cases, there is no light output, and the output level can be considered to be 0. (b) in Figure 2 shows the distribution of partial products in the two dimensions of time and space. Due to the role of the delay line in Figure 1, the partial products related to B ₂ , B ₃ ,..., B _n are respectively Delay 1, 2, ..., (n-1) τ, where τ corresponds to the code length of one symbol of the multiplier signal. In the partial product generation and accumulation area 1, the carry of the partial product signal is realized through delay. (c) in Figure 2 shows the process of accumulating and summing the integrated signals in binary form in the binary accumulation area. It can be seen that after the mixed signal is input to the hexadecimal conversion device, the lowest bit is output as the multiplication result, and the high-bit output is delayed by bits to realize the transmission of the carry signal. Through the above method, the entire binary multiplication process is completed. Figure 3 shows the experimental results of 32-bit binary numbers and binary numbers 11, 101, and 1001 respectively, which are completely consistent with the theoretical calculation results.

Figure 4 shows the purely optical implementation of the base conversion device. An optical linear matrix is combined with optical nonlinear materials to form an optical neural network, and the training is performed to obtain the specified target output, thereby realizing the base conversion function. Figure 5 shows an implementation method of a photoelectric-optical 2-bit binary converter. First, the optical signal detector 91 is used to convert the input optical signal into an electrical signal, and then the electrical signal is used to drive the electrically controlled microrings 92 and 93 to make them resonate. The position of the peak moves, and the output of the corresponding signal is controlled by inputting continuous light at the specified wavelength position. As shown in (c) in the figure, the 2-bit binary converter corresponds to 4 inputs of different levels. For the ESC microring 92, its target output is C ¹ bit, then the inputs are λ ₃ and λ ₄ as shown in (b) in the figure. Only when the levels are 2 and 3, the corresponding binary 10 and 11, there is light output. Similarly, for the electronically controlled micro-ring 92, the target output is C ¹ bit, then the inputs are λ ₂ and λ ₄ as shown in (d) in the figure. When the electric When the value is 1 and 3, corresponding to binary 01 and 11, there is light output at the output end of the microring.

In view of the difficulty in directly implementing an m-bit-wide hexadecimal converter, the step-by-step accumulation method as shown in Figure 6 can also be used to perform n-1 pairwise sums to achieve the binary sum of all partial products. In this way, an n-bit-wide multiplier can be implemented by using only n-1 2-bit-wide base converters. Its specific on-chip implementation is shown in Figure 7. The first half of the structure remains unchanged from the original architecture. In a silicon-based chip, the intensity modulator 41 can be implemented by a Mach-Zehnder modulator, and the intensity modulators 42, 43, 44,..., 4(n+1) can be implemented by a Mach-Zehnder modulator or an electrically controlled microring. The delay line can be implemented by a spiral waveguide. In the multiplier B, the partial product results corresponding to B ₁ and B ₂ are first combined by the 2→1 coupler 711 to obtain a mixed signal of the two partial products, and then input to the 2-bit hexadecimal converter 81, the high bit The output of C ¹ is delayed by τ through the delay line 521, that is, after carrying forward one bit in the timing, it is combined with the mixed signal of the two partial products through the 2→1 coupler 721 to realize the transmission of the carry signal. The output result is then binary added with the partial product result corresponding to B ₃ , and so on, and finally the binary addition of all partial products is completed. In this way, n-bit wide digital multipliers can also be implemented.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements, etc., made within the spirit and principles of the present invention, All should be included in the protection scope of the present invention.

Claims (8)

1. An optical digital multiplier with scalable bit width, characterized in that it includes a partial product generation and accumulation area (1) and a binarization area (2), and the partial product generation and accumulation area (1) includes a Multi-wavelength laser source (11), n+1 intensity modulators (12, 141, 142, 143,...14n), two wavelength division multiplexers (131, 132), n-1 delay lines (151 , 152, 15(n-1)), the multi-wavelength laser source (11) is used to generate n wavelengths and input to the intensity modulator (12), the intensity modulator (12) is used to convert the multiplier The A signal is loaded onto n wavelengths in the form of a time series, and is divided into B ₁ , B ₂ , B ₃ ,..., B corresponding to n inputs to the loaded multiplier B signal through the first wavelength division multiplexer (131) _n intensity modulators (141, 142, 143, ..., 14n) of n, output the partial product of B ₁ , B ₂ , B ₃ , ..., B _n and the multiplier A signal, the n-1 delays Lines (151, 152, 15(n-1)) are used to delay the generated partial product bit by bit to implement carry in the timing, and finally input it to the second wavelength division multiplexer (132) to realize the partial product signal Mix overlay; The binary area (2) includes m delay lines (211, 212,..., 21m), an m+1→1 combiner (22), and a base converter (23). The base conversion The converter (23) is used to convert the input signal from a decimal signal into a binary signal, and the delay line (211, 212,..., 21m) is used to convert the high bit (C ^m ) of the decimal converter (23), ..., C ² , C ¹ ) output bit-wise delay, thereby realizing the transmission of the carry signal. The m+1→1 combiner (22) is used to combine the m delay lines (211, 212, ... , the carry signal output by 21m) is mixed and accumulated with the mixed superposition signal output by the partial product generation and accumulation area (1) to realize feedback of the carry signal and input it into the base converter (23), The lowest bit C ⁰ of the hexadecimal converter (23) outputs the operation result of the multiplier. 2. An optical digital multiplier with expandable bit width according to claim 1, characterized in that the partial product generates continuous light corresponding to n wavelengths of light input to the accumulation area (1), and the electrical input are the two binary multipliers A=A _n ...A ₂ A ₁ and B=B _n ...B ₂ B ₁ of the multiplier, and the output is the mixed signal after the accumulation and addition of the parts corresponding to the two multipliers; the binarization area ( The input of 2) is the mixed signal output by the partial product generation and accumulation area (1), and the output is the result of the multiplication operation; The partial product generation and accumulation area (1) is used to generate partial products corresponding to the two multipliers in the multiplier and mix and accumulate them. The binarization area (2) is used to generate partial products and the accumulation area (1). Part of the accumulation and addition signal is converted from a decimal signal into a binary signal. The high-bit output (C ^m ,..., C ² , C ¹ ) is delayed by bits and fed back to the mixed signal to realize the transmission of the carry signal. The lowest-bit output C ⁰ is used as a multiplication The result of the operation. 3. An optical digital multiplier with expandable bit width according to claim 1, characterized in that the carry number m of the base converter (23) and the bit width n of the multiplier need to satisfy: n+ 1≤2m ⁺¹ -m. 4. An optical digital multiplier with scalable bit width according to claim 1, characterized in that the delay of the n-1 delay lines (151, 152,..., 15(n-1)) are respectively τ, 2τ,..., (n-1)τ, the delays of m delay lines (211, 212,..., 21m) are all τ, and τ corresponds to the code length of one symbol of the multiplier signal. 5. An optical digital multiplier with scalable bit width according to claim 1, characterized in that the multi-wavelength laser source (11) is an optical frequency comb, or a multi-channel laser outputs lasers of different wavelengths. The bundle is realized. 6. An optical digital multiplier with scalable bit width, characterized in that it includes a multi-wavelength laser source (31), n+1 intensity modulators (41, 42, 43, 44,..., 4(n +1)), wavelength division multiplexer (5), 2(n-1) delay lines (611, 612,…, 61(n-1), 621, 622,…, 62(n-1) ), 2(n-1) 2→1 couplers (711, 712,..., 71(n-1), 721, 722,..., 72(n-1)), (n-1) 2bit couplers converter (81, 82, 8(n-1)), the multi-wavelength laser source (31) is used to generate n wavelengths and input to the intensity modulator (41), the intensity modulator (41) It is used to load the multiplier A signal to n wavelengths in the form of time series, and divide it into corresponding n channels through the wavelength division multiplexer (5) and input it to B ₁ , B ₂ , B ₃ in the loaded multiplier B signal. ..., B _n n intensity modulators (42, 43, 44, ..., 4n), output B ₁ , B ₂ , B ₃ , ..., B _n and the partial product of the multiplier A signal, the n-1 A delay line (611, 612, 61(n-1)) is used to delay the generated partial product bit by bit to realize the carry in the timing. The partial product results corresponding to B ₁ and B ₂ are first determined by the above 2→ 1 coupler (711) combines to obtain the mixed signal of the two partial products, which is then input to the 2-bit binary converter (81). The output of the high-order C ¹ is delayed by τ through the delay line (521). That is, after one bit is carried forward in the timing, the carry signal is transmitted after being combined with the two partial product mixed signals through the 2→1 coupler (721), thereby completing the binary phase of the partial product results corresponding to B1 and B2. Add, the output result is then binary added with the partial product result corresponding to B ₃ , and so on, and finally completes the binary addition of all partial products. The lowest value of the n-1th 2-bit binary converter 8(n-1) Bit C ⁰ outputs the final result of the multiplier operation, thus implementing an n-bit wide digital multiplier. 7. An optical digital multiplier with scalable bit width according to claim 6, characterized in that the (n-1) delay lines (611, 612,..., 61(n-1)) The delays of are respectively τ, 2τ,..., (n-1)τ, and the delays of the (n-1) delay lines (621, 622,..., 62(n-1)) are all τ, τ corresponds to the code length of one symbol of the multiplier signal. 8. An optical digital multiplier with scalable bit width according to claim 6, characterized in that the intensity modulator (41) is a Mach-Zehnder modulator, and the intensity modulators (42, 43, 44 ,...,4(n+1)) is a Mach-Zehnder modulator or an electronically controlled microring, and the delay line (611, 612,..., 61(n-1), 621, 622,..., 62( n-1)) is a spiral waveguide.