CN117270117A

CN117270117A - Semiconductor structure and forming method thereof

Info

Publication number: CN117270117A
Application number: CN202310959876.8A
Authority: CN
Inventors: 曾智伟; 夏兴国; 斯帝芬·鲁苏; 余振华; 周淳朴
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-09-01
Filing date: 2023-08-01
Publication date: 2023-12-22

Abstract

The semiconductor structure includes: an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed over the first dielectric layer. The semiconductor structure further includes: a first die disposed on and electrically connected to the optical interposer; a first substrate located under the optical interposer; and a conductive connection located under the first substrate. Embodiments of the present application also relate to methods of forming semiconductor structures.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

An optical data communication system encodes digital data patterns by modulating a laser light. The modulated laser light is transmitted from the sending node to the receiving node over an optical data network. The modulated laser light that has reached the receiving node is demodulated to obtain the original digital data pattern. Implementation and operation of optical data communication systems relies on having reliable and efficient mechanisms for transmitting and receiving laser light.

Sometimes, transmitting and receiving nodes in an optical data network may be interconnected by an interposer, and optical signals (i.e., light) are transmitted through the interposer. Such an interposer may be referred to as an optical interposer. The use of an optical interposer may reduce the length of the optical path and improve the integrity of the optical signal. The optical interposer also enables low cost integration of optoelectronic devices. An optical interposer that can improve chip and system integration and is compatible with CMOS fabrication processes is desired.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor structure comprising: an optical interposer comprising at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed over the first dielectric layer; a first die disposed on and electrically connected to the optical interposer; a first substrate located under the optical interposer; and a conductive connection located under the first substrate.

Other embodiments of the present application provide a semiconductor structure comprising: an optical interposer comprising a first dielectric layer and a second dielectric layer on the first dielectric layer, a first photonic device in the first dielectric layer, a second photonic device in the second dielectric layer, and a redistribution layer on the second dielectric layer, wherein the second dielectric layer is between the first dielectric layer and the redistribution layer; a first die and a second die disposed on the redistribution layer, wherein the first die and the second die are electrically connected to the redistribution layer; a first substrate located under the first dielectric layer; a conductive connection located under the first substrate; and a via passing through the first and second dielectric layers and the first substrate and electrically coupling the redistribution layer to the conductive connection.

Still further embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a first structure having a first substrate and a first layer on the first substrate, wherein the first layer comprises a waveguide in a first dielectric material and one of a modulator and a photodetector; bonding the first structure to a carrier; removing the first substrate from the first structure; providing a second structure having a second substrate and a second layer on the second substrate, wherein the second layer comprises a silicon nitride-based photonic device in a second dielectric material; bonding the first layer to the second layer; removing the carrier; forming a via through the first layer, the second layer, and the second substrate; forming a redistribution layer on the first layer; attaching one or more dies on the redistribution layer; and attaching the second substrate to a base substrate.

Drawings

The invention is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only unless explicitly disclosed. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1, 2 and 3 illustrate partial, simplified cross-sectional views of a semiconductor structure or system having an optical interposer according to an embodiment of the present invention.

Fig. 4, 5 and 6 illustrate partial, simplified top views of a semiconductor structure or system having an optical interposer according to an embodiment of the present invention.

Fig. 7 illustrates a flow chart of a method of fabricating a semiconductor structure or system having an optical interposer, in accordance with an embodiment of the present invention.

Fig. 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 illustrate partial, simplified cross-sectional views of a semiconductor structure or system during various stages of manufacture of a method in accordance with fig. 7, in accordance with an embodiment of the present invention.

Fig. 18 illustrates a flow chart of a method of fabricating a semiconductor structure or system having an optical interposer according to another embodiment of the present invention.

Fig. 19, 20, 21 and 22 illustrate partial, simplified cross-sectional views of a semiconductor structure or system during various stages of manufacture of a method in accordance with fig. 18, in accordance with an embodiment of the present invention.

Fig. 23 illustrates a flow chart of a method of fabricating a semiconductor structure or system having an optical interposer according to another embodiment of the invention.

Fig. 24, 25, 26, 27, 28 and 29 illustrate partial, simplified cross-sectional views of a semiconductor structure or system during various stages of manufacture of a method in accordance with fig. 23, in accordance with an embodiment of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Furthermore, when values or ranges of values are described using "about," "approximately," etc., the term is intended to encompass values within a reasonable range that take into account inherent variations during manufacture as will be appreciated by those of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may cover a size range from 4.25nm to 5.75nm, with a manufacturing tolerance of +/-15% associated with depositing the material layer as known to one of ordinary skill in the art.

The present invention relates generally to optoelectronic systems, and in particular to semiconductor structures with optical intermediaries or optoelectronic systems and methods thereof.

An optical data communication system encodes digital data patterns by modulating a laser light. The modulated laser light is transmitted from a transmitting node (e.g., an optical transmitter) to a receiving node (e.g., an optical receiver) over an optical data network. The modulated laser light that has reached the receiving node is demodulated to obtain the original digital data pattern. The implementation and operation of an optical data communication system relies on having a reliable and efficient mechanism for transmitting and detecting laser light at different nodes within an optical data network.

Sometimes, the transmitting and receiving nodes in an optical data network may be interconnected by an interposer, and the optical signals transmitted through the interposer. Such an interposer may be referred to as an optical interposer. The use of an optical interposer may reduce the length of the optical path and improve the integrity of the optical signal. Some optical intermediaries do not have optoelectronic structures (such as grating couplers, optical modulators, photodetectors, etc.) within them. Instead, such optoelectronic structures are provided inside a chip disposed on an optical interposer, and the optical interposer is optically coupled to the chip through a perpendicular optical path for transmitting and/or receiving optical signals (e.g., in the form of modulated light). The need to provide perpendicular light paths sometimes limits the way the optical interposer can be integrated with the chip. For example, it may limit the mechanism by which the optical interposer is bonded and connected to the chip. Sometimes, it may be desirable for the lenses and mirrors to be coupled to or integrated with the optical interposer, which presents some difficulties for existing CMOS fabrication processes. Some embodiments of the present invention address these and other problems by providing an optical interposer that is compatible with existing CMOS fabrication processes and is flexible when integrated with other structures, such as integrated circuit chips and dies.

According to some embodiments of the invention, an optical structure or optical device (such as a photonic modulator, photodetector, waveguide, grating coupler, edge coupler, other optical element, or a combination thereof) is integrated in the optical interposer. The functions of electro-optical and photoelectric conversion are performed within the optical interposer and by the optical structure mentioned above. The optical interposer is electrically connected to an integrated circuit chip and/or die (hereinafter referred to as die) thereon. In some embodiments, the interface between the optical interposer and the die is only electrical and there is no optical interface. By having only an electrical interface between the optical interposer and the die, lenses and mirrors can be avoided in the optical path (which can be difficult to manufacture in a silicon planar process). In other words, semiconductor structures according to embodiments of the present invention are more compatible with silicon CMOS processes than those utilizing lenses and mirrors. Furthermore, because the interface between the optical interposer and the die is only electrical, the optical interposer can be flexibly integrated with the die using existing interconnect technologies, including hybrid bonding, controlled collapse chip connection (C4) bumps, and micro-bumps.

Furthermore, an optical interposer according to embodiments of the present invention may include multiple dielectric layers (e.g., each having predominantly silicon dioxide) with optical structures embedded in each dielectric layer. In an embodiment, the individual dielectric layers are bonded together, which increases the flexibility of integrating different types of photonic devices into the optical interposer. For example, one dielectric layer may include a silicon-based photonic device embedded therein, and another dielectric layer may include a silicon nitride-based photonic device embedded therein. The two dielectric layers comprising the photonic device therein are fabricated separately and bonded together. By separately manufacturing the two dielectric layers, the manufacturing cycle time and the product time to market can be reduced. Integrating both into the same optical interposer improves the functionality, performance, and reliability of the optical interposer. For example, silicon nitride based photonic devices (such as waveguides and edge couplers) are less sensitive to temperature variations. In an alternative embodiment, a plurality of dielectric layers (including photonic devices therein) in the disclosed optical interposer are fabricated stacked in sequence. In such embodiments, the bonding of multiple dielectric layers is avoided and a more precise vertical alignment between the photonic structures may be achieved. After the dielectric layer including the photonic device therein is fabricated, a redistribution layer (RDL) having metallization patterns such as metal pads, traces, and vias is formed on the dielectric layer. RDLs provide electrical connectivity for die on optical interposers. RDLs may also provide electrical connectivity for optical structures within the dielectric layers of the optical interposer. These and other aspects are further explained with reference to the drawings.

Referring to fig. 1, a semiconductor structure 100 (or system 100) is shown in accordance with an embodiment of the present invention. The semiconductor structure 100 includes a substrate (or base substrate) 102. In an embodiment, the substrate 102 may comprise an organic material and is referred to as an organic substrate 102. For example, the substrate 102 may include a Printed Circuit Board (PCB), such as an FR4 PCB. FR4 is a type of PCB substrate material made of flame retardant epoxy and fiberglass composite. In some embodiments, the substrate 102 may comprise an organic dielectric material, such as a polymer, which may comprise polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer-based materials, or combinations thereof. The substrate 102 also includes metallization patterns 104 (such as metal traces, metal pads, and metal vias) on or in the organic material. The metallization pattern 104 may comprise a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof, and may be formed using deposition and patterning processes.

The semiconductor structure 100 further includes another substrate 202. In an embodiment, the substrate 202 is a semiconductor substrate, such as a silicon substrate (e.g., a silicon wafer or a portion thereof). Additionally or alternatively, the substrate 202 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as a multi-layer or gradient substrate, may also be used as the substrate 202. In some embodiments, the substrate 202 may comprise a glass substrate or a ceramic substrate.

The substrate 202 and the substrate 102 are electrically and mechanically coupled or connected by conductive connections 220. The conductive connectors 220 may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, bumps formed by Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), and the like. The conductive connection 220 may be formed of a metal or metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 220 is formed using methods such as evaporation, sputtering, electroplating, electroless plating, printing, solder transfer, ball placement, reflow, and the like. The conductive connection 220 is connected to a conductive pad (or under bump metal) 224 on the bottom surface of the substrate 202 and to the metallization pattern 104 on the top surface of the substrate 102.

Still referring to fig. 1, the semiconductor structure 100 further includes an optical interposer 300 on the substrate 202. In the illustrated embodiment, optical interposer 300 includes dielectric layer 210, dielectric layer 310 on dielectric layer 210, and RDL 350 on dielectric layer 310. Optical interposer 300 includes optical structures 212, 214, and 216 in dielectric layer 210, and also includes optical structures 312, 314, 316, and 316 in dielectric layer 310. RDL 350 includes metallization pattern 340 (e.g., metal pads, metal traces, and/or metal vias) in and/or on dielectric layer 360. These elements will be described further below. Optical interposer 300 may include other optical structures in dielectric layers 210 and 310 not shown in fig. 1.

In an embodiment, dielectric layer 210 comprises silicon dioxide and optical structures 212, 214, and 216 comprise silicon nitride-based optical structures. In other words, optical structures 212, 214, and 216 may utilize the difference between the refractive indices of silicon nitride and silicon dioxide to confine and transmit light. In alternative embodiments, dielectric layer 210 may include other dielectric materials. In an embodiment, optical structures 212 and 214 include waveguides for transmitting optical signals to and receiving optical signals from optical structures in dielectric layer 310 (such as optical structure 318). In some embodiments, optical structures 212 and 214 are disposed at different vertical levels in dielectric layer 210. In an embodiment, the optical structure 216 may include an edge coupler for coupling the optical structure 214 (e.g., a waveguide) with the optical fiber array 502, and the optical fiber array 502 may be disposed on a side of the optical interposer 300. In an embodiment, edge coupler 216 includes multiple optical path layers that provide high tolerance for alignment with fiber array 502. The fiber array 502 may be further coupled with optical fibers 504 for connection to another structure or system (not shown), such as another semiconductor structure 100 or the like. The fiber array 502 and the fibers 504 are optional and may be omitted in some embodiments.

In an embodiment, dielectric layer 310 comprises silicon dioxide. In alternative embodiments, dielectric layer 310 may include other dielectric materials. In an embodiment, the optical structure 312 may include a grating coupler, and is referred to as a grating coupler 312. In an embodiment, grating coupler 312 includes several segments with a distance between each segment. The grating coupler 312 may be coupled with a laser generator and/or receiver 602 (such as shown in fig. 2) and configured to convert the laser signal into a modulated optical signal, and vice versa. In some embodiments, grating coupler 312 may comprise a metal or dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide or the dielectric constant of dielectric layer 310.

In an embodiment, optical structure 314 may include a photonic modulator, and is referred to as modulator 314. In some embodiments, modulator 314 may include silicon, germanium, tin, group III elements (such as aluminum, indium, or gallium), and/or group V elements (such as arsenic, phosphorus, antimony). In an embodiment, modulator 314 may be configured to convert the laser signal into a modulated optical signal that includes or carries a high-speed data signal. Modulator 314 may be electrically coupled to die 402 and/or controlled by die 402, as will be discussed further below.

In an embodiment, the optical structure 316 may include a photodetector, and is referred to as the photodetector 316. In an embodiment, the photodetector 316 may comprise a photodiode (or photodiode), a phototransistor, or other type of photodetector. The photodetector 316 is configured to convert the optical signal into an electrical signal. In some embodiments, the photodetector 316 may include silicon, germanium, tin, a group III element (such as aluminum, indium, or gallium), and/or a group V element (such as arsenic, phosphorus, antimony). Photodetector 316 may be electrically coupled to die 402, as will be discussed further below.

In an embodiment, the optical structure 318 may include a waveguide, and is referred to as a waveguide 318. In an embodiment, the waveguide 318 comprises a silicon waveguide that uses the difference between the refractive indices of silicon and the dielectric layer 310 (e.g., silicon dioxide) to confine and transmit light. In alternative embodiments, waveguide 318 may comprise a dielectric waveguide or a plasmonic waveguide. The dielectric waveguide may comprise patterned silicon nitride, amorphous silicon, or a high dielectric material surrounded by a low dielectric constant material of dielectric layer 310, such as silicon dioxide. The plasmonic waveguide can include patterned metal nanowires surrounded by a dielectric material of dielectric layer 310. Because dielectric layer 310 is located on top of dielectric layer 210, the optical structures in dielectric layer 310 (including optical structures 312, 314, 316, 318) are located on a higher vertical level than the optical structures in dielectric layer 210 (including optical structures 212, 214, 216). The optical interposer 300 may include a number of optical structures 312, 314, 316, and 318 located in a dielectric layer 310.

As shown in fig. 1, optical interposer 300 provides an optical path, such as a bi-directional optical path, by utilizing optical structures in dielectric layers 210 and 310. For example, modulator 314 may be configured to convert an electrical signal (received from die 402) into a modulated optical signal, which is then transmitted through waveguide 318. Waveguide 318 is coupled (e.g., edge coupled) to optical structure 212 (e.g., waveguide). In an embodiment such as that shown in fig. 1, the waveguide 318 overlaps the optical structure 212 (in other words, they vertically overlap each other) from a top view such that light can be transmitted between the waveguide 318 and the optical structure 212. The optical structure 212 is in turn coupled (e.g., edge coupled) to an optical structure 214 (e.g., another waveguide located at a different level than the optical structure 212), the optical structure 214 in turn being coupled to an edge coupler 216. From there, the modulated optical signal is transmitted to other elements external to the optical interposer 300, such as the fiber array 502. Instead, the optical structures 212, 214, and 216 may receive optical signals from other elements external to the optical interposer 300 (such as through the fiber array 502) and transmit such optical signals to the waveguide 318 and the photodetector 316, and then the waveguide 318 and the photodetector 316 convert the optical signals to electrical signals and transmit the electrical signals to the die 402.

In an embodiment, dielectric layer 210 and dielectric layer 310 are bonded together using an oxide-oxide bond, and the interface between dielectric layers 210 and 310 is barely detectable. This will be further discussed with reference to fig. 7 (such as operation 710). In some embodiments, optical interposer 300 may include additional dielectric layers in addition to dielectric layers 210 and 310. Furthermore, the additional dielectric layers may each include an optical structure such as discussed above. In addition, additional dielectric layers may be bonded to each other and to dielectric layers 210 and 310 using oxide-oxide bonding. This greatly increases the flexibility of creating an optical interposer 300 with the desired functionality. In an alternative embodiment, dielectric layer 210, including optical structures 212, 214, and 216, is formed directly on dielectric layer 310, rather than using bonding. For example, a material layer of dielectric layer 210 and optical structures 212, 214, and 216 may be deposited on dielectric layer 310 and subsequently formed, such as by patterning, etching, and/or polishing processes, to form dielectric layer 210 including optical structures 212, 214, and 216. This will be further discussed with reference to fig. 18 (such as operations 802 and 804).

Still referring to fig. 1, the optical interposer 300 further includes an RDL 350 on a dielectric layer 310 (which is the topmost dielectric layer in the optical interposer 300 with optical structures). RDL 350 includes one or more dielectric layers 360 and respective metallization patterns 340 (e.g., metal pads, metal traces, and/or metal vias) in or on one or more dielectric layers 360. The semiconductor structure 100 also includes conductive connections 370 disposed on some of the metallization patterns 340. Semiconductor structure 100 also includes dies 402 and 404 disposed on conductive connection 370. Conductive connections 370 and RDL 350 electrically and mechanically connect dies 402 and 404 to optical structures (such as modulator 314 and photodetector 316) in optical interposer 300.

In some embodiments, the dielectric layer 360 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a photolithographic mask. In other embodiments, dielectric layer 360 is formed of: nitrides, such as silicon nitride; oxides such as silicon oxide, PSG, BSG, PSG; etc. Dielectric layer 360 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The metallization pattern 340 may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or combinations thereof, and may be formed using deposition and patterning processes.

The conductive connection 370 may be a BGA connection, a solder ball, a metal pillar, a C4 bump, a micro bump, a bump formed by ENEPIG, or the like. The conductive connection 370 may be formed of a metal or metal alloy such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 370 is formed using methods such as evaporation, sputtering, electroplating, electroless plating, printing, solder transfer, ball placement, reflow, and the like.

Each of the dies 402 and 404 can be a bare die, such as a logic die (e.g., a central processing unit, a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE) die), etc., or a combination thereof.

In an embodiment such as that shown in fig. 1, at least die 402 is electrically connected to optical structures (such as optical structures 314 and 316) in optical interposer 300. For example, die 402 may process electrical signal processing while optical interposer 300 processes optoelectronic processing. In the cross-sectional view shown in fig. 1, die 404 is electrically connected to RDL 350, but not to the optical structures in optical interposer 300. However, the die 404 may be electrically connected to the optical structures in the optical interposer 300 in some other portion of the semiconductor structure 100. In addition, optical interposer 300 provides electrical interconnection between die 402 and die 404, for example, through RDL 350.

Still referring to fig. 1, semiconductor structure 100 further includes a via 330. In the illustrated embodiment, via 330 penetrates at least dielectric layers 210 and 310 and substrate 202. The via 330 electrically connects the conductive pad 224 to the metallization pattern 340. The via 330 may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof, and may be formed by plating, such as electroplating or electroless plating, or the like.

Fig. 2 illustrates another embodiment of a semiconductor structure 100. In this embodiment, semiconductor structure 100 includes die 406 in addition to die 402 and 404. Die 406 is electrically and mechanically connected to RDL 350 through conductive connections 370. Die 406 is electrically connected to via 330, via 330 in turn being electrically coupled to conductive connection 220 and substrate 102. Fig. 2 also shows a laser generator and/or receiver 602 that may be coupled to the grating coupler 312. Other aspects of this embodiment are the same as or similar to the embodiment shown in fig. 1.

Fig. 3 illustrates yet another embodiment of a semiconductor structure 100. In this embodiment, the semiconductor structure 100 includes a plurality of dies 402, such as dies 402A, 402B, and so on. Each of the dies 402 is electrically coupled to optical structures in the optical interposer 300, and in particular to optical structures 314A, 316A, 314B, and 316B in the dielectric layer 310. For example, die 402A may be electrically coupled to optical modulator 314A and photodetector 316A, with optical modulator 314A and photodetector 316A being optically coupled to one or more waveguides 318A. Further, the die 402B may be electrically coupled to an optical modulator 314B and a photodetector 316B, the optical modulator 314B and the photodetector 316B being optically coupled to one or more waveguides 318B. The one or more waveguides 318A and the one or more waveguides 318B are optically coupled through one or more optical structures (e.g., waveguides) 212 in the dielectric layer 210. In an embodiment, die 402A may transmit an electrical signal to optical modulator 314A, and optical modulator 314A may then convert the electrical signal to a modulated optical signal. The modulated optical signal is then transmitted to the photodetector 316B, and the photodetector 316B then converts the modulated optical signal to an electrical signal and transmits the electrical signal to the die 402B. Instead, die 402B may transmit an electrical signal to optical modulator 314B, and optical modulator 314B may then convert the electrical signal to a modulated optical signal. The modulated optical signal is then transmitted to the photodetector 316A, and the photodetector 316A then converts the modulated optical signal to an electrical signal and transmits the electrical signal to the die 402A. Thus, semiconductor structure 100 enables a bi-directional optical path between dies 402A and 402B. In various embodiments, semiconductor structure 100 may be configured to provide unidirectional optical paths from die 402A to 402B, unidirectional optical paths from die 402B to 402A, and/or configured to provide bidirectional optical paths between die 402A and 402B. Other aspects of this embodiment are the same as or similar to the embodiment shown in fig. 1.

In some embodiments, semiconductor structure 100 may include two or more dies 402, 404, and/or 406 optically interconnected by optical interposer 300. Some examples are further illustrated in fig. 4, 5 and 6. These examples demonstrate that the disclosed optical interposer enables very flexible system integration.

Fig. 4 illustrates a top view of semiconductor structure 100 according to an embodiment. As shown in fig. 4, semiconductor structure 100 includes two dies 402A and 402B on substrate 202, substrate 202 in turn being located on substrate 102. Each of the dies 402A and 402B may be a logic die, FPGA, memory stack, or other type of die. The dies 402A and 402B are interconnected by optical paths within the optical interposer 300 (not shown in fig. 4) disposed between the dies and the substrate 202. Dashed box 420AB indicates optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402A. Dashed box 420BA indicates optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled with die 402B. Dashed boxes 420AB and 420BA are optically coupled to each other by optical structures 230 in optical interposer 300, such as optical structures 212, 214, 216 in dielectric layer 210 discussed above. In an embodiment, the optical path between dashed boxes 420AB and 420BA is bi-directional. The optical path includes a plurality of optical structures 230 in parallel between dashed boxes 420AB and 420 BA. In an embodiment, these optical structures 230 are silicon nitride based optical devices. The optical structures 230 may be implemented at the same vertical level or at different vertical levels in the optical interposer 300.

Fig. 5 illustrates a top view of a semiconductor structure 100 in accordance with another embodiment. As shown in fig. 5, semiconductor structure 100 includes three dies 402A, 402B, and 402C on substrate 202, which in turn is located on substrate 102. Each of the dies 402A, 402B, and 402C may be a logic die, FPGA, memory stack, or other type of die. The dies 402A, 402B, and 402C are interconnected by optical paths within the optical interposer 300 (not labeled in fig. 5) disposed between the dies and the substrate 202. Dashed boxes 420AB and 420AC indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402A. Dashed boxes 420BA and 420BC indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402B. Dashed boxes 420CA and 420CB indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402C. Dashed boxes 420AB and 420BA are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420AC and 420CA are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420BC and 420CB are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). In an embodiment, these optical structures 230 are silicon nitride based optical devices. The optical structures 230 may be implemented at the same vertical level or at different vertical levels in the optical interposer 300. In an embodiment, the optical path between dashed boxes 420AB and 420BA is bidirectional, the optical path between dashed boxes 420BC and 420CB is bidirectional, and the optical path between dashed boxes 420AC and 420CA is bidirectional.

Fig. 6 illustrates a top view of a semiconductor structure 100 in accordance with another embodiment. As shown in fig. 6, semiconductor structure 100 includes four dies 402A, 402B, 402C, and 402D on substrate 202, which in turn is located on substrate 102. Each of the dies 402A, 402B, 402C, and 402D may be a logic die, FPGA, memory stack, or other type of die. The dies 402A, 402B, 402C, and 402D are interconnected by optical paths within the optical interposer 300 (not labeled in fig. 6) disposed between the dies and the substrate 202. Dashed boxes 420AB, 420AC, and 420AD indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402A. Dashed boxes 420BA, 420BC, and 420BD indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402B. Dashed boxes 420CA, 420CB, and 420CD indicate optical structures (such as optical structures 314, 316, 318 discussed above) in optical interposer 300 that are electrically coupled to die 402C. Dashed boxes 420DA, 420DB, and 420DC indicate optical structures in optical interposer 300 that are electrically coupled with die 402D (such as optical structures 314, 316, 318 discussed above). Dashed boxes 420AB and 420BA are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420AC and 420CA are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420AD and 420DA are optically coupled to each other through a plurality of parallel optical structures 230-2 in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420BC and 420CB are optically coupled to each other by a plurality of parallel optical structures 230-1 in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420BD and 420DB are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). Dashed boxes 420CD and 420DC are optically coupled to each other by a plurality of optical structures 230 in parallel in optical interposer 300 (such as optical structures 212, 214, 216 in dielectric layer 210 discussed above). In an embodiment, these optical structures 230, 230-1, and 230-2 are silicon nitride based optical devices. In an embodiment, optical structures 230-1 and optical structures 230-2 are implemented at different vertical levels in optical interposer 300. The optical structures 230 may be implemented at the same vertical level or at different vertical levels in the optical interposer 300. The optical structures 230 and 230-1 may be implemented at the same vertical level or at different vertical levels in the optical interposer 300. The optical structures 230 and 230-2 may be implemented at the same vertical level or at different vertical levels in the optical interposer 300. In an embodiment, the optical path between dashed boxes 420AB and 420BA is bidirectional, the optical path between dashed boxes 420AC and 420CA is bidirectional, the optical path between dashed boxes 420AD and 420DA is bidirectional, the optical path between dashed boxes 420BC and 420CB is bidirectional, the optical path between dashed boxes 420BD and 420DB is bidirectional, and the optical path between dashed boxes 420CD and 420DC is bidirectional.

Fig. 7 illustrates a flow chart of a method 700 for fabricating the semiconductor structure 100, in accordance with various embodiments. The method 700 includes operations 702, 704, 706, 708, 710, 712, 714, 716, 718, and 720. The present invention contemplates additional operations. Additional operations may be provided before, during, and after method 700, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 700. Method 700 is described below in conjunction with fig. 8-17, with fig. 8-17 showing cross-sectional views of semiconductor structure 100 and other structures during various stages of fabrication in accordance with an embodiment of method 700.

In operation 702, a method 700 (fig. 7) provides or is provided with a first structure 50 having a substrate 302 and a structure 304 located on the substrate 302, such as shown in fig. 8. Structure 304 includes a dielectric layer 310 and a plurality of optical structures in dielectric layer 310. For example, the plurality of optical structures may include the grating coupler 312, modulator 314, photodetector 316, and waveguide 318 discussed above. In an embodiment, the plurality of optical structures (e.g., grating coupler 312, modulator 314, photodetector 316, and waveguide 318) are fabricated from a silicon-on-insulator (SOI) substrate. For example, the SOI substrate includes a silicon layer (or another semiconductor layer), a portion of the dielectric layer 310 between the plurality of optical structures and the substrate 302, wherein the silicon layer (or another semiconductor layer) provides semiconductor material in the plurality of optical structures. In an embodiment, the substrate 302 is a silicon substrate, such as a silicon wafer. In an embodiment, dielectric layer 310 comprises silicon dioxide. Dielectric layer 310 may include a dielectric sublayer. The method 700 also provides or provides the carrier 150 with the temporary bonding material 160. For example, the carrier 150 may be a glass substrate, and the temporary bonding material 160 may be a polyimide-based temporary adhesive or other type of adhesive.

In operation 704, the method 700 (fig. 7) bonds the first structure 50 and the carrier 150 together using the temporary bonding material 160, such as shown in fig. 9. Specifically, structure 304 is attached to temporary bonding material 160 and becomes sandwiched between substrate 302 and carrier 150.

In operation 706, the method 700 (fig. 7) removes the substrate 302, for example, by grinding and/or polishing the substrate 302. The structure 304 is still bonded to the carrier 150 by the temporary bonding material 160, such as shown in fig. 10. Thus, the surface of structure 304 (which is the surface of dielectric layer 310) is exposed.

In operation 708, the method 700 (fig. 7) provides or is provided with a second structure 60 having a substrate 202 and a structure 204 located on the substrate 202, such as shown in fig. 11. Structure 204 includes a dielectric layer 210 and a plurality of optical structures in dielectric layer 210. For example, the plurality of optical structures may include the optical structures (e.g., waveguides) 212, 214 and the optical structure (e.g., edge coupler) 216 discussed above. In an embodiment, the substrate 202 is a silicon substrate (e.g., a silicon wafer or a portion thereof). Additionally or alternatively, the substrate 202 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as a multi-layer or gradient substrate, may also be used as the substrate 202. In some embodiments, the substrate 202 may comprise a glass substrate or a ceramic substrate. In an embodiment, dielectric layer 210 comprises silicon dioxide. The dielectric layer 210 may include a dielectric sublayer. The surface of the dielectric layer 210 is exposed.

In operation 710, the method 700 (fig. 7) joins the first structure 50 and the second structure 60 together, such as shown in fig. 12. In an embodiment, the exposed surfaces of dielectric layers 210 and 310 comprise silicon dioxide, and the bonding of first structure 50 and second structure 60 is accomplished using an oxide-oxide direct bond (i.e., by bonding the exposed surfaces of dielectric layers 210 and 310). Thus, the interface between dielectric layer 210 and dielectric layer 310 is barely visible. In addition, the bond strength of the oxide-oxide bond is strong enough to withstand any backside processes such as grinding and Chemical Mechanical Planarization (CMP).

In operation 712, the method 700 (fig. 7) peels the carrier 150, for example, by using a thermal process or an Ultraviolet (UV) process to decompose the temporary bonding material 160. This leaves dielectric layers 210 and 310 on substrate 202, such as shown in fig. 13. Thus, the other surface of structure 304 (which is the surface of dielectric layer 310) is exposed.

In operation 714, method 700 (fig. 7) forms via 330 penetrating dielectric layers 310 and 210 and substrate 202, such as shown in fig. 14. This may involve a variety of processes. For example, operation 714 may first form a hole through dielectric layers 310 and 210 and substrate 202, such as by drilling, etching, and/or other methods. Operation 714 may then form conductive vias 330 in the holes (e.g., on sidewalls of the holes and/or completely fill the holes). Operation 714 may also form conductive pads 224 on the bottom surface of substrate 202 that are electrically connected to vias 330. Operation 714 may further perform a planarization process (such as CMP) on via 330 and dielectric layer 310.

In operation 716, method 700 (fig. 7) forms RDL 350 on via 330 and dielectric layer 310, such as shown in fig. 15. RDL 350 includes one or more dielectric layers 360 and metallization pattern 340 discussed above. Operation 716 may include patterning, etching, deposition, planarization, and/or other suitable processes. Accordingly, optical interposer 300 is formed with RDL 350, dielectric layers 210 and 310, and optical structures embedded in dielectric layers 210 and 310. The conductive material in the via 330 and the metallization pattern 340 may be formed in the same process or in different processes.

In operation 718, method 700 (fig. 7) attaches one or more dies 402 and/or 404 on RDL 350, such as shown in fig. 16. One or more dies 402 and/or 404 may be attached to RDL 350 using conductive connections 370 discussed above. This results in an assembly having substrate 202, optical interposer 300, die 402 and/or 404, and vias 330.

In operation 720, the method 700 (fig. 7) attaches the assembly resulting from operation 718 to the substrate 102, such as shown in fig. 17. The substrate 102 may be an organic substrate as discussed above and may include a metallization pattern 104. The assembly may be attached to the substrate 102 using conductive connections 220 as discussed above.

Fig. 18 shows a flowchart of a method 800 for fabricating a semiconductor structure 100 according to another embodiment. Method 800 includes operations 802, 804, 806, 808, 810, 812, 814, and 816. The present invention contemplates additional operations. Additional operations may be provided before, during, and after method 800, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 800. The method 800 is described below in conjunction with fig. 19-22 and 14-17, with fig. 19-22 and 14-17 showing cross-sectional views of the semiconductor structure 100 and other structures during various stages of fabrication in accordance with embodiments of the method 800.

In operation 802, the method 800 (fig. 18) provides or is provided with a first structure 50 having a substrate 302 and a structure 304 located on the substrate 302, such as shown in fig. 19. Structure 304 includes a dielectric layer 310 and a plurality of optical structures in dielectric layer 310. For example, the plurality of optical structures may include the grating coupler 312, modulator 314, photodetector 316, and waveguide 318 discussed above. In an embodiment, the plurality of optical structures (e.g., grating coupler 312, modulator 314, photodetector 316, and waveguide 318) are fabricated from a silicon-on-insulator (SOI) substrate. For example, the SOI substrate includes a silicon layer (or another semiconductor layer), a portion of the dielectric layer 310 between the plurality of optical structures and the substrate 302, wherein the silicon layer (or another semiconductor layer) provides semiconductor material in the plurality of optical structures. In an embodiment, the substrate 302 is a silicon substrate, such as a silicon wafer. In an embodiment, dielectric layer 310 comprises silicon dioxide. Dielectric layer 310 may include a dielectric sublayer.

In operation 804, method 800 (fig. 18) forms structure 204 on structure 304, such as shown in fig. 20. Structure 204 includes a dielectric layer 210 and a plurality of optical structures in dielectric layer 210. For example, the plurality of optical structures may include the optical structures (e.g., waveguides) 212, 214 and the optical structure (e.g., edge coupler) 216 discussed above. In some embodiments, the optical structures in dielectric layer 210 are formed to overlap with the optical structures in dielectric layer 310 so as to be optically coupled to each other to form an optical path. In an embodiment, dielectric layer 210 comprises silicon dioxide and optical structures 212, 214, and 216 comprise silicon nitride. The dielectric layer 210 may include a dielectric sublayer. In some embodiments, structure 204 is in direct contact with structure 304. In an embodiment, structure 204 is formed by a process that includes depositing a material (such as a dielectric material) over structure 304 and patterning the material to form the individual optical structures.

In operation 806, the method 800 (fig. 18) attaches the substrate 202 on the structure 204, such as shown in fig. 21. In an embodiment, the substrate 202 is a silicon substrate (e.g., a silicon wafer or a portion thereof). Additionally or alternatively, the substrate 202 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as a multi-layer or gradient substrate, may also be used as the substrate 202. In some embodiments, the substrate 202 may comprise a glass substrate or a ceramic substrate. The substrate 202 may be attached to the structure 204 using an adhesive or other suitable material and/or method.

In operation 808, the method 800 (fig. 18) removes the substrate 302, for example, by grinding and/or polishing the substrate 302. The resulting structure is shown in fig. 22, upside down as compared to the structure shown in fig. 21.

In operation 810, method 800 (fig. 18) forms a via 330 penetrating dielectric layers 310 and 210 and substrate 202, such as shown in fig. 14. This is essentially the same as operation 714 discussed above.

In operation 812, method 800 (fig. 18) forms RDL 350 over via 330 and dielectric layer 310, such as shown in fig. 15. This is essentially the same as operation 716 discussed above.

In operation 814, method 800 (fig. 18) attaches one or more dies 402 and/or 404 on RDL 350, such as shown in fig. 16. This is essentially the same as operation 718 discussed above.

In operation 816, the method 800 (fig. 18) attaches the assembly resulting from operation 814 to the substrate 102, such as shown in fig. 17. This is essentially the same as operation 720 discussed above.

Fig. 23 shows a flow chart of a method 900 for manufacturing a semiconductor structure 100 according to yet another embodiment. Method 900 includes operations 902, 904, 906, 908, 910, and 912. The present invention contemplates additional operations. Additional operations may be provided before, during, and after method 900, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 900. Method 900 is described below in connection with fig. 24-29, with fig. 24-29 showing cross-sectional views of semiconductor structure 100 and other structures during various stages of fabrication in accordance with an embodiment of method 900.

In operation 902, the method 900 (fig. 23) provides or is provided with a first structure 50 having a substrate 302 and a structure 304 located on the substrate 302, such as shown in fig. 24. Structure 304 includes a dielectric layer 310 and a plurality of optical structures in dielectric layer 310. For example, the plurality of optical structures may include the grating coupler 312, modulator 314, photodetector 316, and waveguide 318 discussed above. In an embodiment, the plurality of optical structures (e.g., grating coupler 312, modulator 314, photodetector 316, and waveguide 318) are fabricated from a silicon-on-insulator (SOI) substrate. For example, the SOI substrate includes a silicon layer (or another semiconductor layer), a portion of the dielectric layer 310 between the plurality of optical structures and the substrate 302, wherein the silicon layer (or another semiconductor layer) provides semiconductor material in the plurality of optical structures. In an embodiment, the substrate 302 is a silicon substrate, such as a silicon wafer. In an embodiment, dielectric layer 310 comprises silicon dioxide. Dielectric layer 310 may include a dielectric sublayer. Further, as depicted in fig. 24, structure 304 includes connection structures 320, such as metal lines and vias. The connection structure 320 is electrically coupled to a plurality of optical structures. In this embodiment, the connection structure 320 is used to electrically connect a plurality of optical structures to a RDL 350 (see fig. 27) that is later fabricated. In another embodiment (not shown), a plurality of optical structures (e.g., grating coupler 312, modulator 314, photodetector 316, and waveguide 318) are fabricated on bulk silicon substrate 302, rather than an SOI substrate. In such an embodiment, as shown in fig. 24, portions of the dielectric layer between the plurality of optical structures and the substrate 302 are omitted.

In operation 904, method 900 (fig. 23) forms structure 204 on structure 304, such as shown in fig. 25. Structure 204 includes a dielectric layer 210 and a plurality of optical structures located in dielectric layer 210. For example, the plurality of optical structures may include the optical structures (e.g., waveguides) 212, 214 and the optical structure (e.g., edge coupler) 216 discussed above. In some embodiments, the optical structures in dielectric layer 210 are formed to overlap with the optical structures in dielectric layer 310 so as to be optically coupled to each other to form an optical path. Further, as depicted in fig. 25, structure 204 includes connection structure 222 electrically coupled to connection structure 320. The connection structure 222 may include metal lines and vias (see fig. 27) that electrically connect the plurality of optical structures to RDL 350, which is later fabricated. In an embodiment, dielectric layer 210 comprises silicon dioxide and optical structures 212, 214, and 216 comprise silicon nitride. The dielectric layer 210 may include a dielectric sublayer. In some embodiments, structure 204 is in direct contact with structure 304. In an embodiment, structure 204 is formed by a process that includes depositing material (such as dielectric material and conductive material) over structure 304 and patterning the material to form the various elements.

In operation 906, method 900 (fig. 23) forms via 330 penetrating dielectric layers 310 and 210 and substrate 302, such as shown in fig. 26. This is essentially the same as operation 714 discussed above.

In operation 908, method 900 (fig. 23) forms RDL 350 over via 330 and dielectric layer 210, such as shown in fig. 27. This is essentially the same as operation 716 discussed above. In the depicted embodiment, the metallization pattern 340 in RDL 350 is also electrically connected to the connection structure 222.

In operation 910, method 900 (fig. 23) attaches one or more dies 402 and/or 404 on RDL 350, such as shown in fig. 28. This is essentially the same as operation 718 discussed above.

In operation 912, the method 900 (fig. 23) attaches the assembly resulting from operation 910 to the substrate 102, such as shown in fig. 29. This is essentially the same as operation 720 discussed above.

Other components and processes may also be included in the embodiments discussed above. For example, test structures may be included to aid in the verification testing of semiconductor structure 100. The test structures may include, for example, test pads formed in RDL 350 that allow for testing of semiconductor structure 100, use of probes and/or probe cards, and the like. Verification tests may be performed on intermediate structures and final structures. Furthermore, the structures and methods disclosed herein may be used in conjunction with test system methods that incorporate intermediate verification of known good die (or known good device layers) to increase yield and reduce cost.

Although not intended to be limiting, one or more embodiments of the invention provide many benefits to semiconductor devices and fabrication, such as three-dimensional integrated circuits or systems with optical devices. For example, embodiments of the present invention provide an optical interposer that may be used in a three-dimensional integrated circuit or system. The optical interposer provides an optoelectronic device and a waveguide. In various embodiments, the interface between the optical interposer and the die attached thereto is only electrical, which makes possible flexible integration of the optical interposer and the die using existing or future developed bonding methods. The disclosed structures and methods can be easily integrated into existing semiconductor (such as CMOS) fabrication processes.

In an exemplary aspect, the present invention relates to a semiconductor structure comprising: an optical interposer having at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed over the first dielectric layer. The semiconductor structure further includes: a first die disposed on and electrically connected to the optical interposer; a first substrate located under the optical interposer; and a conductive connection located under the first substrate.

In an embodiment, the semiconductor structure further comprises: a via hole passing through the first and second dielectric layers and the first substrate and electrically connected to the conductive connection. In some embodiments of the semiconductor structure, the optical interposer further includes a redistribution layer on the second dielectric layer. In some embodiments, the at least one first photonic device comprises a silicon nitride based photonic device. In a further embodiment, the at least one second photonic device comprises a modulator, photodetector, waveguide, or grating coupler.

In some embodiments, the interface between the optical interposer and the first die is free of an optical interface. In some embodiments, the semiconductor structure further comprises: a base substrate located below the first substrate, wherein the conductive connection electrically couples the first substrate to the base substrate. In some embodiments, the semiconductor structure further comprises: an optical fiber array coupled to at least one first photonic device on a side of the optical interposer.

In some embodiments, the semiconductor structure further comprises: at least one third photonic device is located in the second dielectric layer, wherein the at least one second photonic device comprises a first photonic modulator, the at least one third photonic device comprises a first photodetector, and the first photonic modulator is optically coupled to the first photodetector. In a further embodiment, the at least one second photonic device further comprises a second photodetector, and the at least one third photonic device further comprises a second photonic modulator, wherein the second photonic modulator is optically coupled to the second photodetector. In yet a further embodiment, the semiconductor structure further comprises: a second die disposed on and electrically connected to the optical interposer, wherein the first photonic modulator is electrically coupled to the first die and the first photodetector is electrically coupled to the second die.

In another exemplary aspect, the present invention is directed to a semiconductor structure including an optical interposer. The optical interposer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, a first photonic device in the first dielectric layer, a second photonic device in the second dielectric layer, and a redistribution layer on the second dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the redistribution layer. The semiconductor structure further includes: a first die and a second die disposed on the redistribution layer, wherein the first die and the second die are electrically connected to the redistribution layer. The semiconductor structure further includes a first substrate under the first dielectric layer, a conductive connection under the first substrate, and a via through the first and second dielectric layers and the first substrate and electrically coupling the redistribution layer to the conductive connection.

In an embodiment of the semiconductor structure, the first photonic device comprises a silicon nitride based waveguide and the second photonic device comprises a photonic modulator, a photodetector, a waveguide, a grating coupler, or a combination thereof. In another embodiment, the connection between the optical interposer and the first die and the second die is an electrical connection and there is no optical connection.

In an embodiment, the semiconductor structure further comprises: an organic base substrate underlying the first substrate, wherein the conductive connection electrically couples the first substrate to the organic base substrate. In another embodiment, the first die and the second die are optically coupled to each other by a first photonic device and a second photonic device.

In yet another exemplary aspect, the present invention relates to a method comprising: a first structure is provided having a first substrate and a first layer on the first substrate, wherein the first layer includes a waveguide in a first dielectric material and one of a modulator and a photodetector. The method further comprises the steps of: bonding the first structure to the carrier; removing the first substrate from the first structure; and providing a second structure having a second substrate and a second layer located on the second substrate, wherein the second layer comprises a silicon nitride based photonic device located in a second dielectric material. The method further comprises the steps of: bonding the first layer to the second layer; removing the carrier; forming a via hole through the first layer, the second layer, and the second substrate; forming a redistribution layer on the first layer; attaching one or more dies on the redistribution layer; and attaching the second substrate to the base substrate.

In an embodiment of the method, the first dielectric material and the second dielectric material both comprise silicon dioxide, and the bonding of the first layer to the second layer uses an oxide-oxide bond. In another embodiment, one or more dies are attached to the redistribution layer using conductive connections. In yet another embodiment, the second substrate is attached to the base substrate using conductive connections.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising:

an optical interposer comprising at least one first photonic device in a first dielectric layer and at least one second photonic device in a second dielectric layer, wherein the second dielectric layer is disposed over the first dielectric layer;

A first die disposed on and electrically connected to the optical interposer;

a first substrate located under the optical interposer; and

and a conductive connection located under the first substrate.

2. The semiconductor structure of claim 1, further comprising:

and a via passing through the first and second dielectric layers and the first substrate and electrically connected to the conductive connection.

3. The semiconductor structure of claim 1, wherein the optical interposer further comprises a redistribution layer on the second dielectric layer.

4. The semiconductor structure of claim 1, wherein the at least one first photonic device comprises a silicon nitride based photonic device.

5. The semiconductor structure of claim 4, wherein the at least one second photonic device comprises a modulator, photodetector, waveguide, or grating coupler.

6. The semiconductor structure of claim 1, wherein an interface between the optical interposer and the first die is free of an optical interface.

7. The semiconductor structure of claim 1, further comprising:

a base substrate located below the first substrate, wherein the conductive connection electrically couples the first substrate to the base substrate.

8. The semiconductor structure of claim 1, further comprising:

an array of optical fibers coupled to the at least one first photonic device on a side of the optical interposer.

9. A semiconductor structure, comprising:

an optical interposer comprising a first dielectric layer and a second dielectric layer on the first dielectric layer, a first photonic device in the first dielectric layer, a second photonic device in the second dielectric layer, and a redistribution layer on the second dielectric layer, wherein the second dielectric layer is between the first dielectric layer and the redistribution layer;

a first die and a second die disposed on the redistribution layer, wherein the first die and the second die are electrically connected to the redistribution layer;

a first substrate located under the first dielectric layer;

a conductive connection located under the first substrate; and

a via passes through the first and second dielectric layers and the first substrate and electrically couples the redistribution layer to the conductive connection.

10. A method of forming a semiconductor structure, comprising:

providing a first structure having a first substrate and a first layer on the first substrate, wherein the first layer comprises a waveguide in a first dielectric material and one of a modulator and a photodetector;

Bonding the first structure to a carrier;

removing the first substrate from the first structure;

providing a second structure having a second substrate and a second layer on the second substrate, wherein the second layer comprises a silicon nitride-based photonic device in a second dielectric material;

bonding the first layer to the second layer;

removing the carrier;

forming a via through the first layer, the second layer, and the second substrate;

forming a redistribution layer on the first layer;

attaching one or more dies on the redistribution layer; and

the second substrate is attached to a base substrate.