CN117254894A - Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment - Google Patents

Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment Download PDF

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Publication number
CN117254894A
CN117254894A CN202311541062.9A CN202311541062A CN117254894A CN 117254894 A CN117254894 A CN 117254894A CN 202311541062 A CN202311541062 A CN 202311541062A CN 117254894 A CN117254894 A CN 117254894A
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clock
phase
speed serial
serial signal
sampling
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CN117254894B (en
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郝舒炜
贾弘翊
韦嶔
张红荣
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XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
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XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a method, a device and electronic equipment for automatically correcting the sampling phase of a high-speed serial signal; the method comprises the following steps: continuously sampling the associated clock of the high-speed serial signal, and traversing the PLL phases of the sampling clock to obtain a group of clock words corresponding to each PLL phase; determining a target phase of the PLL corresponding to at least one group of clock words with the lowest error rate by counting the error rate of each group of clock words; and performing PLL phase adjustment according to the target PLL phase to sample the high-speed serial signal by using the phase-adjusted sampling clock. The invention makes use of conventional universal resources in FPGA devices to simplify and ensure the receiving application of high-speed serial signals using random access clocks.

Description

Method and device for automatically correcting sampling phase of high-speed serial signal and electronic equipment
Technical Field
The invention belongs to the field of digital signal processing, and particularly relates to a method and device for automatically correcting sampling phase of a high-speed serial signal and electronic equipment.
Background
The receiving error rate of the high-speed serial signal is very dependent on the sampling phase of the data, and the theoretical optimal sampling point is the middle point of a signal eye diagram, and at the moment, the phase distance from the front edge and the back edge of the signal, which possibly change, is farthest, and the signal is most stable. The low-speed channel clock needs to be multiplied to 1/2 of the serial data frequency (high frequency) by a PLL (phase locked loop) and then used for sampling of the data.
In ASIC (application specific integrated chip), since the circuit is fixed, the routing delay of the sampling clock in the chip can be estimated, so that correct sampling can be realized by compensating the controllable delay line at the design level. For FPGA (field programmable gate array) devices, the signal trace is affected by software compiling, so that the length of the trace of the low-speed trace clock signal sent from IO (input/output) to PLL and returned to IO for serial data sampling is random, which causes uncertainty of phase relation between the high-speed clock for sampling data and the data itself, and makes it difficult to achieve optimal effect of receiving and sampling the high-speed serial signal.
Aiming at the problem that the high-speed serial signal in the FPGA is difficult to optimally sample, one solution is to fix the wiring delay of a sampling clock in an FPGA chip by applying strict layout and wiring constraint and manually apply a controllable delay line to the IO side of the sampled signal for compensation. However, the layout and wiring in the FPGA chip requires a very specialized factory background and information, FAE (Field Application Engineer, field technical support engineer) support, and the operation itself of performing the layout and wiring constraint is also troublesome, which causes a barrier to the use of the user; the manual delay compensation requires multiple attempts and does not necessarily achieve the optimal sampling point; more cumbersome, each new design requires repeating the above cumbersome adjustment work.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a method, an apparatus and an electronic device for automatically correcting a sampling phase of a high-speed serial signal.
The technical problems to be solved by the invention are realized by the following technical scheme:
in a first aspect, the present invention provides a method for automatically correcting a sampling phase of a high-speed serial signal, applied to an FPGA, the method comprising:
continuously sampling the associated clock of the high-speed serial signal, and traversing the PLL phases of the sampling clock to obtain a group of clock words corresponding to each PLL phase;
determining a target phase of the PLL corresponding to at least one group of clock words with the lowest error rate by counting the error rate of each group of clock words;
and performing PLL phase adjustment according to the target PLL phase to sample the high-speed serial signal by using the phase-adjusted sampling clock.
In one embodiment, when the data word period of the high-speed serial signal is equal to the clock period of the associated clock, the method further comprises:
and after the PLL phase adjustment is carried out according to the target PLL phase and before the sampling data is sliced and output, the slicing window of the deserializing circuit of the FPGA is adjusted so that the clock word which is deserialized by the deserializing circuit accords with a standard clock word, and the standard clock word is a clock word defined by an interface protocol corresponding to the high-speed serial signal.
In one embodiment, the bit period of the high-speed serial signal is equal to half the clock period of the associated clock.
In one embodiment, the high-speed serial signal comprises: LVDS (low voltage differential signaling) or TMDS (transition minimized differential signaling) from a CPU (central processing unit) or an external sensor.
In one embodiment, the method is implemented based on the general resources of an FPGA.
In a second aspect, the present invention provides an apparatus for automatically correcting sampling phase of a high-speed serial signal, applied to an FPGA, the apparatus comprising:
the phase traversing and adjusting module is used for traversing the PLL phases of the sampling clocks of the FPGA while the FPGA continuously samples the associated clocks of the high-speed serial signals, so that the FPGA obtains a group of clock words corresponding to the PLL phases respectively;
the clock word statistical analysis module is used for counting the error rate of each group of clock words and determining the target PLL phase corresponding to at least one group of clock words with the lowest error rate;
the phase traversing and adjusting module is further configured to perform PLL phase adjustment according to the target PLL phase, so that the FPGA samples the high-speed serial signal with the phase-adjusted sampling clock.
In one embodiment, when the data word period of the high-speed serial signal is equal to the clock period of the associated clock, the apparatus further comprises: a window adjustment module;
the window adjusting module is configured to adjust a splitting window of a deserializing circuit of the FPGA after the phase traversing and adjusting module performs PLL phase adjustment according to the target PLL phase and before the FPGA performs splitting output on the sampled data, so that a clock word deserialized by the deserializing circuit conforms to a standard clock word, where the standard clock word is a clock word defined by an interface protocol corresponding to the high-speed serial signal.
In one embodiment, the bit period of the high-speed serial signal is equal to half the clock period of the associated clock.
In one embodiment, the apparatus is based on a universal resource implementation of an FPGA.
In a third aspect, the present invention provides an electronic device, including an FPGA, where the FPGA is configured to implement the method steps described in any one of the methods for automatically correcting a sampling phase of a high-speed serial signal.
In the method for automatically correcting the sampling phase of the high-speed serial signal, the continuous sampling is carried out on the associated clock of the high-speed serial signal, and meanwhile, the PLL phase of the sampling clock is traversed to obtain clock words corresponding to the PLL phases respectively; determining a target phase of the PLL corresponding to the clock word with the lowest error rate by counting the error rate of each clock word; performing PLL phase adjustment according to the target PLL phase to sample the high-speed serial signal using the phase-adjusted sampling clock; the method has the advantages that strict layout and wiring constraint is not required to be applied, and a controllable delay line is not required to be manually applied to the IO side of the sampled signal for compensation, so that the receiving application of the high-speed serial signal using the associated clock becomes simple and reliable, the problems in the prior art are solved, and the method can be realized by utilizing the conventional universal resources in the FPGA device.
Drawings
FIG. 1 is a flow chart of a method for automatically correcting sampling phase of a high-speed serial signal according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a method of an embodiment of the present invention applied to LVDS sampling;
FIG. 3 is a schematic diagram of a method of an embodiment of the present invention applied to TMDS sampling;
FIG. 4 is a schematic diagram of a high speed serial signal having a data word period equal to the clock period of the random access clock;
FIG. 5 is a schematic diagram of a high speed serial signal having a bit period equal to half of the clock period of the random access clock;
fig. 6 is a schematic diagram of an apparatus for automatically correcting sampling phase of a high-speed serial signal applied to an FPGA according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In order to solve the technical problems in the background art, the embodiment of the invention provides a method and a device for automatically correcting a sampling phase of a high-speed serial signal and electronic equipment.
Firstly, a method for automatically correcting sampling phase of a high-speed serial signal provided by the embodiment of the invention is described in detail, the method is applied to an FPGA, as shown in fig. 1, and the method comprises the following steps:
s10: and continuously sampling the associated clock of the high-speed serial signal, and traversing the PLL phases of the sampling clock to obtain a group of clock word data corresponding to each PLL phase.
The high-speed serial signal and the associated clock thereof can be sent to the FPGA by an external device/chip through a high-speed serial interface; as illustrated in fig. 2 and 3, the high-speed serial signal may include: LVDS or TMDS from a CPU or an external sensor, of course, is not limited thereto. In fig. 2 and 3, LVDS1:7 and TMDS1:10 are two different data interfaces, respectively.
In practical application, the HDMI (high definition multimedia interface) for transmitting the high-speed video signal is composed of three pairs of TMDS and a pair of TMDS clocks, so that when the FPGA needs to receive and process the HDMI signal, the method of the embodiment of the present invention can be used.
After the external device/chip sends the high-speed serial signal and the associated clock thereof to the FPGA through the high-speed serial interface, the FPGA samples the associated clock under the control of the sampling clock, and then the built-in deserializing circuit is utilized to deserialize the clock data obtained by sampling, so that a group of clock words CLKWD is obtained, and the group of clock words are also called as CLKWD data. The method comprises the steps of traversing the PLL phases of sampling clocks, setting the action time of each PLL phase to be one sampling period, and enabling the sampling clocks under different PLL phases to just complete sampling of one period under the current phase, so that a group of clock word data corresponding to each PLL phase can be obtained, wherein each group of clock word comprises a clock word of one sampling period.
S20: and determining the target phase of the PLL corresponding to at least one group of clock words with the lowest error rate by counting the error rate of each group of clock words.
Specifically, each group of clock words corresponds to a sampling period, in an ideal case, the clock words in the sampling period are fixed, and in an actual link, the sampling result of the clock words is changed due to factors such as poor sampling point positions, signal link interference and the like, so that the error rate of the group of clock words can be calculated by counting abnormal clock words in the group of clock words.
In practical applications, the clock word with the lowest bit error rate may be more than one group, which is likely to be caused by sampling the PLL phases corresponding to the groups of clock words near the midpoint of the signal eye of the associated clock. Since there is more than one set of clock words with the lowest bit error rate, there are a variety of specific implementations of determining the target PLL phase in this step.
For example, in one implementation, the PLL phase corresponding to any one of the at least one set of clock words having the lowest bit error rate may simply be taken as the target PLL phase.
In another implementation manner, based on the above implementation manner, the distribution of PLL phases corresponding to each set of clock words with the lowest error rate may be further counted, so that the PLL phase with the distribution position at the middle position is selected as the target PLL phase.
S30: PLL phase adjustment is performed according to the target PLL phase to sample the high-speed serial signal with the phase-adjusted sampling clock.
It will be understood that traversing the PLL phase in step S10 is a temporary analog adjustment of the PLL phase, and in step S30, the PLL phase is actually adjusted according to the target PLL phase, that is, in step S30, the PLL phase of the FPGA is adjusted to the target PLL phase, so that the high-speed serial signal is sampled with the sampling clock after the phase adjustment.
In addition, in practical application, since the DATA of the high-speed serial signal is composed of a plurality of bits, after the high-speed serial signal is sampled by using the sampling clock after phase adjustment, the deserializing circuit of the FPGA is required to correctly divide the serial sampling DATA, so that the FPGA can deserialize and output the parallel correct DATA, otherwise, the obtained sampling DATA is presented as an error combination of the tail of the previous DATA and the head of the new DATA. Therefore, after PLL phase adjustment is performed according to the target PLL phase, the FPGA samples the high-speed serial signal using the phase-adjusted sampling clock to obtain a set of serial sampling data, so that the correctness of the sampling data is ensured first. The FPGA then further uses the deserializer to segment the serial sample DATA to output parallel DATA.
In the method for automatically correcting the sampling phase of the high-speed serial signal, provided by the embodiment of the invention, the PLL phase of the sampling clock is traversed while the following clock of the high-speed serial signal is continuously sampled, so that clock words corresponding to the PLL phases are obtained; determining a target phase of the PLL corresponding to the clock word with the lowest error rate by counting the error rate of each clock word; PLL phase adjustment is performed according to the target PLL phase to sample the high-speed serial signal with the phase-adjusted sampling clock. The above process does not need to apply strict layout and wiring constraint and manually apply controllable delay lines to the IO side of the sampled signal to compensate, so that the embodiment of the invention makes the receiving application of the high-speed serial signal using the random clock simple and reliable, and solves the problems existing in the prior art.
In one embodiment, when the data word period of the high-speed serial signal is equal to the clock period of the associated clock, the method for automatically correcting the sampling phase of the high-speed serial signal according to the embodiment of the present invention may further include the following steps:
after the PLL phase adjustment is performed according to the target PLL phase and before the sampling data is sliced and output, a slicing window of a deserializing circuit of the FPGA is adjusted so that a clock word which is deserialized by the deserializing circuit accords with a standard clock word, and the standard clock word is a clock word defined by an interface protocol corresponding to the high-speed serial signal.
For the case that the data word period of the high-speed serial signal is equal to the clock period of the following clock, since the following clock is actually a low-speed clock, the low-speed following clock needs to be multiplied to the high-frequency serial data frequency through the PLL and then used for sampling the data, and at this time, the deserializing circuit needs to determine a slicing window for slicing the serial data by referring to the clock word of the low-speed clock.
As shown in FIG. 4, B0-B7 constitute a complete DATA DATA of the high-speed serial signal DATAIN, denoted as B [7:0], which is seen to have a period equal to the clock period of the random access clock CLKIN. As can be seen from fig. 4, since the DATA period of the high-speed serial signal is equal to the clock period of the associated clock, the CLKWD and the DATA deserialized by the FPGA have consistency in phase relationship, so that the correct DATA can be recovered as long as the correct CLKWD is recovered.
However, after performing PLL phase adjustment according to the target PLL phase, even though serial sampling DATA has ensured that sampling is correct, since the slicing window of the deserializing circuit is unchanged, the clock word that is being deserialized based on the old slicing window may still be erroneous, and the DATA that the corresponding deserializing circuit deserializes using the slicing window is also erroneous. Therefore, the splitting window of the deserializing circuit needs to be adjusted by referring to the standard clock word, so that the clock word which is deserialized by the deserializing circuit accords with the standard clock word, and the parallel DATA obtained after the serial sampling DATA is split by the deserializing circuit can be correct.
Taking the standard LVDS1:7 as a common example in video transmission, the standard CLKWD is 1100011, if the segmentation window is set to be unsuitable, the CLKWD may be incorrectly de-serialized to 1110001, 1111000, 0111100, 0011110, 0001111, 1000111, and the de-serializer circuit correspondingly recovers the DATA and will be accordingly incorrect. Therefore, the splitting window of the deserializing circuit of the FPGA needs to be adjusted so that the clock word deserialized by the deserializing circuit accords with the standard clock word, and at the moment, the current splitting window is used for splitting the serial adopted DATA, so that the correct DATA can be ensured to be recovered.
In practical applications, besides the case where the data word period of the high-speed serial signal is equal to the clock period of the random access clock, another case is where the bit period of the high-speed serial signal is equal to half the clock period of the random access clock, as shown in fig. 5. In this case, each bit of the high-speed serial signal corresponds to a rising edge or a falling edge of the associated clock, the associated clock is deserialized into a combination similar to 01010101 by the FPGA, and the corresponding relationship between the clock word CLKWD and the DATA word DATA in phase is difficult to determine, so that the DATA slicing does not depend on an accurate clock word any more, but a certain cooperation is required to be given on the transmitted DATA by the transmitting end, and the high-speed serial signal is transmitted by using a DATA packet with a preamble; specifically, the transmitting end continuously transmits a small section of special code similar to CLKWD and capable of being identified, namely a Preamble code, before transmitting the valid data, and the Preamble code is followed by a start code word, wherein the start code word is used for identifying the end of the Preamble code and the beginning of the valid data; therefore, when the FPGA receives serial DATA, if a string of bits conforming to the characteristics of the Preamble code is found, the Preamble code can be identified, and then the start code following the Preamble code can be utilized to determine the bit of the corresponding DATA in the serial DATA, so that effective DATA is accurately sampled and segmented under the target PLL phase, and correct DATA is recovered. It should be noted that, in this case, the sampling and slicing modes of the high-speed serial signal are not different from those in the prior art, but the sampling of the high-speed serial signal in the embodiment of the present invention is performed in the corrected target PLL phase, so that the DATA output by the FPGA using the method of the embodiment of the present invention is more reliable.
In summary, the method for automatically correcting the sampling phase of the high-speed serial signal provided by the embodiment of the invention does not need to apply strict layout and wiring constraint or manually apply a controllable delay line to the IO side of the sampled signal for compensation, so that the receiving application of the high-speed serial signal using the associated clock becomes simple and reliable, and the problems in the prior art are solved.
The method of the embodiment of the invention can be realized by utilizing the conventional universal resources in the FPGA device. Specifically, the receiving and sampling of the random access clock and the high-speed serial signal is realized by the PLL and the deserializing circuit in the FPGA. The implementation of the adjustment of the phase of the PLL, the statistics of the error rate of the clock word, the adjustment of the segmentation window of the deserializing circuit and other logic expressions can be performed based on the logic slice array of the FPGA, so that the embodiment of the invention realizes the automatic adjustment and the reliable receiving of the high-speed serial signal sampling by using universal FPGA resources.
Based on the same inventive concept, the embodiment of the invention also provides a device for automatically correcting the sampling phase of a high-speed serial signal, which is applied to an FPGA, and is shown in fig. 6, and the device comprises: the system comprises a phase traversing and adjusting module and a clock word statistical analysis module.
The phase traversing and adjusting module is used for traversing the PLL phase of the sampling clock of the FPGA while the FPGA continuously samples the associated Clock (CLKIN) of the high-speed serial signal (DATAIN) so that the FPGA obtains a group of clock words corresponding to the PLL phases respectively;
the clock word statistical analysis module is used for counting the error rate of each group of clock words and determining the target phase of the PLL corresponding to at least one group of clock words with the lowest error rate;
the phase traversing and adjusting module is further configured to perform PLL phase adjustment according to a target PLL phase, so that the FPGA samples the high-speed serial signal with the phase-adjusted sampling clock.
In one embodiment, when the data word period of the high-speed serial signal is equal to the clock period of the random access clock, the apparatus further comprises: a window adjustment module;
the window adjusting module is used for adjusting the segmentation window of the deserializing circuit of the FPGA after the phase traversing and adjusting module executes the phase adjustment of the PLL according to the target PLL phase and before the FPGA segments and outputs the sampling data, so that the clock word deserialized by the deserializing circuit accords with the standard clock word, and the standard clock word is the clock word defined by the interface protocol corresponding to the high-speed serial signal.
In one embodiment, the bit period of the high-speed serial signal is equal to half the clock period of the random access clock.
In one embodiment, the high-speed serial signal may include: LVDS or TMDS from a CPU or external sensor.
In practical application, the phase traversing and adjusting module, the clock word statistical analysis module and the window adjusting module can be realized by utilizing the universal resources of the FPGA.
The device for automatically correcting the sampling phase of the high-speed serial signal provided by the embodiment of the invention has the advantages that the receiving application of the high-speed serial signal using the associated clock is simple and reliable, the problems existing in the prior art are solved, and the device can be realized by utilizing the conventional universal resources in the FPGA device.
The embodiment of the invention also provides electronic equipment, which comprises an FPGA, wherein the FPGA is used for realizing the method steps of any method for automatically correcting the sampling phase of the high-speed serial signal.
The electronic device provided by the embodiment of the invention exists in various forms, including but not limited to:
(1) A mobile communication device: such devices are characterized by mobile communication capabilities and are primarily aimed at providing voice, data communications. Such terminals include: smart phones, multimedia phones, functional phones, low-end phones, etc.
(2) Ultra mobile personal computer device: such devices are in the category of personal computers, having computing and processing functions, and generally also having mobile internet access characteristics. Such terminals include: PDA (palm top computer), MID (mobile internet device), and UMPC (ultra mobile personal computer) devices, etc.
(3) Portable entertainment device: such devices may display and play multimedia content. The device comprises: audio, video players, palm game players, electronic books, and smart toys and portable car navigation devices.
(4) Other electronic devices with high-speed serial data transmission and processing requirements.
Although the present application has been described herein with respect to various embodiments, other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures and the disclosure. In the description of the present invention, the word "comprising" does not exclude other elements or steps, the "a" or "an" does not exclude a plurality, and the "a" or "an" means two or more, unless specifically defined otherwise. Moreover, some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.
For the apparatus/electronics embodiments, the description is relatively simple as it is substantially similar to the method embodiments, with reference to the description of the method embodiments in part.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. A method for automatically correcting sampling phase of a high-speed serial signal, the method comprising:
continuously sampling the associated clock of the high-speed serial signal, and traversing the PLL phases of the sampling clock to obtain a group of clock words corresponding to each PLL phase;
determining a target phase of the PLL corresponding to at least one group of clock words with the lowest error rate by counting the error rate of each group of clock words;
and performing PLL phase adjustment according to the target PLL phase to sample the high-speed serial signal by using the phase-adjusted sampling clock.
2. The method of automatically correcting a sampling phase of a high-speed serial signal according to claim 1, wherein when a data word period of the high-speed serial signal is equal to a clock period of the associated clock, the method further comprises:
and after the PLL phase adjustment is carried out according to the target PLL phase and before the sampling data is sliced and output, the slicing window of the deserializing circuit of the FPGA is adjusted so that the clock word which is deserialized by the deserializing circuit accords with a standard clock word, and the standard clock word is a clock word defined by an interface protocol corresponding to the high-speed serial signal.
3. The method of claim 1, wherein the bit period of the high-speed serial signal is equal to half the clock period of the associated clock.
4. The method of automatically correcting a sampling phase of a high-speed serial signal according to claim 1, wherein the high-speed serial signal comprises: LVDS or TMDS from a CPU or external sensor.
5. The method for automatically correcting the sampling phase of a high-speed serial signal according to claim 1, wherein the method is implemented based on the common resources of an FPGA.
6. An apparatus for automatically correcting sampling phase of a high-speed serial signal, the apparatus being applied to an FPGA, the apparatus comprising:
the phase traversing and adjusting module is used for traversing the PLL phases of the sampling clocks of the FPGA while the FPGA continuously samples the associated clocks of the high-speed serial signals, so that the FPGA obtains a group of clock words corresponding to the PLL phases respectively;
the clock word statistical analysis module is used for counting the error rate of each group of clock words and determining the target PLL phase corresponding to at least one group of clock words with the lowest error rate;
the phase traversing and adjusting module is further configured to perform PLL phase adjustment according to the target PLL phase, so that the FPGA samples the high-speed serial signal with the phase-adjusted sampling clock.
7. The apparatus for automatically correcting a sampling phase of a high-speed serial signal according to claim 6, wherein when a data word period of the high-speed serial signal is equal to a clock period of the associated clock, the apparatus further comprises: a window adjustment module;
the window adjusting module is configured to adjust a splitting window of a deserializing circuit of the FPGA after the phase traversing and adjusting module performs PLL phase adjustment according to the target PLL phase and before the FPGA performs splitting output on the sampled data, so that a clock word deserialized by the deserializing circuit conforms to a standard clock word, where the standard clock word is a clock word defined by an interface protocol corresponding to the high-speed serial signal.
8. The apparatus for automatically correcting sampling phase of a high-speed serial signal according to claim 6, wherein a bit period of the high-speed serial signal is equal to half a clock period of the associated clock.
9. The apparatus for automatically correcting a sampling phase of a high-speed serial signal according to any one of claims 6 to 8, wherein the apparatus is implemented based on a general resource of an FPGA.
10. An electronic device comprising an FPGA for implementing the method of automatically correcting the sampling phase of a high-speed serial signal of any one of claims 1-5.
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