CN117253691A - Laminated chip inductor - Google Patents

Laminated chip inductor Download PDF

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Publication number
CN117253691A
CN117253691A CN202311274946.2A CN202311274946A CN117253691A CN 117253691 A CN117253691 A CN 117253691A CN 202311274946 A CN202311274946 A CN 202311274946A CN 117253691 A CN117253691 A CN 117253691A
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CN
China
Prior art keywords
electrode
electrode coil
inductor
coil
insulating layer
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CN202311274946.2A
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Chinese (zh)
Inventor
高林
庞孔鑫
刘美文
王增琦
蔡锦伦
李肇龙
兰巧玲
余谋发
宋毅华
向湘红
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Guangdong Fenghua Advanced Tech Holding Co Ltd
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Guangdong Fenghua Advanced Tech Holding Co Ltd
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Priority to CN202311274946.2A priority Critical patent/CN117253691A/en
Publication of CN117253691A publication Critical patent/CN117253691A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/32—Insulating of coils, windings, or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/32—Insulating of coils, windings, or parts thereof
    • H01F27/323—Insulation between winding turns, between winding layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The invention discloses a laminated chip inductor, which comprises a protective layer, an insulating layer, an electrode coil and a terminal electrode; the protective layer is internally provided with a plurality of insulating layers; the insulating layer is arranged from top to bottom in a lamination manner; each insulating layer is embedded with an electrode coil with the same shape; conductive holes are formed in the insulating layers and used for connecting and conducting all electrode coils in adjacent insulating layers; the vertical distance between the insulating layer and the adjacent insulating layer is a first preset value; the shortest horizontal distance between the protective layer and the electrode coil is a second preset value; the terminal electrode is used for connecting the electrode coil with an external electrode; the first preset value is calculated according to the capacitance value of the laminated inductor and the horizontal cross-section area of the electrode coil; the second preset value is calculated from the inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil. The invention realizes the adjustment of the SRF of the inductor, and meets the self-resonance frequency adjustment of the inductor by adjusting the related design parameters of the inductor.

Description

Laminated chip inductor
Technical Field
The invention relates to the field of electronic components, in particular to a laminated chip inductor design.
Background
With the continuous development of electronic technology, the electronic products such as smart phones and tablet terminals gradually increase the quality requirements, the necessary electronic components of the electronic products also start to advance towards the directions of high frequency, miniaturization and high power, and the inductors contained in the electronic components are also technically improved, so that the electronic components gradually evolve into laminated inductors with electrode ring conductors alternately stacked at present from the previous winding of coil conductors on a magnetic core. The main parameters of the laminated inductor include inductance suitable for the application, high Self-resonant frequency (SRF-Resonant Frequency) and Quality Factor (Q). The self-resonance frequency point of the laminated inductor is determined by the inductance value and the capacitance value of the inductor. In designing a self-resonant circuit of a chip inductor, it is necessary to determine the required self-resonant frequency and then to determine the required self-resonant frequency according to the formula And calculating, wherein f is self-resonant frequency, L is inductance value, and C is capacitance value. In practical designs, it is necessary to select the appropriate inductance according to the required self-resonant frequencyAnd a capacitor to match the calculated self-resonant frequency with a frequency required for practical use; the quality factor of the inductor can be improved through design optimization, so that the high-frequency characteristic is improved to meet the requirement of multi-scene application.
In the conventional inductor design, most of the inductors are guided by the target inductance, the self-resonant frequency of the product is not considered in the design stage, and the self-resonant frequency adjustment of the inductors cannot be realized.
Disclosure of Invention
The invention provides a laminated chip inductor, which is used for realizing the adjustment of an inductor SRF and meeting the self-resonant frequency adjustment of the inductor by adjusting related design parameters of the inductor.
In order to solve the technical problems, the invention provides a laminated chip inductor, which comprises a protective layer, an insulating layer, an electrode coil and a terminal electrode;
wherein the protective layer internally contains the insulating layers;
the insulating layer is arranged from top to bottom in a lamination manner; each insulating layer is embedded with an electrode coil with the same shape; conductive holes are formed in the insulating layers and used for connecting and conducting electrode coils in adjacent insulating layers;
the vertical distance between the insulating layer and the adjacent insulating layer is a first preset value;
the shortest horizontal distance between the protective layer and the electrode coil is a second preset value;
the terminal electrode comprises a first terminal electrode and a second terminal electrode, and is used for connecting the electrode coil with an external electrode;
wherein the first preset value is calculated according to the capacitance value of the laminated chip inductor and the horizontal cross-sectional area of the electrode coil; the second preset value is calculated from the inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil.
The invention provides a laminated chip inductor, which is arranged by a plurality of insulating laminated layers embedded with electrode coil layers with the same shape, and comprises conductive holes for conducting the electrode coils in adjacent insulating layers; the electrode coils are sequentially arranged according to patterns and are connected with external electrodes through end electrodes. Wherein, the vertical distance between the insulating layer and adjacent insulating layer can be adjusted, and the distance determines the parasitic capacitance value of the laminated chip inductor; the shortest horizontal distance between the protective layer and the electrode coil set can be adjusted, and this distance determines the radius of the electrode coil, which determines the inductance value of the laminated inductor. The self-resonant frequency of the laminated inductor is further determined by the parasitic capacitance and inductance values of the laminated inductor. Therefore, the invention forms the laminated inductor with adjustable vertical distance between one insulating layer and the adjacent insulating layer and the shortest horizontal distance between the protective layer and the electrode coil group in the connecting mode, and the self-resonance frequency of the laminated inductor can be further adjusted according to the production design requirement.
As a preferred example, the first terminal electrode is located on the top insulating layer, passes through the protective layer, and is exposed to the outside of the protective layer; the second terminal electrode is positioned on the bottom insulating layer, penetrates through the protective layer and is exposed outside the protective layer.
In the preferred example, the two terminal electrodes are respectively arranged on the top insulating layer and the bottom insulating layer, so that the two terminal electrodes are used for reducing the resistance between the two terminal electrodes, and the Q value of the product is further improved.
As a preferable example, the insulating layer is provided with a conductive hole, specifically:
and the positions corresponding to the conductive holes are inconsistent with the positions corresponding to the conductive holes of the adjacent insulating layers in the vertical direction.
In the preferred example, the conductive holes which are inconsistent with the corresponding positions of the conductive holes of the adjacent insulating layers are arranged in the insulating layers, so that the inductance of the electrode coil assembly is improved.
As a preferable example, the first preset value is calculated from a capacitance value of the laminated inductor and a horizontal cross-sectional area of the electrode coil, specifically:
wherein C is a capacitance value, epsilon is a dielectric constant, k is an electrostatic force constant, d is a first preset value, and s is a horizontal cross-sectional area of the electrode coil.
The preferred example calculates the specific value of the first preset value by the above formula from the known laminated inductor model and its inductance and capacitance values.
As a preferable example, the second preset value is calculated from the inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil, specifically:
wherein mu 0 For vacuum permeability=4pi×10 -7 Mu s is the relative magnetic conductivity of the magnetic core inside the electrode coil, and mu is the relative magnetic conductivity of the magnetic core when the coil is hollow s ＝1，N 2 The k coefficient is determined by the ratio of the radius (R) of the electrode coil to the length (l) of the electrode coil.
The present preferred example calculates a specific value of the second preset value by the above formula from the known inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil.
As a preferable example, the first preset value is in a range of 10 to 50 μm.
The preferred example allows the distance between adjacent insulating layers to be increased or decreased by fine tuning the distance between adjacent insulating layers based on the standard of the laminated power inductance precision, and allows the length of the electrode coil to be increased or decreased, thereby reducing or increasing the inductance by an appropriate amount.
As a preferable example, the second preset value ranges from 1/8 to 1/12 of the length of the inductor.
In the preferred example, the distance between the protective layer and the electrode coil is finely adjusted by taking the standard of the laminated power inductance precision as a reference, so that the distance between the protective layer and the electrode coil is increased or decreased, the area of the magnetic core is increased or decreased, and the inductance is reduced or increased and adjusted by a proper amount.
As a preferable example, the protective layer is a rectangular parallelepiped insulating case.
The present preferred example protects the internal insulating layer and the electrodes from damage of the internal devices by the rectangular parallelepiped insulating case protective layer.
Each insulating layer is embedded with an electrode coil with the same shape, and the electrode coil is specifically as follows:
each electrode coil has the same shape and different directions, and the electrode coils are sequentially rotated by 90 degrees anticlockwise from top to bottom.
The electrode coil patterns are sequentially rotated by 90 degrees anticlockwise in the preferred example, so that the electrode coil groups meet the right-hand spiral rule, namely the ampere rule, and the relationship between the current and the magnetic induction line direction of the current excitation magnetic field is met.
As a preferred example, the number of electrode coils is at least 3.
The present preferred example is that by setting the number of electrode coils, the longer the length of the electrode coil group, the higher the Q value, when the number of electrode coils constituting the electrode coil group is greater.
Drawings
Fig. 1 is a perspective view of a laminated chip inductor structure according to an embodiment of the present invention;
fig. 2 is a diagram of a laminated chip inductor size label according to an embodiment of the present invention;
FIG. 3 is a diagram of the shape of an electrode coil according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a laminated structure and a sequence of a laminated inductor according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The laminated chip inductor provided by the embodiment of the invention meets the requirement of self-resonant frequency adjustment of the inductor by adjusting the related design parameters of the inductor.
Referring to fig. 1 to 2, in one embodiment of the present invention, there is provided a laminated chip inductor as shown in fig. 1, including a protective layer 1, an insulating layer 2, an electrode coil 3, and a terminal electrode 4;
wherein the protective layer 1 internally contains the insulating layers 2;
the insulating layer 2 is arranged from top to bottom in a laminated manner; each insulating layer 2 is embedded with an electrode coil 3 with the same shape; conductive holes are formed in the insulating layers 2 and are used for connecting and conducting the electrode coils 3 in the adjacent insulating layers 2;
the vertical distance between the insulating layer 2 and the adjacent insulating layer 2 is a first preset value;
the shortest horizontal distance between the protective layer 1 and the electrode coil 3 is a second preset value;
the terminal electrode 4 comprises a first terminal electrode and a second terminal electrode, and is used for connecting the electrode coil 3 with an external electrode;
wherein the first preset value is calculated according to the capacitance value of the laminated chip inductor and the horizontal cross-sectional area of the electrode coil; the second preset value is calculated from the inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil.
In the embodiment of the invention, a protective layer 1 is arranged outside the insulating layers 2 which are arranged in a laminated manner, and each insulating layer 2 is internally provided with an electrode coil 3 and contains a conductive hole for conducting the electrode coil 3 in the adjacent insulating layer 2. The vertical distance between the insulating layer and the adjacent insulating layer can be adjusted, and the distance determines the parasitic capacitance value of the laminated chip inductor; the shortest horizontal distance between the protective layer and the electrode coil set can be adjusted, and the distance determines the radius of the electrode coil, and the radius of the electrode coil determines the inductance value of the laminated inductor; the self-resonant frequency of the laminated chip inductor is further affected by the above two factors.
In the embodiment of the invention, when the model and the inductance of the inductor are determined for a certain model, the vertical distance between the insulating layer and the adjacent insulating layer and the shortest horizontal distance between the protective layer and the electrode coil group are increased or reduced through design adjustment, so that the self-resonant frequency of a fine tuning product is achieved, and the Q value of the product is improved; the standard of the laminated power inductance precision is used as a reference, and the inductance range of the M-level product is within +/-20% of the nominal value, so that the product performance meets the standard, the SRF point and the Q value of the product can be improved, the high-frequency characteristic of the product is improved, the loss is reduced, and the product performance is optimized through the fine tuning design scheme.
Therefore, the embodiment of the invention forms the laminated chip inductor with the adjustable vertical distance between one insulating layer and the adjacent insulating layer and the shortest horizontal distance between the protective layer and the electrode coil group in the connecting mode, and the self-resonant frequency of the laminated chip inductor can be further adjusted according to the production design requirement.
In one embodiment of the present invention, the first end electrode is located on the top insulating layer, passes through the protective layer and is exposed outside the protective layer; the second terminal electrode is positioned on the bottom insulating layer, penetrates through the protective layer and is exposed outside the protective layer.
Referring to fig. 1, in this embodiment of the present invention, two end electrodes respectively located on the top insulating layer and the bottom insulating layer of the inductor connect the internal electrode coil with the external electrode, so as to expand the number of electrode coils between the end electrodes, reduce the resistance between the end electrodes, and increase the Q value of the product.
In one embodiment of the present invention, the insulating layer is provided with a conductive hole, specifically:
and the positions corresponding to the conductive holes are inconsistent with the positions corresponding to the conductive holes of the adjacent insulating layers in the vertical direction.
Referring to fig. 1, in this embodiment of the present invention, conductive holes connecting electrode coils in upper and lower adjacent insulating layers are provided between each insulating layer, and may be provided at any position on the terminal electrode coil where adjacent conductive holes in the vertical direction are located differently. In practical application, the positions of the conductive holes are arranged at positions far away from the corresponding positions of the adjacent conductive holes in the horizontal direction as far as possible, so that the inductance of the inductor is improved.
In one embodiment of the present invention, the first preset value is calculated according to a capacitance value of the laminated inductor and a horizontal cross-sectional area of the electrode coil, and specifically is:
wherein C is a capacitance value, epsilon is a dielectric constant, k is an electrostatic force constant, d is a first preset value, and s is a horizontal cross-sectional area of the electrode coil.
In one embodiment of the present invention, the second preset value is calculated according to an inductance value of the laminated inductor, a horizontal cross-sectional area of the electrode coil, and a length of the electrode coil, and specifically is:
wherein mu 0 For vacuum permeability=4pi×10 -7 Mu s is the relative magnetic conductivity of the magnetic core inside the electrode coil, and mu is the relative magnetic conductivity of the magnetic core when the coil is hollow s ＝1，N 2 The k coefficient is determined by the ratio of the radius (R) of the electrode coil to the length (l) of the electrode coil.
In one embodiment of the present invention, the value range of the first preset value is 10-50 μm.
In one embodiment of the present invention, the second preset value ranges from 1/8 to 1/12 of the length of the inductor.
In this embodiment of the invention, the chip type electricity is designed in the originalIn the case of a self-resonant circuit, it is necessary to determine the desired self-resonant frequency and then to determine the desired self-resonant frequency according to the formula(f is self-resonance frequency, L is inductance value, C is capacitance value) and proper inductance and capacitance are calculated and selected so that the calculated self-resonance frequency is matched with the frequency required by practical application; the quality factor of the inductor can be improved through design optimization, so that the high-frequency characteristic is improved to meet the requirement of multi-scene application. However, when the model and the inductance of the inductor are determined for a certain model, the self-resonant frequency and the capacitance of the inductor need to be adjusted. On the premise of determining the model and the inductance of the inductor, the formula is +.>(C is capacitance value, ε is dielectric constant, k is electrostatic force constant, d is electrode coil spacing, s is electrode coil cross-sectional area) and formula +.>(μ 0 For vacuum permeability=4pi×10 -7 ，μ s Mu when the coil is hollow, the relative magnetic permeability of the magnetic core inside the electrode coil is the same s ＝1，N 2 The square of the number of turns of the electrode coil, S is the cross-sectional area of the electrode coil, l is the length of the electrode coil, and the k-factor depends on the ratio of the radius of the electrode coil to the length of the electrode coil), it can be derived that when the shortest horizontal distance between the protective layer and the electrode coil set increases, the magnetic core area S decreases, the inductance decreases, and the shortest horizontal distance between the protective layer and the electrode coil set is generally appropriately adjusted in magnitude based on the design size of the product. Because the prior process capability needs to be considered in the practical application, the conventional performance of the product needs to be ensured to meet the standard, wherein the adjustment area of the shortest horizontal distance between the protective layer and the electrode coil assembly is 1/8 to 1/12 of the length of the inductor; the vertical distance between the insulating layer and the adjacent insulating layer is increased, the coil length is increased, and the inductance is reduced, wherein the vertical distance adjustment area between the insulating layer and the adjacent insulating layer is 10-50 μm.
In one embodiment of the present invention, the protective layer is a rectangular parallelepiped insulating shell.
In one embodiment of the present invention, each of the insulating layers is embedded with an electrode coil of the same shape, specifically:
each electrode coil has the same shape and different directions, and the electrode coils are sequentially rotated by 90 degrees anticlockwise from top to bottom.
Referring to fig. 3 to 4, the electrode coil patterns of the same shape are sequentially rotated by 90 ° counterclockwise in order, so that the electrode coil set satisfies the right-hand spiral rule, i.e. ampere rule, and satisfies the relationship between the current and the direction of the induction line of the current excitation magnetic field.
In one embodiment of the invention, the number of electrode coils is at least 3.
In this embodiment of the present invention, by setting the number of electrode coils, the greater the number of electrode coils constituting the electrode coil group, the longer the length of the electrode coil group.
In one embodiment of the present invention, for a laminated inductor product 2520 (2.5 mm by 2.0 mm), when the design dimension length l=2900 μm, the inductance is 0.33uH, and the number of electrode coils in the internal electrode is 5 layers, the design of different shortest horizontal distances (d 1) between the protective layer and the electrode coils results in the following test results:
it can be seen that different distance designs between the protective layer and the electrode coil of the test product can be used, when the design distance value is increased, the inductance value is reduced, but the nominal inductance value can still be hit, the SRF point and the Q value are increased, and the loss is reduced.
In an embodiment of the present invention, for a laminated inductor product 2520 (2.5 mm×2.0 mm), the inductance is 0.24uH, and when the number of electrode coils in the inner electrode is 5 layers, the test results of the inductor product are as follows according to different distance (d 2) design schemes between adjacent insulating layers:
it can be seen that when the design distance value is increased, the inductance is reduced, the nominal inductance value can be hit, the SRF point and the Q value are increased, and the loss is reduced according to different distance design schemes between adjacent insulating layers of the test product.
The invention provides a laminated chip inductor, which is arranged by a plurality of insulating laminated layers embedded with electrode coil layers with the same shape, and comprises conductive holes for conducting the electrode coils in adjacent insulating layers; the electrode coils are sequentially arranged according to patterns and are connected with external electrodes through end electrodes. Wherein, the vertical distance between the insulating layer and adjacent insulating layer can be adjusted, and the distance determines the parasitic capacitance value of the laminated chip inductor; the shortest horizontal distance between the protective layer and the electrode coil set can be adjusted, and this distance determines the radius of the electrode coil, which determines the inductance value of the laminated inductor. The self-resonant frequency of the laminated inductor is further determined by the parasitic capacitance and inductance values of the laminated inductor. Therefore, the invention forms the laminated inductor with adjustable vertical distance between one insulating layer and the adjacent insulating layer and the shortest horizontal distance between the protective layer and the electrode coil group in the connecting mode, and the self-resonance frequency of the laminated inductor can be further adjusted according to the production design requirement.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The laminated chip inductor is characterized by comprising a protective layer, an insulating layer, an electrode coil and a terminal electrode;
wherein the protective layer internally contains the insulating layers;
the insulating layer is arranged from top to bottom in a lamination manner; each insulating layer is embedded with an electrode coil with the same shape; conductive holes are formed in the insulating layers and used for connecting and conducting electrode coils in adjacent insulating layers;
the vertical distance between the insulating layer and the adjacent insulating layer is a first preset value;
the shortest horizontal distance between the protective layer and the electrode coil is a second preset value;
the terminal electrode comprises a first terminal electrode and a second terminal electrode, and is used for connecting the electrode coil with an external electrode;
wherein the first preset value is calculated according to the capacitance value of the laminated chip inductor and the horizontal cross-sectional area of the electrode coil; the second preset value is calculated from the inductance value of the laminated inductor, the horizontal cross-sectional area of the electrode coil, and the length of the electrode coil.
2. The laminated chip inductor as recited in claim 1, wherein the first terminal electrode is located on the top insulating layer, passes through the protective layer and is exposed outside the protective layer; the second terminal electrode is positioned on the bottom insulating layer, penetrates through the protective layer and is exposed outside the protective layer.
3. The laminated chip inductor according to claim 1, wherein a conductive hole is provided in the insulating layer, specifically:
and the positions corresponding to the conductive holes are inconsistent with the positions corresponding to the conductive holes of the adjacent insulating layers in the vertical direction.
4. The laminated chip inductor according to claim 1, wherein the first preset value is calculated from a capacitance value of the laminated chip inductor and a horizontal cross-sectional area of an electrode coil, specifically:
wherein C is a capacitance value, epsilon is a dielectric constant, k is an electrostatic force constant, d is a first preset value, and s is a horizontal cross-sectional area of the electrode coil.
5. The laminated chip inductor according to claim 1, wherein the second preset value is calculated from an inductance value of the laminated chip inductor, a horizontal cross-sectional area of the electrode coil, and a length of the electrode coil, specifically:
wherein mu 0 For vacuum permeability=4pi×10 -7 Mu s is the relative magnetic conductivity of the magnetic core inside the electrode coil, and mu is the relative magnetic conductivity of the magnetic core when the coil is hollow s ＝1，N 2 The k coefficient is determined by the ratio of the radius (R) of the electrode coil to the length (l) of the electrode coil.
6. The laminated chip inductor as recited in claim 1, wherein the first predetermined value is in a range of 10 to 50 μm.
7. The laminated chip inductor as recited in claim 1, wherein the second predetermined value is in the range of 1/8 to 1/12 of the length of the inductor.
8. The laminated chip inductor as recited in claim 1, wherein the protective layer is a rectangular parallelepiped insulating case.
9. The laminated inductor as claimed in claim 8, wherein each of the insulating layers has an electrode coil embedded therein, the electrode coil having the same shape, specifically:
each electrode coil has the same shape and different directions, and the electrode coils are sequentially rotated by 90 degrees anticlockwise from top to bottom.
10. A laminated inductor according to claim 1, wherein the number of electrode coils is at least 3.
CN202311274946.2A 2023-09-28 2023-09-28 Laminated chip inductor Pending CN117253691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311274946.2A CN117253691A (en) 2023-09-28 2023-09-28 Laminated chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311274946.2A CN117253691A (en) 2023-09-28 2023-09-28 Laminated chip inductor

Publications (1)

Publication Number Publication Date
CN117253691A true CN117253691A (en) 2023-12-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311274946.2A Pending CN117253691A (en) 2023-09-28 2023-09-28 Laminated chip inductor

Country Status (1)

Country Link
CN (1) CN117253691A (en)

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