CN117253528A

CN117253528A - Reference circuit and biasing method thereof

Info

Publication number: CN117253528A
Application number: CN202311264677.1A
Authority: CN
Inventors: 杨光军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2023-12-19

Abstract

The invention discloses a reference circuit, which comprises: a reference unit, which adopts a split gate floating gate device; the split gate floating gate device includes: first and second source drain regions, a plurality of separate first gate structures having floating gates located between the first and second source drain regions, a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The reference unit is used for providing a first reference current. When the first reference current is provided, the floating gates of the first gate structures of the reference units are in an erased state, and the control gates of the reference units are connected with 0V bias so as to reduce power consumption and increase speed. The invention also provides a biasing method of the reference circuit. The invention can reduce power consumption and improve reading speed.

Description

Reference circuit and biasing method thereof

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly to a reference circuit; the invention also relates to a biasing method of the reference circuit.

Background

As shown in fig. 1, a schematic circuit diagram of a memory cell 101 of a conventional memory is shown; as shown in fig. 2, a schematic cross-sectional structure of a memory cell 101 of a conventional memory is shown; an existing memory such as a flash memory includes a plurality of memory cells 101, and an array structure of the memory is formed by arranging a plurality of the memory cells 101.

Each of the memory cells 101 employs a split gate floating gate device.

As shown in fig. 2, the split gate floating gate device includes: a first source drain region 205a and a second source drain region 206 that are symmetrical, a plurality of separate first gate structures with floating gates 104 between the first source drain region 205a and the second source drain region 205b, a second gate structure 103 between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The split gate floating gate device is a dual split gate floating gate device, and the number of first gate structures is two, indicated by reference numerals 102a and 102b, respectively.

The split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions.

A P-doped channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source drain region 205a and the second source drain region 205b are both formed on the P-type semiconductor substrate 201 and self-aligned to the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the first source drain region 205a and the second source drain region 205b or further formed by doping on the P-type semiconductor substrate 201.

The second source drain region 205b of the memory cell 101 is connected to a second source drain electrode, which is connected to the bit line BL1.

The first source drain region 205a of the memory cell 101 is connected to a first source drain electrode, which is connected to a bit line BL0.

Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.

Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.

The control gates 105 are connected to corresponding control gate lines, and the word line gate 106 is connected to the word line WL. In fig. 1, the memory cell 101 includes two first gate structures, so the control gate lines also include two control gate lines, respectively denoted by CG0 and CG1, the control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

Operations on the memory unit 101 include: taking erase, program and read as an example, 3 operation voltages are shown in table one:

list one

	CG0	WL	CG1	BL0	BL1
						Erase	-7V	8V	-7V	0V	0V
Prog	8V	1.5V	5V	5V	Idp
						Read	0V	3.5V	5V	0V	Isense

In Table one, erase represents Erase, prog represents program, write, read represents Read, idp represents bit line programming current, isense represents sense current, read current. CG0 represents the voltage of the control gate 105 of the first gate structure 102a, WL represents the voltage of the word line gate 106 of the second gate structure 103, CG1 represents the voltage of the control gate 105 of the first gate structure 102b, BL0 represents the voltage of the bit line BL0, and BL1 represents the signal of the bit line BL1.

It can be seen that, during erasing, CG0 and CG1 are both-7V, WL is 8V, and BL0 and BL1 are both 0V, so that erasing of the memory bit 'a' is realized under the effect of a larger voltage difference between CG0 and WL; typically, the voltages of CG1 and WL will also erase the memory bit corresponding to floating gate 104 in first gate structure 102 b.

When programming, i.e. writing, WL is 1.5V and CG1 bit is 5V, channels controlled by the second gate structure 103 and the first gate structure 102b can be turned on, CG0 is 8V, BL0 is 5V, and BL1 is added with a programming current Idp, so that the programming current Idp flows to BL0 through the channels controlled by the first gate structure 102b and the second gate structure 103, hot carriers are formed under the 5V voltage of BL0, and the hot carriers are injected into the floating gate 104 corresponding to the memory bit 'a' under the high voltage of 8V of CG 0.

In the reading process, CG0 is 0V, so that the channel of the first gate structure 102a corresponding to CG0 is completely determined by the state of the memory bit 'a', the channel controlled by the second gate structure 103 and the first gate structure 102b is turned on by 3.5V voltage of WL and 5V voltage of CG1, BL0 is 0V, namely, grounded, and BL1 can read out the reading current, namely Isense. In the sense amplifier, the sense amplifier compares the sense current Isense with the reference current to read the data.

The reference current needs to be implemented using a reference circuit, which uses a reference cell having the same structure as the memory cell 101. In the prior art reference circuit, the reference cell typically adopts a "10" state as the state for providing the reference current, for example, the floating gate of the first gate structure 102a in fig. 1 stores a signal of "1" and the floating gate of the first gate structure 102b stores a bit of "0". FIG. 3 is a schematic diagram of a sense amplifier to which a reference circuit of a conventional memory is applied; the sense amplifier includes a first current path, a second current path, and a third current path.

The reference unit 101a is disposed on the first current path.

The reference cell 101a of the reference circuit of the existing memory is identical in structure to the memory cell 101 shown in fig. 1. The floating gate 104 of the first gate structure 102a of the reference cell 101a corresponds to a storage bit 'a', and the floating gate 104 of the first gate structure 102b corresponds to a storage bit 'b'. 'a' stores information of '0' which is a programmed state, and 'b' stores information of '1' which is an erased state.

In use, the control gate 105 of the first gate structure 102a is connected to a reference control gate line RCG and is connected in parallel to a reference control gate voltage; the control gate 105 of the first gate structure 102b is grounded.

The word line gate 106 is connected to a reference word line RWL. Under the control of the voltage of the reference word line RWL and the voltage of the reference control gate line RCG, a first reference current Iref1 flowing through the reference cell 101a is formed.

The second current path and the first current path are mirror images of each other through a current mirror 301, and a second reference current Iref2 output by the second current path is a mirror image current of the first reference current Iref1. In fig. 3, the current mirror 301 is composed of PMOS transistors MP1 and MP2, wherein the PMOS transistor MP2 is directly used as the second current path.

Upon reading a selected memory cell 101, the third current path includes the selected memory cell 101, the third current path providing the cell current Ic of the selected memory cell 101.

The second current path and the third current path form a current comparison circuit and are used to compare the magnitudes of the second reference current Iref2 and the cell current Ic of the selected memory cell 101 and output a read voltage according to the comparison result. In fig. 3, the output circuit further includes an inverter 304, and the read voltage formed by current comparison is further input into the inverter 304, and the output signal of the next stage is output through the output terminal of the inverter 304. In other embodiments, the output circuit can be changed accordingly as desired.

The third current path is further provided with a first bit line adjustment unit 302a, where the first bit line adjustment unit 302a includes a first NMOS transistor MN1 and a first inverter 303a.

The drain electrode of the first NMOS transistor MN1 is connected with a data line node, and the source electrode of the first NMOS transistor MN1 is connected with a bit line node of the memory cell 101; the data line node is a connection point of the second current path and the third current path.

A decoder 303 is further connected between the source of the first NMOS transistor MN1 and the bit line node of the memory cell 101, and in fig. 3, one NMOS transistor is used to represent the decoder 303, and the corresponding NMOS transistor is turned on by the decoding signal Y, so as to implement selection of the bit line node of the corresponding memory cell 101.

The first inverter 303a is connected between the gate and the source of the first NMOS transistor MN 1.

The first current path is further provided with a second bit line adjustment unit 302b, where the second bit line adjustment unit 302b includes a second NMOS transistor MN2 and a second inverter 303b.

The drain electrode of the second NMOS transistor MN2 is connected to the current mirror 301.

The source of the first NMOS transistor MN1 is connected with the bit line node of the reference unit 101a.

The second inverter 303b is connected between the gate and the source of the second NMOS transistor MN 2.

As shown in fig. 4, a signal curve of the reference circuit of the existing memory shown in fig. 3; the signal CE is a chip enabling signal, and when the signal CE is at a high level, the memory performs a read operation, namely a read flash; when the signal CE is low, the CPU operates as CPU exe.

The signal RCG/RWL includes a curve of the signal RCG and a curve of the signal RWL, which are different in magnitude but identical in variation, and therefore are represented by the same curve. The curve of the signal RCG is the curve of the reference control gate voltage applied to the reference control gate line RCG in fig. 3, and the curve of the signal RWL is the reference word line voltage applied to the reference word line RWL in fig. 3.

It can be seen that at each pulse of signal CE, signals RCG and RWL switch, which causes an increase in power consumption and a slow reading speed due to parasitic resistance and capacitance on reference control gate line RCG.

Disclosure of Invention

The invention provides a reference circuit which can reduce power consumption and improve reading speed. The invention also provides a biasing method of the reference circuit.

The reference circuit provided by the invention comprises: the reference unit adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region and a second source drain region, a plurality of separated first gate structures with floating gates positioned between the first source drain region and the second source drain region, and a second gate structure positioned between the first gate structures; the first grid structure is provided with a control grid positioned on the top of the floating gate.

The reference unit is used for providing a first reference current.

When the first reference current is provided, the floating gate of each first gate structure of the reference unit is in an erased state, and each control gate of the reference unit is connected with 0V bias so as to reduce power consumption and increase speed.

In a further development, the first reference current is used as a reference current for a cell current of a memory cell of a memory, and is used for comparing with the cell current of the memory cell during a reading process of the memory cell to determine a memory state of the memory cell.

A further improvement is that the structure of the reference cell is identical to the structure of the memory cell.

And each control gate of the memory unit is independently connected with a corresponding control gate voltage.

The separation gate floating gate device is a double separation gate floating gate device, and the number of the first gate structures is two.

A further improvement is that the memory comprises a memory array and sense amplifiers, the memory cells being located in the memory array.

The sense amplifier includes a first current path, a second current path, and a third current path.

The reference unit is disposed on the first current path.

The second current path and the first current path are mirror images through a current mirror, and the second reference current output by the second current path is mirror image current of the first reference current.

The third current path includes the selected memory cell when the selected memory cell is read, the third current path providing the cell current of the selected memory cell.

The second current path and the third current path form a current comparison circuit and are used for comparing the second reference current with the magnitude of the cell current of the selected memory cell and outputting a read voltage according to the comparison result.

The further improvement is that each first gate structure is formed by superposing a tunneling dielectric layer, the floating gate, a control gate dielectric layer and the control gate.

The second grid structure is formed by overlapping a word grid medium layer and a word grid.

In a further improvement, a first bit line adjusting unit is further arranged on the third current path, and the first bit line adjusting unit comprises a first NMOS tube and a first inverter.

The drain electrode of the first NMOS tube is connected with a data line node, and the source electrode of the first NMOS tube is connected with a bit line node of the memory cell; the data line node is a connection point of the second current path and the third current path.

The first inverter is connected between the grid electrode and the source electrode of the first NMOS tube.

In a further improvement, a second bit line adjusting unit is further arranged on the first current path, and the second bit line adjusting unit comprises a second NMOS tube and a second inverter.

And the drain electrode of the second NMOS tube is connected with the current mirror.

The source electrode of the first NMOS tube is connected with the bit line node of the reference unit.

The second inverter is connected between the grid electrode and the source electrode of the second NMOS tube.

In order to solve the technical problems, in the bias method of the reference circuit provided by the invention, the reference circuit comprises a reference unit, and the reference unit adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region and a second source drain region, a plurality of separated first gate structures with floating gates positioned between the first source drain region and the second source drain region, and a second gate structure positioned between the first gate structures; the first grid structure is provided with a control grid positioned at the top of the floating gate; the bias method for obtaining the first reference current by the reference unit comprises the following steps:

the reference cell is programmed to set the floating gate of each of the first gate structures of the reference cell to a programmed state.

The reference cell is erased to set the floating gate of each of the first gate structures of the reference cell to an erased state.

And each control gate of the reference unit is connected with 0V bias so as to reduce power consumption and increase speed.

The reference unit is disposed on the first current path.

The drain electrode of the first NMOS tube is connected with a data line node, and the source electrode of the first NMOS tube is connected with a bit line node of the memory cell; the data line node is a connection point of the second current path and the third current path;

In the reference circuit, the split gate floating gate device is adopted as the reference unit, and floating gates of all first gate structures of the reference unit are set to be in an erasure state, so that during reading, all control gates of reference voltage are connected with 0V bias to obtain first reference current, and the control gates are 0V, so that charging and discharging of control gate lines are not required during reading, the power consumption can be reduced, the speed can be improved, and the power consumption and the speed can be improved simultaneously.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a schematic circuit diagram of a memory cell of a conventional memory;

FIG. 2 is a schematic cross-sectional structure of a memory cell of a conventional memory;

FIG. 3 is a schematic diagram of a sense amplifier to which a reference circuit of a conventional memory is applied;

FIG. 4 is a signal plot of a reference circuit of the prior art memory shown in FIG. 3;

FIG. 5A is a schematic circuit diagram of a reference unit of a reference circuit according to an embodiment of the present invention;

FIG. 5B is a schematic cross-sectional view of a reference cell of a reference circuit according to an embodiment of the invention;

fig. 6 is a schematic diagram of a sense amplifier to which the reference circuit of the embodiment of the present invention is applied.

Detailed Description

As shown in fig. 5A, a circuit structure of a reference unit 101b of the reference circuit according to the embodiment of the invention is shown; FIG. 5B is a schematic diagram showing a cross-sectional structure of a reference cell 101B of a reference circuit according to an embodiment of the invention; FIG. 6 is a schematic diagram of a sense amplifier to which the reference circuit of the embodiment of the present invention is applied; the reference circuit of the embodiment of the invention comprises: a reference cell 101b, wherein the reference cell 101b adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region 205a and a second source drain region 205b, a plurality of separate first gate structures having floating gates 104 between said first source drain region 205a and said second source drain region 205b, a second gate structure 103 between said first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The reference cell 101b is configured to provide a first reference current Iref1.

When the first reference current Iref1 is supplied, the floating gates 104 of the first gate structures of the reference cells 101b are in an erased state, i.e., '1' state, and the control gates 105 of the reference cells 101b are biased with 0V to reduce power consumption and speed.

In the embodiment of the present invention, the first reference current Iref1 can be adjusted by adjusting the erase depth of the floating gate 104 of each of the first gate structures of the reference cell 101b, that is, the erase depth of the floating gate 104 of each of the first gate structures of the reference cell 101b can be set according to the requirement of the first reference current Iref1.

In the embodiment of the present invention, the first reference current Iref1 is used as the reference current of the cell current Ic of the memory cell 101 of the memory, and during the reading process of the memory cell 101, the first reference current Iref1 is used to compare with the cell current Ic of the memory cell 101 to determine the memory state of the memory cell 101.

In the embodiment of the present invention, the structure of the reference unit 101a is the same as the structure of the memory unit 101.

Each control gate 105 of the memory cell 101 is independently connected to a corresponding control gate 105 voltage. The structure of the memory cell 101 is shown in fig. 1 and 2.

The split gate floating gate device is a dual split gate floating gate device, the number of the first gate structures is two, and the two first gate structures are denoted by reference numerals 102a and 102b, respectively. In fig. 5A, the floating gate 104 of the first gate structure 102a corresponds to a storage bit 'a', and the floating gate 104 of the first gate structure 102b corresponds to a storage bit 'b'. A 1 in brackets after the storage bit 'a' is indicated as storage information of the storage bit 'a' being an '1', i.e., an erased state, and a 1 in brackets after the storage bit 'b' is indicated as storage information of the storage bit 'b' being an '1'.

In fig. 5A, the control gate 105 of the first gate structure 102a is connected to a reference control gate line RCG0, the control gate 105 of the first gate structure 102b is connected to a reference control gate line RCG1, and the word line gate 106 is connected to a reference word line RWL. In the embodiment of the invention, RCG0 and RCG1 are both connected with 0V. This can achieve the following benefits:

firstly, the provision of Iref1 can be ensured, because the memory bits 'a' and 'b' are both in the erased state, so that when both RCG0 and RCG1 are connected to 0V, the channel regions controlled by the bottoms of the first gate structures 102a and 102b are turned on; therefore, under the condition that the voltage applied to the reference word line RWL turns on the channel region controlled by the second gate structure 103, the entire reference cell 101b is turned on, so that Iref1 can be formed.

Secondly, since the reference control gate lines RCG0 and RCG1 are both connected with 0V, there is no need to additionally raise the high level for the reference control gate lines RCG0 and RCG1, but if the high level is provided for the reference control gate lines RCG0 or RCG1, there will be a voltage level switching of the reference control gate line RCG0 or RCG1 during the reading process, and the reference control gate line RCG0 or RCG1 has parasitic resistance and capacitance, and this repeated voltage switching will generate larger power consumption and larger delay for reading, thereby reducing the reading speed; in the embodiment of the invention, since the reference control gate lines RCG0 and RCG1 are both connected with 0V, the level switching of the reference control gate line RCG0 or RCG1 does not exist, and the power consumption and the delay caused by the level switching do not exist, so that the power consumption can be reduced and the reading speed can be improved at the same time.

In some embodiments, the split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions.

The first source drain region 205a and the second source drain region 205b are connected to corresponding bit lines, and two corresponding bit lines are respectively indicated by a reference BL0 and a reference BL1.

The second gate structure 103 is formed by overlapping the medium layer 204 of the word line grating 106 and the word line grating 106.

As shown in fig. 1, the control gate line CG0 of the control gate 105 of the first gate structure 102a of the memory cell 101, the control gate line CG1 of the control gate 105 of the first gate structure 102b, the word line gate 106 is connected to the word line WL.

In an embodiment of the present invention, the memory includes a memory array and a sense amplifier, and the memory cell 101 is located in the memory array.

The reference unit 101b is disposed on the first current path.

The second current path and the first current path are mirror images of each other through a current mirror 301, and a second reference current Iref2 output by the second current path is a mirror image current of the first reference current Iref1. In fig. 6, the current mirror 301 is composed of PMOS transistors MP1 and MP2, wherein the PMOS transistor MP2 directly serves as the second current path.

The second current path and the third current path form a current comparison circuit and are used to compare the magnitudes of the second reference current Iref2 and the cell current Ic of the selected memory cell 101 and output a read voltage according to the comparison result. In fig. 6, the output circuit further includes an inverter 304, and the read voltage formed by current comparison is further input into the inverter 304, and the output signal of the next stage is output through the output terminal of the inverter 304. In other embodiments, the output circuit can be changed accordingly as desired.

The source of the first NMOS transistor MN1 is connected with the bit line node of the reference unit 101b.

In the reference circuit of the embodiment of the invention, the split gate floating gate device is adopted as the reference unit 101b, and the floating gates 104 of the first gate structures of the reference unit 101b are all set to be in an erased state, so that when reading, the first reference current Iref1 can be obtained by connecting 0V bias to each control gate 105 of the reference voltage, and because the control gate 105 is 0V, the control gate 105 line does not need to be charged or discharged in the reading process, thereby not only reducing the power consumption, but also improving the speed, and further realizing the simultaneous improvement of the power consumption and the speed.

In the bias method of the reference circuit in the embodiment of the invention, the reference circuit comprises: a reference cell 101b, wherein the reference cell 101b adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region 205a and a second source drain region 205b, a plurality of separate first gate structures having floating gates 104 between said first source drain region 205a and said second source drain region 205b, a second gate structure 103 between said first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The bias method for obtaining the first reference current Iref1 comprises the following steps:

the reference cell 101b is programmed to set the floating gate 104 of each of the first gate structures of the reference cell 101b to a programmed state.

The reference cell 101b is erased to set the floating gate 104 of each of the first gate structures of the reference cell 101b to an erased state.

Each of the control gates 105 of the reference cells 101b is biased with 0V to reduce power consumption and increase speed.

The first reference current Iref1 is used as a reference current for the cell current Ic of the memory cell 101 of the memory, and the first reference current Iref1 is used to compare with the cell current Ic of the memory cell 101 to determine the memory state of the memory cell 101 during the reading of the memory cell 101.

In the method of the embodiment of the present invention, the first reference current Iref1 can be adjusted by adjusting the erase depth of the floating gate 104 of each of the first gate structures of the reference cell 101b, that is, the erase depth of the floating gate 104 of each of the first gate structures of the reference cell 101b can be set according to the requirement of the first reference current Iref1.

In the method of the embodiment of the present invention, the structure of the reference unit 101a is the same as the structure of the memory unit 101.

In fig. 5A, the control gate 105 of the first gate structure 102a is connected to a reference control gate line RCG0, the control gate 105 of the first gate structure 102b is connected to a reference control gate line RCG1, and the word line gate 106 is connected to a reference word line RWL. In the method of the embodiment of the invention, RCG0 and RCG1 are connected with 0V. This can achieve the following benefits:

Secondly, since the reference control gate lines RCG0 and RCG1 are both connected with 0V, there is no need to additionally raise the high level for the reference control gate lines RCG0 and RCG1, but if the high level is provided for the reference control gate lines RCG0 or RCG1, there will be a voltage level switching of the reference control gate line RCG0 or RCG1 during the reading process, and the reference control gate line RCG0 or RCG1 has parasitic resistance and capacitance, and this repeated voltage switching will generate larger power consumption and larger delay for reading, thereby reducing the reading speed; in the method of the embodiment of the invention, the reference control grid lines RCG0 and RCG1 are connected with 0V, so that the level switching of the reference control grid line RCG0 or RCG1 does not exist, and the power consumption and the time delay generated by the level switching do not exist, thereby simultaneously reducing the power consumption and improving the reading speed.

In the method of the embodiment of the present invention, the memory includes a memory array and a sense amplifier, and the memory cell 101 is located in the memory array.

The reference unit 101b is disposed on the first current path.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. A reference circuit, comprising: the reference unit adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region and a second source drain region, a plurality of separated first gate structures with floating gates positioned between the first source drain region and the second source drain region, and a second gate structure positioned between the first gate structures; the first grid structure is provided with a control grid positioned at the top of the floating gate;

the reference unit is used for providing a first reference current;

2. The reference circuit of claim 1, wherein: the first reference current is used as a reference current of a cell current of a memory cell of a memory, and is used for comparing with the cell current of the memory cell to determine a memory state of the memory cell during reading of the memory cell.

3. The reference circuit of claim 2, wherein: the structure of the reference unit is the same as that of the storage unit;

4. A reference circuit as claimed in claim 3, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.

5. A reference circuit as claimed in claim 3, wherein: the memory comprises a memory array and a sense amplifier, wherein the memory unit is positioned in the memory array;

the sense amplifier includes a first current path, a second current path, and a third current path;

the first current path is provided with the reference unit;

the second current path and the first current path are mirror images through a current mirror, and the second reference current output by the second current path is the mirror image current of the first reference current;

the third current path includes the selected memory cell when the selected memory cell is read, the third current path providing the cell current of the selected memory cell;

6. A reference circuit as claimed in claim 3, wherein: each first gate structure is formed by superposing a tunneling dielectric layer, the floating gate, a control gate dielectric layer and the control gate;

7. The reference circuit of claim 5, wherein: the third current path is also provided with a first bit line adjusting unit, and the first bit line adjusting unit comprises a first NMOS tube and a first inverter;

8. The reference circuit of claim 7, wherein: the first current path is also provided with a second bit line adjusting unit, and the second bit line adjusting unit comprises a second NMOS tube and a second inverter;

the drain electrode of the second NMOS tube is connected with the current mirror;

the source electrode of the first NMOS tube is connected with a bit line node of the reference unit;

9. The bias method of the reference circuit is characterized in that the reference circuit comprises a reference unit, and the reference unit adopts a split gate floating gate device; the split gate floating gate device includes: a first source drain region and a second source drain region, a plurality of separated first gate structures with floating gates positioned between the first source drain region and the second source drain region, and a second gate structure positioned between the first gate structures; the first grid structure is provided with a control grid positioned at the top of the floating gate; the bias method for obtaining the first reference current by the reference unit comprises the following steps:

programming the reference cell to set the floating gate of each of the first gate structures of the reference cell to a programmed state;

erasing the reference cell to set the floating gate of each of the first gate structures of the reference cell to an erased state;

10. The method of biasing a reference circuit of claim 9, wherein: the first reference current is used as a reference current of a cell current of a memory cell of a memory, and is used for comparing with the cell current of the memory cell to determine a memory state of the memory cell during reading of the memory cell.

11. The method of biasing a reference circuit of claim 10, wherein: the structure of the reference unit is the same as that of the storage unit;

12. The method of biasing a reference circuit of claim 11, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.

13. The method of biasing a reference circuit of claim 11, wherein: the memory comprises a memory array and a sense amplifier, wherein the memory unit is positioned in the memory array;

the first current path is provided with the reference unit;

14. The method of biasing a reference circuit of claim 11, wherein: each first gate structure is formed by superposing a tunneling dielectric layer, the floating gate, a control gate dielectric layer and the control gate;

15. The method of biasing a reference circuit of claim 13, wherein: the third current path is also provided with a first bit line adjusting unit, and the first bit line adjusting unit comprises a first NMOS tube and a first inverter;

16. The method of biasing a reference circuit of claim 15, wherein: the first current path is also provided with a second bit line adjusting unit, and the second bit line adjusting unit comprises a second NMOS tube and a second inverter;