CN117252135A

CN117252135A - Prototype verification system of system on crystal

Info

Publication number: CN117252135A
Application number: CN202310817090.2A
Authority: CN
Inventors: 刘战伟; 赵豪兵; 虎艳宾; 王偲柠; 邵阳雪; 魏帅; 孙立
Original assignee: Songshan Laboratory
Current assignee: Songshan Laboratory
Priority date: 2023-07-04
Filing date: 2023-07-04
Publication date: 2023-12-19

Abstract

A prototype verification system for a system-on-chip is disclosed. By arranging a first chipset and a subsystem in the prototype verification system, the first chipset is provided with a plurality of first field programmable gate arrays, each first field programmable gate array implements all or part of the logic functions of one or more core grains of the on-chip system by running a first bitstream file, and the subsystem implements an extended function. Thus, a prototype verification system of the on-chip system is built through the first field programmable gate array, and the prototype verification of the on-chip system is realized.

Description

Prototype verification system of system on crystal

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a prototype verification system of a system-on-chip.

Background

The software defined system on chip (Software Defined System on Wafer, SDSoW) is also called a system on chip, and is a complete wafer substrate for interconnecting all modules in the system, and a wafer densely covered with various core particles is used for realizing a complete system, so that the system has extremely strong flexibility and expandability. If the on-chip system is verified through the prototype verification system, the production efficiency of the on-chip system can be greatly improved. A complete prototype verification system for a system-on-a-chip is currently lacking.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a prototype verification system for a system-on-chip, so as to implement prototype verification of the system-on-chip.

In a first aspect, an embodiment of the present invention provides a prototype verification system of a system-on-chip, the prototype verification system comprising:

a first chipset comprising a plurality of first field programmable gate arrays for running a first bitstream file to implement logic functions of the system on a chip; and

at least one subsystem connected with the first chip set for realizing the expansion function;

wherein the system on a die comprises a plurality of die, and a first field programmable gate array is used for realizing all or part of logic functions of one or more die of the system on a die.

In some embodiments, the extended functionality includes functionality corresponding to at least one of a digital signal processing module, a central processing unit, a graphics processor, and a network processor.

In some embodiments, the subsystem comprises:

the second chipset includes at least one second field programmable gate array for running a second bit stream file to implement a corresponding extended function.

In some embodiments, the subsystem includes at least one of a digital signal processing module, a central processing unit, a graphics processor, and a network processor.

In some embodiments, the prototype verification system further comprises:

at least one interface is connected between the subsystem and the first field programmable gate array.

In some embodiments, the prototype verification system further comprises:

and the interconnection line is used for interconnecting the first field programmable gate arrays in a chip and/or between chips and interconnecting the first field programmable gate arrays with the interface.

In some embodiments, the first field programmable gate array includes at least one functional sub-module for implementing all or part of the logic functions of one die of the system on a die.

In some embodiments, the model number and number of the first field programmable gate array are determined based on the logic size of the die of the system-on-chip and the interconnect requirements of the die.

In some embodiments, the first bit stream file and the second bit stream file include configuration information for programmable logic units and routing resources.

In some embodiments, the interface comprises at least one of a switch interface, a high-speed interconnect technology interface, a high-speed serial computer expansion bus standard interface, and an ethernet interface.

According to the technical scheme, the first chip set and the subsystem are arranged in the prototype verification system, the first chip set is provided with a plurality of first field programmable gate arrays, each first field programmable gate array is used for realizing all or part of logic functions of one or more core grains of the on-chip system by running a first bit stream file, and the subsystem is used for realizing an expansion function. Thus, a prototype verification system of the on-chip system is built through the first field programmable gate array, and the prototype verification of the on-chip system is realized.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a prototype verification system according to a first embodiment of the invention;

FIG. 2 is a schematic diagram of a prototype verification system according to a second embodiment of the invention;

FIG. 3 is a schematic diagram of a prototype verification system according to a third embodiment of the invention;

FIG. 4 is a schematic diagram of a prototype verification system according to a fourth embodiment of the invention;

FIG. 5 is a schematic diagram of a prototype verification system according to a fifth embodiment of the invention;

fig. 6 is a flow chart of a verification method of a system on a chip according to an embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

The software defined system on chip (Software Defined System on Wafer, SDSoW) is also called as a system on chip, and is a complete wafer substrate used as an interconnection base for each module in the system, and a wafer densely covered with various core grains is used to realize a complete system, and the connection between each module supports software definition, or even the function of each module itself. The on-chip system breaks through the limitation of the technology on improving the chip integration level from the system angle, and has extremely strong flexibility and expandability. On the wafer interconnection substrate, all the core particles needed in the system are connected together, so that high-density integration is realized. A core (Chiplet) refers to a prefabricated, functional, combinable, integrated Chiplet. The core technology is to package small chips with different mature technologies and different modules, and integrate the small chips into a complete chip. That is, the system on a chip adopts wafer manufacturing to manufacture a complete system with a plurality of core grains on the chip, and the system has high wire outlet density and small line loss. The wafer manufacturing has the advantages of high integration density, good economy and mature industrial chain. For example, 500 chips are integrated on one wafer, and the chip has the functions of calculation, storage, communication, interconnection interfaces and the like, but no insertion loss exists between the chip and the wafer, and the chip has a very close interconnection distance, so that the driving capability requirement on a driver is reduced, the power consumption of the chips can be reduced, and the power consumption of the whole system is reduced.

Compared with the traditional system designed based on a PCB (Printed Circuit Board, a printed circuit board) or a microsystem constructed based on advanced packaging, the system on chip has the characteristics of extremely large integration scale, extremely complex interconnection network, ultra-large density heterogeneous integration and the like. In order to realize the development of a flexible and efficient computing system on a chip, the systematic research of an architecture design method, a network on a chip, an assembly process and the like is required to be carried out, and the problems of equivalent evaluation of work performance and the like are overcome by researching the technology based on the prior device and the technology of verifying the network prototype of the system on the chip built by the PCB card.

FPGA (Field Programmable Gate Array ) is a product of further development on the basis of programmable devices such as PAL (programmable array logic ), GAL (generic array logic, general array logic) and the like. It appears as a semi-custom circuit in the application specific integrated circuit (ASIC, application Specific Integrated Circuit) field, which not only solves the deficiencies of custom circuits, but also overcomes the disadvantages of limited gate numbers of the original programmable devices.

The FPGA includes programmable input-Output Blocks (Programmable Input/Output Blocks, IOBs), programmable logic Blocks (Configurable Logic Block, CLBs), digital clock management modules, embedded block RAM (Random Access Memory ), wiring resources (interconnections), and other embedded cells. The user can configure the programmable input/output block, the programmable logic block and the like in the FPGA to meet the requirements of the user. At the same time, it also has the characteristics of static re-programmable and dynamic in-system reconfiguration, so that the function of the hardware can be modified programmatically like software.

CLBs are the basic logic units of FPGAs, the actual number and characteristics of which will vary from device to device, but each CLB contains a configurable switching matrix of 4 or 6 inputs, several selection circuits (multiplexers etc.) and flip-flops.

FPGAs can support a wide variety of I/O standards and thus can provide ideal interface bridging for system design. I/Os within an FPGA are categorized by group, i.e., the IOB is divided into groups, each of which can independently support a different I/O standard. Through flexible configuration of software, different electrical standards and I/O physical characteristics can be adapted, the magnitude of driving current can be adjusted, and the pull-up resistance and pull-down resistance can be changed.

CLBs provide logic performance, and flexible wiring resources are responsible for transferring signals between CLBs and I/os. There are several types of routing, from global low skew routing (global dedicated routing resources) designed to exclusively implement CLB interconnections (stub resources), to high speed horizontal and vertical long lines within the device (long line resources), to clocks and other global signals.

The FPGA prototype verification platform can provide the real physical interface and hardware environment necessary for debugging the chip software, which cannot be provided by the logic function simulation and formal verification. Compared with a hardware accelerator, the software of the FPGA prototype verification platform runs an order of magnitude faster. Local or some interface logic codes can run according to the frequency which is closer to the real chip, so that the debugging time of software running and the period of verification iteration are greatly shortened, and meanwhile, the parallel development and verification of software and hardware is possible. The prototype verification technology based on the FPGA has the advantages of low cost, high speed, easiness in construction and the like, and has important significance in the field of SoC (System on Chip) active verification. However, compared with SoC, the on-chip system has higher integration level and more complex functions, and the prototype verification technology of SoC is not suitable for on-chip system, and there is no complete technology for FPGA-based prototype verification system of on-chip system.

Thus, the embodiment of the invention provides a prototype verification system of a system-on-chip to verify the system-on-chip.

Fig. 1 is a schematic diagram of a prototype verification system according to a first embodiment of the invention. In the embodiment shown in fig. 1, the prototype verification system comprises a first chipset 1 and at least one subsystem. The first chipset 1 includes a plurality of first field programmable gate arrays, and the plurality of first field programmable gate arrays are used for running a first bitstream file to implement logic functions of the system on a chip. The subsystem is connected with the first chip set 1 and is used for realizing an expansion function.

Wherein the first bit stream file includes configuration information for programmable logic units and routing resources. Wherein the programmable logic unit is a basic module of a programmable logic block CLB in the first field programmable gate array.

In this embodiment, the system on chip includes a plurality of die, and a first field programmable gate array is used to implement all logic functions of one or more die of the system on chip.

Wherein, the core particle refers to a prefabricated small chip with specific functions and capable of being combined and integrated. That is, a core pellet is also understood to be a preform, which is a part of a device that is prefabricated for assembly into a system on a chip. That is, assuming that the on-chip system includes a plurality of core grains, a prefabricated member corresponding to each core grain of the on-chip system is manufactured, and the prefabricated member is packaged to obtain the on-chip system.

In this embodiment, the overall logic function of the one or more cores of the on-chip system for implementing the first field programmable gate array is specifically: a first field programmable gate array is used to implement the functionality of one die of the system on die and/or a first field programmable gate array is used to implement the functionality of multiple dies of the system on die. That is, a first field programmable gate array is used to implement the function of the N die of the system on a die, where n=1, 2,3, … …. Wherein, the whole logic function refers to the complete logic function of one core particle.

Fig. 1 illustrates that the first chipset 1 includes four first field programmable gate arrays, 11, 12, 13, and 14, respectively. It should be noted that the "first" in the first field programmable gate array according to the embodiment of the present invention is not limited to the type or model of the FPGA (Field Programmable Gate Array ) and the like, but refers to the FPGA (Field Programmable Gate Array ) for implementing the function of the core of the system on a chip.

The first field programmable gate array includes at least one functional sub-module for implementing all logic functions of one die of the system on a die. In fig. 1, each first field programmable gate array comprises a plurality of shaded blocks, wherein each shaded block represents an instantiation of one functional sub-module, i.e. one core. Instantiation of a core refers to a configuration that implements the complete logic function of a core. Taking the first field programmable gate array 11 as an example for illustration, the first field programmable gate array 11 includes six functional sub-modules, that is, the first field programmable gate array 11 is configured to implement the complete logic function of six cores.

It should be understood that, in the embodiment of the present invention, the number of the core grains that can be implemented by the first field programmable gate array is not limited, and the specific configuration may be performed according to the logic scale of the selected FPGA and the logic scale of the core grains. For example, for a smaller logic scale die, a first field programmable gate array may implement all of the logic functions of multiple dies; for larger logic scale die, a first field programmable gate array may implement all of the logic functions of a die.

Further, the prototype verification system further comprises an interconnection line for on-chip and/or inter-chip interconnection of the plurality of first field programmable gate arrays. The on-chip interconnection refers to connection between different functional sub-modules in a first field programmable gate array. Inter-chip interconnect refers to a connection between one or more different first field programmable gate arrays. Specifically, the FPGA includes programmable input-Output Blocks (Programmable Input/Output Blocks, IOBs), and according to actual application requirements, the programmable input-Output Blocks that need to be connected are connected through an interconnection line to implement intra-chip and/or inter-chip interconnection.

In testing the on-chip system, it is necessary to cooperate with other functional modules (such as DSP, CPU, GPU and NPU, etc.), whereby at least one subsystem is connected to the first chipset 1 for implementing the extended functionality. Wherein the extended functions include at least one corresponding function among a digital signal processing (DSP, digital Signal Processing) module, a central processing unit (CPU, central Processing Unit), a graphics processor (GPU, graphics processing unit), and a network processor (NPU, neural-network Processing Unit).

The prototype verification system further comprises at least one interface connected between the subsystem and the first field programmable gate array.

The interface may be a Switch interface, an SRIO (Serial Rapid I/O) interface, a PCIe (peripheral component interconnect express, high-speed Serial computer expansion bus standard) interface, an ethernet interface, or the like.

Specifically, the subsystem of the embodiment of the invention comprises at least one data processing module of DSP, CPU, GPU, NPU and the like and peripheral circuits required by the data processing module. The various subsystems may be implemented by board cards, circuits or devices, etc. Each subsystem comprises a data transmission interface, and therefore, the data transmission interface of the subsystem is connected with the interface of the prototype verification system through a data line so as to realize data interaction between the subsystem and the first chipset.

Four subsystems are illustrated in fig. 1, such as 21, 22, 23 and 24, respectively, in fig. 1. Correspondingly, the prototype verification system comprises four interfaces, 31, 32, 33 and 34 respectively shown in fig. 1, each subsystem being connected to a corresponding interface for data interaction.

It should be understood that the implementation manner and the number of the subsystems are not limited in the embodiment of the present invention, and may be specifically configured according to practical situations, for example, multiple subsystems may be in one board card, circuit or device, and for example, the subsystems may be one subsystem or multiple subsystems. Correspondingly, the number and form of the interfaces can be configured with the subsystems, and in general, one subsystem corresponds to one interface, and meanwhile, the form of the interfaces is matched with the data transmission mode of the subsystem.

Therefore, the logic function of the on-chip system is realized through the FPGA, and meanwhile, the subsystem is set to be in the form of an external sub-card, and the corresponding external sub-card can be selected for access according to actual requirements, so that the prototype verification system can be suitable for different on-chip systems, and the universality of the prototype verification system is improved.

It should be further understood that the connection between the interface in fig. 1 and the first field programmable gate array in the first chipset is only an example provided by the embodiment of the present invention, and the embodiment of the present invention does not limit a specific connection manner, and may be set according to practical situations.

The type and the number of the first field programmable gate array are determined according to the logic scale of the core grains of the system on chip and the interconnection requirement of the core grains.

Further, the embodiment of the invention provides a method for acquiring a prototype verification system of a system-on-chip, which comprises the following steps:

step S110, evaluating the logic scale of the prefabricated member of the system on a chip and the number and the speed of the high-speed transceivers required, and selecting proper FPGA models and the number of the FPGAs according to the logic scale and the number and the speed of the high-speed transceivers.

Wherein the FPGA has integrated therein high speed transceivers, e.g., GTP, GTX, GTH and GTZ, etc., wherein GTP, GTX, GTH and GTZ are different models of GT (Gigabyte Transceiver, G-bit transceiver). GT is a fixed circuit integrated inside an FPGA chip, is a serial transceiver, and has a general line speed up to Gbps. Different models of GT have different transmission speeds.

And step S120, selecting an interface in a corresponding form as an external interface according to the interface form of the subsystem to connect the system, and determining the number of the required high-speed transceivers according to the resources of the high-speed transceivers integrated in the FPGA.

The method specifically includes determining the number of high-speed transceivers required according to the resources of the high-speed transceivers integrated in the FPGA, determining the requirement of the on-chip system on the rate according to the rate of the high-speed transceivers integrated in the FPGA, and selecting the number of the high-speed transceivers required to be interconnected so that the transmission rate of the interconnected high-speed transceivers meets the rate requirement of the on-chip system.

And step S130, according to the logic function of the prefabricated member of the system on a chip, simulating the scene of the prefabricated member by utilizing the internal resources of the FPGA, wherein each FPGA internally instantiates 1-N prefabricated members according to the logic scale of the prefabricated member, and N is a positive integer greater than 1.

If the size of the core particles causes that only one core particle can be realized in each FPGA, the logic function of the corresponding core particle is realized by using the internal resource instantiation of the FPGA.

If the size of the core particles results in multiple core particles being implemented in each FPGA, the logic functions of the multiple core particles may be implemented in one FPGA. And under the condition that a plurality of core particles are integrated in the FPGA, multiple prefabricated members are instantiated by combining with the resource simulation in the FPGA, data transmission is carried out among the prefabricated members in a parallel port mode, and interfaces of the prefabricated members are not occupied by the instantiated prefabricated members.

And step 140, constructing a NoC (network-on-chip) network to realize on-chip, inter-chip and off-chip interconnection according to interfaces of the connection subsystem and the requirements of interconnection between FPGAs in the first chipset and the internal interconnection.

The on-chip interconnection refers to connection of a plurality of core particles in one FPGA, the on-chip interconnection refers to connection of a plurality of FPGAs, and the off-chip interconnection refers to connection of the FPGAs and interfaces.

And step S150, accessing the subsystem into the first chipset according to the application scene requirement to construct a complete prototype verification system.

Step S160, compiling and synthesizing corresponding RTL (register-transfer level) codes, laying out and wiring by using a rear-end implementation tool of the FPGA aiming at the synthesized netlist and constraint file, generating a first bit stream file, downloading the generated first bit stream file into the FPGA, and debugging by using an online debugging tool to obtain an operation result of the prototype verification system.

The embodiment of the invention sets a first chip set and a subsystem in a prototype verification system, wherein the first chip set is provided with a plurality of first field programmable gate arrays, each first field programmable gate array realizes all or part of logic functions of one or more core grains of the on-chip system by running a first bit stream file, and the subsystem realizes an expansion function. Thus, a prototype verification system of the on-chip system is built through the first field programmable gate array, and the prototype verification of the on-chip system is realized.

Fig. 2 is a schematic diagram of a prototype verification system according to a second embodiment of the invention. In the embodiment shown in fig. 2, the prototype verification system comprises a first chipset 1 and at least one subsystem. The first chipset 1 includes a plurality of first field programmable gate arrays, and the plurality of first field programmable gate arrays are used for running a first bitstream file to implement logic functions of the system on a chip. The subsystem is connected with the first chip set 1 and is used for realizing an expansion function.

The prototype verification system shown in fig. 2 differs from that of fig. 1 in the implementation of the subsystems. In fig. 1, each subsystem is implemented in the form of an external sub-card, while in the embodiment shown in fig. 2, the subsystem is implemented by an FPGA, and meanwhile, the prototype verification system shown in fig. 2 does not need to be provided with an interface, and only needs to be connected through an interconnection line. The implementation of the first chipset is similar to that of fig. 1, and the embodiments of the present invention are not described herein again.

In particular, the subsystem comprises a second chipset 2 comprising at least one second field programmable gate array for running a second bit stream file to implement the corresponding extended functionality. Fig. 2 illustrates the extended functionality of four subsystems, 21, 22, 23 and 24 respectively, implemented by four second field programmable gate arrays, respectively.

It should be understood that, in the embodiment of the present invention, the number of data processing modules that can be implemented by the second field programmable gate array is not limited, and the specific configuration may be performed according to the logic scale of the selected FPGA and the logic scale of the data processing modules. For example, for a data processing module with a smaller logical size, a second field programmable gate array may implement the logical functions of a plurality of data processing modules; for larger logic scale data processing modules, a second field programmable gate array may implement the logic functions of a data processing module.

According to the embodiment of the invention, the on-chip system and the subsystem are realized through the FPGA, various functions can be flexibly configured according to actual application scenes, and the flexibility of the prototype verification system is improved.

step S210, the logic scale of the prefabricated member of the system on a chip and the number and the speed of the high-speed transceivers are evaluated, and the proper FPGA model and the proper FPGA number are selected according to the logic scale and the number and the speed of the high-speed transceivers and are used for generating a first chip set. The number and rate of the required extended functionality logic size and high speed transceiver requirements are evaluated and the appropriate FPGA model and number of FPGAs are selected based on the number and rate of logic size and high speed transceivers for use in generating the second chipset.

Step S220, the number of the high-speed transceivers required is determined according to the resources of the high-speed transceivers integrated in the FPGA.

The method specifically includes determining the number of high-speed transceivers required according to the resources of the high-speed transceivers integrated in the FPGA, determining the rate requirement of the on-chip system according to the rate of the high-speed transceivers integrated in the FPGA, and selecting the number of high-speed transceivers required to be interconnected so that the transmission rate of the interconnected high-speed transceivers meets the rate requirement of the on-chip system and the subsystem.

Step S230, according to the logic function of the prefabricated member of the system on a chip, utilizing the internal resources of the FPGA to simulate the scene of the prefabricated member, and each FPGA internally instantiates 1-N prefabricated members according to the logic scale of the prefabricated member, wherein N is a positive integer greater than 1.

The subsystems are instantiated in the same manner to implement the extended functionality.

And step S240, constructing a NoC (network-on-chip) network to realize on-chip, inter-chip and off-chip interconnection, and constructing a complete prototype verification system.

The on-chip interconnection refers to connection of a plurality of core particles in one FPGA, the on-chip interconnection refers to connection of a plurality of FPGAs, and the off-chip interconnection refers to connection of the FPGA of the first chipset and the FPGA of the second chipset.

Step S250, compiling and synthesizing corresponding RTL (register-transfer level) codes, laying out and wiring by using a rear-end implementation tool of the FPGA aiming at the synthesized netlist and constraint file, generating a first bit stream file and a second bit stream file, downloading the generated first bit stream file and second bit stream file into the FPGA, and debugging by using an online debugging tool to obtain an operation result of the prototype verification system.

Fig. 3 is a schematic diagram of a prototype verification system according to a third embodiment of the invention. In the embodiment shown in fig. 3, the prototype verification system comprises a first chipset 1 and at least one subsystem. The first chipset 1 includes a plurality of first field programmable gate arrays, and the plurality of first field programmable gate arrays are used for running a first bitstream file to implement logic functions of the system on a chip. The subsystem is connected with the first chip set 1 and is used for realizing an expansion function.

In this embodiment, the subsystem includes at least one data processing module of DSP, CPU, GPU, NPU, etc. and its required peripheral circuits, that is, the subsystem includes at least one subsystem in the form of an external sub-card. Meanwhile, the subsystem further comprises a second chipset 2, which comprises at least one second field programmable gate array for running a second bit stream file to realize a corresponding extended function.

Fig. 3 illustrates the extended functionality of two subsystems implemented by two second field programmable gate arrays, 21 and 22, respectively. The extended functions of the two subsystems are respectively implemented by two external sub-cards, 23 and 24. That is, the subsystem in the embodiment shown in fig. 3 includes both a subsystem implemented by at least one of a data processing module, DSP, CPU, GPU, NPU, etc., and its required peripheral circuitry, and a subsystem implemented by an FPGA.

Therefore, through the implementation manner shown in fig. 3, when the subsystem cannot be implemented through the FPGA, or when the subsystem is difficult to implement by the FPGA, or when the FPGA scale of the prototype verification system is insufficient to implement all the subsystems, all or part of the subsystem that can pass through the FPGA can be selectively implemented through the FPGA, and other subsystems are implemented through the external sub-card, so that the flexibility of the system is improved.

step S310, the logic scale of the prefabricated member of the system on a chip and the number and the speed of the high-speed transceivers are evaluated, and the proper FPGA model and the proper FPGA number are selected according to the logic scale and the number and the speed of the high-speed transceivers and are used for generating a first chip set.

Step 320, determining the number of high-speed transceivers required according to the resources of the high-speed transceivers integrated in the FPGA.

Step S330, classifying the subsystems to obtain classification results, wherein the classification results are used for representing whether the subsystems can be realized through the FPGA.

Step S340, according to the logic function of the prefabricated member of the system on a chip, utilizing the internal resources of the FPGA to simulate the scene of the prefabricated member, and each FPGA internally instantiates 1-N prefabricated members according to the logic scale of the prefabricated member, wherein N is a positive integer greater than 1. The subsystem with functions capable of being realized in the FPGA is constructed by utilizing resources integrated in the FPGA, for example, the functions of simulating the DSP to process the prefabricated members can be exemplified by utilizing a DSP unit in the FPGA, and when a plurality of prefabricated members are constructed in a chip, data interaction is realized among the prefabricated members in a parallel port mode, so that the resources of a high-speed transceiver are not occupied.

And step S350, constructing a NoC (network-on-chip) network to realize on-chip, inter-chip and off-chip interconnection, and constructing a complete prototype verification system.

And step S360, compiling and synthesizing corresponding RTL (register-transfer level) codes, laying out and wiring by using a rear-end implementation tool of the FPGA aiming at the synthesized netlist and constraint file, generating a first bit stream file and a second bit stream file, downloading the generated first bit stream file and second bit stream file into the FPGA, and debugging by using an online debugging tool to obtain an operation result of the prototype verification system.

It should be understood that the implementation of the core particles of the on-chip system of the prototype verification system shown in fig. 1-3 is only a few examples provided by embodiments of the present invention, which are not limited in this regard and may be implemented in other ways.

Specifically, fig. 4 is a schematic diagram of a prototype verification system according to a fourth embodiment of the invention. In the embodiment shown in fig. 4, the prototype verification system comprises a first chipset 1 and at least one subsystem. The first chipset 1 includes a plurality of first field programmable gate arrays, and the plurality of first field programmable gate arrays are used for running a first bitstream file to implement logic functions of the system on a chip. The subsystem is connected with the first chip set 1 and is used for realizing an expansion function.

In this embodiment, the implementation manner of the subsystem is similar to that of fig. 1, and the embodiments of the present invention are not repeated here. It should be understood that the implementation manner of the first chipset in the embodiment of the present invention is equally applicable to the prototype verification system shown in fig. 2 and 3, and will not be repeated.

In the embodiment shown in fig. 4, the first chipset includes a plurality of first field programmable gate arrays for running a first bitstream file to implement the logic functions of the system on a chip. The system on a chip comprises a plurality of core grains, a first field programmable gate array is used for realizing all logic functions of one or more core grains of the system on a chip, and the residual resources of the first field programmable gate array realize part of logic functions of one or more core grains.

As shown in fig. 4, the first chipset includes four first field programmable gate arrays, 11, 12, 13, and 14, respectively. The first field programmable gate arrays 11-14 can respectively realize the complete logic functions of five core grains, and after the complete logic functions of the five core grains are realized, the first field programmable gate arrays 11-14 all have residual resources, so that the residual resources respectively realize part of the logic functions of one core grain, and the residual resources are integrated together to realize the complete logic functions of one core grain.

Therefore, each FPGA can be fully utilized, and the integration level of the system is improved. Meanwhile, the FPGA can be flexibly configured according to the logic scale of the core particles, for example, one or more core particles with smaller logic scale are realized in one FPGA, one core particle with larger logic scale is realized through the residual resources of a plurality of FPGAs, and the flexibility of the system is improved.

step S410, the logic scale of the prefabricated member of the system on a chip and the number and the speed of the high-speed transceivers are evaluated, and the proper FPGA model and the proper FPGA number are selected according to the logic scale and the number and the speed of the high-speed transceivers.

Step S420, selecting an interface in a corresponding form as an external interface according to the interface form of the subsystem to connect the system, and determining the number of the required high-speed transceivers according to the resources of the high-speed transceivers integrated in the FPGA.

Step S430, according to the logic function of the prefabricated member of the system on a chip, utilizing the internal resources of the FPGA to simulate the scene of the prefabricated member, and each FPGA internally instantiates 1-N prefabricated members according to the logic scale of the prefabricated member, wherein N is a positive integer greater than 1. The remaining resources of each FPGA implement part of the logic function of one core.

The scales of a plurality of small core particles can be placed in one FPGA, and a large-scale core particle is realized in the other 3 FPGAs.

One or more core grains are realized in each FPGA, and the residual resources of the FPGA can realize one large-scale core grain.

Step S440, according to the interface of the connection subsystem and the requirements of interconnection between FPGAs and the interior of the first chip set, a NoC (network-on-chip) network is constructed to realize on-chip, inter-chip and off-chip interconnection.

And S450, accessing the subsystem into the first chipset according to the application scene requirement to construct a complete prototype verification system.

Step S460, compiling and synthesizing corresponding RTL (register-transfer level) codes, laying out and wiring by applying a rear-end implementation tool of the FPGA aiming at the synthesized netlist and constraint file, generating a first bit stream file, downloading the generated first bit stream file into the FPGA, and debugging by applying an online debugging tool to obtain an operation result of the prototype verification system.

Fig. 5 is a schematic diagram of a prototype verification system according to a fifth embodiment of the invention. In the embodiment shown in fig. 5, the prototype verification system comprises a first chipset 1 and at least one subsystem. The first chipset 1 includes a plurality of first field programmable gate arrays, and the plurality of first field programmable gate arrays are used for running a first bitstream file to implement logic functions of the system on a chip. The subsystem is connected with the first chip set 1 and is used for realizing an expansion function.

In the embodiment shown in fig. 5, the first chipset includes a plurality of first field programmable gate arrays for running a first bitstream file to implement the logic functions of the system on a chip. The on-chip system comprises a plurality of core grains, one part of the first field programmable gate array is used for realizing all logic functions of one or more core grains of the on-chip system, and the other part of the residual resources of the first field programmable gate array are used for realizing part of logic functions of one core grain.

As shown in fig. 5, the first chipset includes four first field programmable gate arrays, 11, 12, 13, and 14, respectively. Wherein the first field programmable gate array 11 can implement the complete logic functions of six cores, and the first field programmable gate arrays 12-13 are used for implementing part of the logic functions of one core.

That is, assuming that the first chipset includes four FPGAs, the system on a chip includes seven die, where six die are small in size and can be implemented in one FPGA. One core is large in size and needs to be implemented in three FPGAs.

Further, the method for obtaining the prototype verification system of the on-chip system according to the embodiment of the present invention is similar to that of fig. 4, and the description of the embodiment of the present invention is omitted here.

Further, the embodiment of the present invention also provides a testing method of a system on a chip, which can be applied to the prototype verification system shown in any one of the embodiments of fig. 1 to 5, specifically as shown in fig. 6, and includes the following steps:

step S611, RTL engineering.

RTL engineering of a prototype verification system of a system-on-chip is designed to realize the logic function of the system-on-chip.

Step S612, design synthesis.

Step S613, design segmentation, design transplanting and FPGA production constraint.

For design division, the logic scale of the on-chip system is generally far greater than the capacity of a single FPGA, and in this step of design division (Partitioning), the core of the original on-chip system needs to be divided in a modularized manner so as to be put into different FPGAs to realize verification.

For design migration, the design of the system on a chip often needs to be modified to accommodate the underlying structure of the FPGA and the selected prototype verification platform before verification is performed. Typical modifications include: modules that are inconvenient to implement or do not need to be placed on the prototype verification platform for verification are deleted, and the underlying structures on some FPGAs are used to replace the corresponding structures specific on the on-chip system through code modification.

Step S614, design synthesis.

For steps S612 and S614, the design synthesis may be performed before or after the design is divided. A synthesis tool is applied to effect the conversion from RTL to netlist level. Available tools include design kits provided by FPGA vendors or third party integration tools, and the like.

Step S615, place and route.

The layout and wiring are processes of generating bit stream files by applying a back-end implementation tool provided by an FPGA manufacturer to perform layout and wiring aiming at the synthesized netlist and constraint files.

Step S616, on-line debugging

And downloading the generated bit stream file into the FPGA, and debugging by applying a debugging tool.

Further, the test method of the system on a chip in the embodiment of the invention further includes simulation verification, specifically as shown in a dashed line box in fig. 6, including the following steps:

Step S621, behavior level simulation.

Step S622, function simulation.

The simulation means that the working condition of the actual physical environment is simulated by using a simulator, and the realized design is completely tested.

For step S621 and step S622, the behavioral level simulation and the functional simulation are test simulation on the logic function to understand whether the implemented function meets the requirement of the original design, and the simulation process does not add timing information, and does not involve the hardware characteristics of the specific device, such as delay characteristics, etc.

Step S623, time sequence simulation.

Step S624, static time sequence simulation.

For steps S623-S624, relevant device delay, wire delay and other time sequence parameters are extracted after layout and wiring, and simulation is performed on the basis, so that the simulation can reflect the running state of a real device.

Step S625, debugging the system.

On the premise of time sequence Sign-off, the system debugging downloads a bit stream file formed after layout and wiring to a specific FPGA chip, which is also called chip configuration. FPGAs come in a variety of configurations including configuration directly by a computer via a special download cable connection JTAG (Joint Test Action Group, joint test workgroup) interface, automatic configuration when powered on by a peripheral configuration chip, etc. And downloading the bit stream file into the FPGA device, and then performing physical test on the actual device, wherein the design correctness is proved after a correct verification result is obtained.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A prototype verification system for a system-on-chip, the prototype verification system comprising:

2. The prototype verification system according to claim 1, wherein the extended functions comprise at least one corresponding function of a digital signal processing module, a central processing unit, a graphics processor, and a network processor.

3. The prototype verification system according to claim 2, wherein the subsystem comprises:

4. The prototype verification system according to claim 1, wherein said subsystem comprises at least one of a digital signal processing module, a central processing unit, a graphics processor, and a network processor.

5. The prototype verification system according to claim 4, further comprising:

6. The prototype verification system according to claim 5, further comprising:

7. The prototype verification system according to claim 1, wherein said first field programmable gate array comprises at least one functional sub-module for implementing all or part of the logic functions of one core of said system-on-chip.

8. The prototype verification system according to claim 1, wherein the model number and number of the first field programmable gate array are determined based on the logic size of the die of the system-on-chip and the interconnect requirements of the die.

9. A prototype verification system according to claim 3, wherein the first bit stream file and the second bit stream file comprise configuration information for programmable logic units and wiring resources.

10. The prototype verification system according to claim 5, wherein said interface comprises at least one of a switch interface, a high-speed interconnect technology interface, a high-speed serial computer expansion bus standard interface, and an ethernet interface.