CN117250485A - Multi-power-supply component power-on time sequence verification circuit and verification method - Google Patents
Multi-power-supply component power-on time sequence verification circuit and verification method Download PDFInfo
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- CN117250485A CN117250485A CN202311061795.2A CN202311061795A CN117250485A CN 117250485 A CN117250485 A CN 117250485A CN 202311061795 A CN202311061795 A CN 202311061795A CN 117250485 A CN117250485 A CN 117250485A
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- 238000012795 verification Methods 0.000 title claims abstract description 146
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000012360 testing method Methods 0.000 claims description 45
- 230000002457 bidirectional effect Effects 0.000 claims 1
- 239000006185 dispersion Substances 0.000 claims 1
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100532097 Vitis rotundifolia RUN1 gene Proteins 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a multi-power-supply component power-on time sequence verification circuit and a verification method, wherein the method comprises the steps of independently debugging and/or laboratory verification of the power-on time sequence of a device to be verified; the first programmable logic circuit outputs a preset first power-on time sequence control logic signal to independently debug the power-on time sequence of the device to be verified; and the second programmable logic circuit outputs a second power-on time sequence control logic signal to perform laboratory verification on the power-on time sequence of the device to be verified. The verification circuit comprises a verification card UVC, a verification card VCM and a switch switching circuit, the verification card UVC is connected with a device to be verified through a power supply circuit, a first programmable logic circuit and the power supply circuit are arranged on the verification card UVC, and a second programmable logic circuit is arranged on the verification card VCM. The verification circuit and the verification method can realize the switching of the power-on time sequence verification mode, and overcome the limitation that the power-on time sequence logic is required to be continuously modified and the power-on time sequence verification is realized by repeated programming in the traditional method.
Description
Technical Field
The invention belongs to the technical field of verification design of processors, and relates to a multi-power-supply component power-on time sequence verification circuit and a verification method.
Background
With the rapid development of high-speed digital signals, more demands are put on a power-on time sequence control mode of a multi-power supply processor integrating multiple cores and a high-speed interface. The current power-on time sequence of the multi-power supply processor adopts a programmable logic circuit, and the power-on time sequence verification is realized by continuously modifying power-on time sequence logic in the programmable logic circuit and repeatedly programming.
Therefore, there is a need to provide a more flexible power-up timing control switching and verification circuit design scheme.
Disclosure of Invention
In order to solve the limitations of complex verification process, low efficiency, low universality and the like in the prior art of verifying the power-on time sequence of a multi-power-supply component by adopting a programmable logic circuit, the invention discloses a power-on time sequence verification circuit and a power-on time sequence verification method of the multi-power-supply component.
The technical scheme for realizing the aim of the invention is as follows:
the embodiment of the invention provides a multi-power-supply component power-on time sequence verification method, which comprises the steps of independently debugging and/or laboratory verification of the power-on time sequence of a device to be verified;
independently debugging the power-on time sequence of the device to be verified, comprising the following steps: controlling a first programmable logic circuit to output a preset first power-on time sequence control logic signal to a power supply circuit, and debugging the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing laboratory verification on the power-on time sequence of the device to be verified, including: and controlling a second programmable logic circuit to output a second power-on time sequence control logic signal to the power supply circuit, and performing laboratory verification on the power-on time sequence of the device to be verified by adopting the power supply circuit.
Further, the independent debugging mode and the laboratory verification mode are switched by adopting a working state discrete quantity signal.
Further, the laboratory verification comprises a verification test or a verification test, and the second power-on time sequence control logic signal comprises a preset second power-on time sequence control logic signal and a second power-on time sequence control logic signal edited in real time;
performing verification test on the power-on time sequence of the device to be verified, including: controlling the second programmable logic circuit to output the preset second power-on time sequence control logic signal to the power supply circuit, and performing verification test on the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing a verification test on a power-on time sequence of the device to be verified, including: and controlling the second programmable logic circuit to output the second power-on time sequence control logic signal edited in real time to the power supply circuit, and performing verification test by adopting the power-on time sequence of the device to be verified of the power supply circuit.
Further, the edited second power-on timing control logic signal is generated by the test equipment and output via the DSP master control circuit.
Furthermore, the laboratory state discrete quantity signal is adopted for switching between the verification test mode and the verification test mode.
The invention further provides a multi-power-supply component power-on time sequence verification circuit, which comprises a verification card UVC and a verification card VCM, wherein a switch switching circuit is arranged on the verification card UVC, a first programmable logic circuit is arranged on the verification card UVC, a second programmable logic circuit is arranged on the verification card VCM, and the first programmable logic circuit and the second programmable logic circuit are both connected with the switch switching circuit;
the UVC of the verification card is provided with a power circuit, the input end of the power circuit is connected with the switch switching circuit, and the output end of the power circuit is detachably connected with a device to be verified;
the output end of the power supply circuit is also connected with the first programmable logic circuit and the second programmable logic circuit, and the power supply circuit is switched with the first programmable logic circuit or the second programmable logic circuit through working state discrete quantity signals.
Further, a DSP master control circuit is further disposed on the verification card VCM, and the DSP master control circuit is bi-directionally connected with the second programmable logic circuit and the testing device. The second programmable logic circuit outputs a preset second power-on time sequence control logic signal or a second power-on time sequence control logic signal edited in real time to the power supply circuit through the working state discrete quantity signal selection, wherein the preset second power-on time sequence control logic signal is preset logic in the second programmable logic circuit, and the second power-on time sequence control logic signal edited in real time is generated by the test equipment and is output through the DSP main control circuit.
Further, the device to be verified is detachably connected to the output end of the power supply circuit through an interface.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
1. according to the multi-power-supply-component power-on time sequence verification method, the working state discrete quantity signal EXIST and the laboratory state discrete quantity signal GSE are integrated, and the working state of the verification card UVC is judged through logic, so that a hardware system can flexibly realize power-on time sequence control switching through multiple modes, and the limitation that the traditional verification method needs to realize power-on time sequence verification by continuously modifying power-on time sequence logic and repeatedly programming in a programmable logic device is overcome.
2. The verification circuit for the power-on time sequence of the multi-power-supply component not only can realize verification of the power-on time sequence of the multi-power-supply component, but also can enable the verification card UVC to be separated from the control of the verification card VCM, so that the verification card UVC can work independently, and the verification circuit can be combined with the verification card VCM to increase the application scene of the verification card UVC.
3. The verification circuit provided by the invention has the advantages that the design is simple, any power-on time sequence combination can be verified, the debugging mode, the verification test mode and the verification test mode can be switched, the verification result is more sufficient, and the universality and the portability are very strong.
4. According to the verification circuit and the verification method, the DSP main control circuit 6 and the test equipment 7 are introduced to control the realization of the real-time setting of the power-on time sequence, so that the real-time setting of any power-on time sequence logic can be realized, and the limitation of continuously modifying the power-on time sequence logic and repeatedly programming in the programmable logic device is overcome.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a power-on timing verification circuit for a multi-powered device according to the present invention;
1, a switch switching circuit; 2. a first programmable logic circuit; 3. a second programmable logic circuit; 4. a power supply circuit; 5. a device to be verified; 6. a DSP master control circuit; 7. and testing equipment.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The embodiment of the invention provides a multi-power-supply component power-on time sequence verification method, which comprises the steps of independently debugging and/or laboratory verification of the power-on time sequence of a device to be verified;
independently debugging the power-on time sequence of the device to be verified, comprising the following steps: controlling a first programmable logic circuit to output a preset first power-on time sequence control logic signal to a power supply circuit, and debugging the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing laboratory verification on the power-on time sequence of the device to be verified, including: and controlling a second programmable logic circuit to output a second power-on time sequence control logic signal to the power supply circuit, and performing laboratory verification on the power-on time sequence of the device to be verified by adopting the power supply circuit.
Further, the independent debugging mode and the laboratory verification mode are switched by adopting a working state discrete quantity signal.
Further, the laboratory verification comprises a verification test or a verification test, and the second power-on time sequence control logic signal comprises a preset second power-on time sequence control logic signal and a second power-on time sequence control logic signal edited in real time;
performing verification test on the power-on time sequence of the device to be verified, including: controlling the second programmable logic circuit to output the preset second power-on time sequence control logic signal to the power supply circuit, and performing verification test on the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing a verification test on a power-on time sequence of the device to be verified, including: and controlling the second programmable logic circuit to output the second power-on time sequence control logic signal edited in real time to the power supply circuit, and performing verification test by adopting the power-on time sequence of the device to be verified of the power supply circuit.
Further, the edited second power-on timing control logic signal is generated by the test equipment and output via the DSP master control circuit.
Furthermore, the laboratory state discrete quantity signal is adopted for switching between the verification test mode and the verification test mode.
Another embodiment of the present invention provides a multi-power device power-on timing verification circuit, which is designed to verify a power-on timing of a device to be verified by using the method in the above embodiment.
Referring to fig. 1, the verification circuit for power-on timing sequence of the multi-power-supply component includes a verification card UVC (UnderValidation Card) and a verification card VCM (Validation Control Module), and a switch switching circuit 1 is disposed on the verification card UVC, where it should be noted that the switch switching circuit 1 may also be disposed on the verification card VCM. The verification card UVC is provided with a first programmable logic circuit 2, the verification card VCM is provided with a second programmable logic circuit 3, and the first programmable logic circuit 2 and the second programmable logic circuit 3 are both connected with the switch switching circuit 1. The verification card UVC is provided with a power supply circuit 4, the input end of the power supply circuit 4 is connected with the switch switching circuit 1, the output end of the power supply circuit 4 is detachably connected with a device 5 to be verified, and preferably, the device 5 to be verified is detachably connected with the output end of the power supply circuit 4 through an interface.
In the embodiment of the invention, the switch switching circuit 1 is used for realizing that a power supply circuit is communicated with the first programmable logic circuit 2 or the second programmable logic circuit 3. The output end of the power supply circuit 4 is also connected with the first programmable logic circuit 2 and the second programmable logic circuit 3, and the power supply circuit 4 is powered on with the first programmable logic circuit 2 or the second programmable logic circuit 3 through switching of working state discrete quantity signals.
Specifically, referring to fig. 1, the switching of the individual debug mode or the laboratory verification mode of the power-on timing sequence of the device to be verified 5 is realized by the high and low of the operating state discrete quantity signal EXIST level. For example, when the verification card is inserted into the verification card VCM for communication, the switch switching circuit 1 receives the working state discrete quantity signal EXIST to be low level "0", and enters the laboratory verification mode, and the second programmable logic circuit 3 on the verification card VCM outputs a RUN2 signal to the switch switching circuit 1 to control the switch switching circuit 1 to output a signal (RUN) to the power circuit 4.
When the single debug mode is adopted, the first programmable logic circuit 2 is communicated with the switch switching circuit 1, and a power-on time sequence control logic signal RUN1 (namely a first power-on time sequence control logic signal) generated by the first programmable logic circuit 2 is used as an output signal RUN of the switch switching circuit 1. When the system is in the laboratory verification mode, the second programmable logic circuit 3 is communicated with the switch switching circuit 1, and a power-on time sequence control logic signal RUN2 (namely a second power-on time sequence control logic signal comprising a preset second power-on time sequence control logic signal and a second power-on time sequence control logic signal edited in real time) of the second programmable logic circuit 3 is used as an output signal RUN of the switch switching circuit 1, and the output signal RUN controls the output of the power-on time sequence of the power circuit 4 to realize the power-on time sequence control of the multi-power supply processor.
Further, referring to fig. 1, the verification card VCM is further provided with a DSP master control circuit 6, and the DSP master control circuit 6 is bi-directionally connected with the second programmable logic circuit 3 and the test device 7. The second programmable logic circuit 3 outputs a preset second power-on time sequence control logic signal or a second power-on time sequence control logic signal edited in real time to the power circuit 4 through the working state discrete quantity signal selection, wherein the preset second power-on time sequence control logic signal is preset logic in the second programmable logic circuit 3, and the second power-on time sequence control logic signal edited in real time is generated by the DSP main control circuit 6.
Specifically, referring to fig. 1, the level of the discrete magnitude signal GSE is high or low by an operation state, for example: when the working state discrete quantity signal GSE signal is low level 0, the working state discrete quantity signal GSE signal is in a verification test state, and the power-on time sequence logic of the second programmable logic circuit 3 is required to wait for the DSP main control circuit 6 and the test equipment 7 to set the power-on time sequence and then generate the power-on time sequence; when the operating state discrete magnitude signal GSE signal is a high level "1", it indicates that the operating state discrete magnitude signal GSE is in a verification test state, and the power-on sequential logic in the second programmable logic circuit 3 uses the preset power-on sequential logic, and does not wait for the setting of the DSP master control circuit 6 and the test device 7. The switching of the power-on time sequence logic in the second programmable logic circuit 3 is controlled, so that the switching of a verification test mode or a verification test mode of the multi-power supply processor under the control of the verification card VCM is realized, a preset second power-on time sequence control logic signal RUN2 or a second power-on time sequence control logic signal RUN2 edited in real time is output to the switch switching circuit 1 as an output signal RUN of the switch switching circuit 1, and the output signal RUN controls the output of the power-on time sequence of the power circuit 4, so that the power-on time sequence control of the multi-power supply processor is realized.
The embodiment of the invention realizes the following technical effects:
1. according to the multi-power-supply-component power-on time sequence verification method, the working state discrete quantity signal EXIST and the working state discrete quantity signal GSE are integrated, and the working state of the verification card UVC is judged through logic, so that a hardware system can flexibly realize power-on time sequence control switching through multiple modes, and the limitation that the traditional verification method needs to realize power-on time sequence verification by continuously modifying power-on time sequence logic and repeatedly programming in a programmable logic device is overcome.
2. The verification circuit for the power-on time sequence of the multi-power-supply component not only can realize verification of the power-on time sequence of the multi-power-supply component, but also can enable the verification card UVC to be separated from the control of the verification card VCM, so that the verification card UVC can work independently, and the verification circuit can be combined with the verification card VCM to increase the application scene of the verification card UVC.
3. The verification circuit provided by the invention has the advantages that the design is simple, any power-on time sequence combination can be verified, the debugging mode, the verification test mode and the verification test mode can be switched, the verification result is more sufficient, and the universality and the portability are very strong.
4. According to the verification circuit and the verification method, the DSP main control circuit 6 and the test equipment 7 are introduced to control the realization of the real-time setting of the power-on time sequence, so that the real-time setting of any power-on time sequence logic can be realized, and the limitation of continuously modifying the power-on time sequence logic and repeatedly programming in the programmable logic device is overcome.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations can be made to the embodiments of the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The verification method of the power-on time sequence of the multi-power-supply component is characterized by comprising the steps of independently debugging and/or verifying a laboratory on the power-on time sequence of the component to be verified;
independently debugging the power-on time sequence of the device to be verified, comprising the following steps: controlling a first programmable logic circuit to output a preset first power-on time sequence control logic signal to a power supply circuit, and debugging the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing laboratory verification on the power-on time sequence of the device to be verified, including: and controlling a second programmable logic circuit to output a second power-on time sequence control logic signal to the power supply circuit, and performing laboratory verification on the power-on time sequence of the device to be verified by adopting the power supply circuit.
2. The method for verifying power-on time sequence of a multi-power-supply component according to claim 1, wherein the single debugging mode and the laboratory verification mode are switched by using an operating state discrete quantity signal.
3. The multi-powered component power-up timing verification method of claim 1, wherein the laboratory verification comprises a verification test or a verification test, and the second power-up timing control logic signal comprises a preset second power-up timing control logic signal and a second power-up timing control logic signal edited in real time;
performing verification test on the power-on time sequence of the device to be verified, including: controlling the second programmable logic circuit to output the preset second power-on time sequence control logic signal to the power supply circuit, and performing verification test on the power-on time sequence of the device to be verified by adopting the power supply circuit;
performing a verification test on a power-on time sequence of the device to be verified, including: and controlling the second programmable logic circuit to output the second power-on time sequence control logic signal edited in real time to the power supply circuit, and performing verification test by adopting the power-on time sequence of the device to be verified of the power supply circuit.
4. A multi-supply component power-up timing verification method as set forth in claim 3 wherein said edited second power-up timing control logic signal is generated by a test device and output via a DSP master circuit.
5. A multi-supply component power-on timing verification method as claimed in claim 3, wherein the verification test mode and the verification test mode are switched by using a laboratory state dispersion signal.
6. The multi-power-supply component power-on time sequence verification circuit is characterized by comprising a verification card UVC and a verification card VCM, wherein a switch switching circuit is arranged on the verification card UVC, a first programmable logic circuit is arranged on the verification card UVC, a second programmable logic circuit is arranged on the verification card VCM, and the first programmable logic circuit and the second programmable logic circuit are connected with the switch switching circuit;
the UVC of the verification card is provided with a power circuit, the input end of the power circuit is connected with the switch switching circuit, and the output end of the power circuit is detachably connected with a device to be verified;
the output end of the power supply circuit is also connected with the first programmable logic circuit and the second programmable logic circuit, and the power supply circuit is switched with the first programmable logic circuit or the second programmable logic circuit through working state discrete quantity signals.
7. The multi-power-supply-component power-on time sequence verification circuit according to claim 6, wherein a DSP master control circuit is further arranged on the verification card VCM, and the DSP master control circuit is in bidirectional connection with the second programmable logic circuit and the testing equipment;
the second programmable logic circuit outputs a preset second power-on time sequence control logic signal or a second power-on time sequence control logic signal edited in real time to the power supply circuit through the working state discrete quantity signal selection, wherein the preset second power-on time sequence control logic signal is preset logic in the second programmable logic circuit, and the second power-on time sequence control logic signal edited in real time is generated by the test equipment and is output through the DSP main control circuit.
8. The multi-power-supply-component power-on time sequence verification circuit according to claim 6, wherein the device to be verified is detachably connected to the output end of the power supply circuit through an interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311061795.2A CN117250485A (en) | 2023-08-22 | 2023-08-22 | Multi-power-supply component power-on time sequence verification circuit and verification method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311061795.2A CN117250485A (en) | 2023-08-22 | 2023-08-22 | Multi-power-supply component power-on time sequence verification circuit and verification method |
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| Publication Number | Publication Date |
|---|---|
| CN117250485A true CN117250485A (en) | 2023-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311061795.2A Pending CN117250485A (en) | 2023-08-22 | 2023-08-22 | Multi-power-supply component power-on time sequence verification circuit and verification method |
Country Status (1)
| Country | Link |
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| CN (1) | CN117250485A (en) |
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2023
- 2023-08-22 CN CN202311061795.2A patent/CN117250485A/en active Pending
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