CN117242583A

CN117242583A - Metal oxide semiconductor capacitor and circuit board including the same embedded therein

Info

Publication number: CN117242583A
Application number: CN202280033113.4A
Authority: CN
Inventors: 科里·内尔森
Original assignee: Kyocera Avx Components Co ltd
Current assignee: Kyocera Avx Components Co ltd
Priority date: 2021-05-03
Filing date: 2022-04-18
Publication date: 2023-12-15

Abstract

A Metal Oxide Semiconductor (MOS) capacitor may include: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed on at least a portion of the oxide layer; a first terminal connected to a surface of the substrate; and a second terminal connected to the conductive layer. The oxide layer may be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first and second terminals may be exposed along a surface of the substrate for surface mounting the capacitor. The MOS capacitor can exhibit excellent high-frequency performance. For example, the insertion loss of the MOS capacitor may be greater than about-0.75 dB for frequencies ranging from about 5GHz to about 40 GHz.

Description

Metal oxide semiconductor capacitor and circuit board including the same embedded therein

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional patent application Ser. No. 2021, 5/3/114, and U.S. provisional patent application Ser. No. 2021, 7/21/63/224,030, the disclosures of both of which are incorporated herein by reference in their entireties.

Background

Metal-oxide-semiconductor (MOS) capacitors have various advantages such as temperature stability, typically high breakdown voltage, and low leakage current. However, MOS capacitors generally have poor high frequency performance. For example, MOS capacitors typically employ terminations that require wire bond connections.

Disclosure of Invention

According to one embodiment of the present disclosure, a capacitor may include: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed on at least a portion of the oxide layer; a first terminal connected to a surface of the substrate; and a second terminal connected to the conductive layer. The oxide layer may be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first and second terminals may be exposed along a surface of the substrate for surface mounting the capacitor.

According to another embodiment of the present disclosure, a capacitor may include: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed on at least a portion of the oxide layer; a first terminal connected to a surface of the substrate; and a second terminal connected to the conductive layer. The oxide layer may be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. The capacitor may exhibit an insertion loss at the second terminal and for an input signal applied to the first terminal. The insertion loss is greater than about-0.75 decibels (dB) for frequencies ranging from about 5GHz to about 40 GHz.

According to another embodiment of the present disclosure, a method of forming a capacitor may include: forming an oxide layer on a surface of a substrate, the substrate comprising a semiconductor material; depositing a conductive layer over at least a portion of the oxide layer; depositing a first terminal on a surface of the substrate such that the first terminal is exposed along the surface of the substrate for surface mounting a capacitor; and depositing a second terminal on the conductive layer such that the second terminal is exposed along a surface of the substrate for surface mounting the capacitor.

According to another embodiment of the present disclosure, a circuit board may include: a circuit board substrate having a mounting surface; and a capacitor at least partially embedded within the circuit board substrate. The capacitor may include: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed on at least a portion of the oxide layer; a first terminal connected to a surface of the substrate; and a second terminal connected to the conductive layer. The oxide layer may be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. The at least one via may be connected with one of the first terminal or the second terminal. The one or more vias may extend toward the mounting surface of the circuit board.

Drawings

A full and enabling disclosure of the present application, including the best mode thereof, directed to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying figures, in which:

fig. 1A is a perspective view of a capacitor according to aspects of the present disclosure.

FIG. 1B shows an oxide layer within a first portion of a surface of a substrate and a first terminal within a second portion of the surface of the substrate;

fig. 1C is a top view of the capacitor of fig. 1A.

Fig. 2 is a perspective view of the following capacitor assembly: the capacitor assembly includes the capacitor of fig. 1A-1C and a mounting surface, such as a printed circuit board;

FIG. 3 illustrates a circuit board including a capacitor embedded therein, in accordance with aspects of the present disclosure;

FIG. 4 is a flow chart of a method for forming a capacitor according to aspects of the present disclosure; and

fig. 5 shows a first insertion loss curve of the capacitor of fig. 1A to 1C compared to a second insertion loss curve of a prior art MOS.

Repeated use of reference characters in the specification and drawings is intended to represent the same or analogous features or elements of the application.

Detailed Description

Those of ordinary skill in the art will understand that the present discussion is a description of exemplary embodiments only, and is not intended as limiting the broader aspects of the present application, which broader aspects are embodied in the exemplary constructions.

In general, the present application relates to a Metal Oxide Semiconductor (MOS) capacitor configured for surface mounting. The MOS capacitor may be free of electrical connections that lead to high frequency disturbances and adversely affect high frequency performance. Examples of such electrical connections include wire bond connections.

As an example, the MOS capacitor can generally have excellent high-frequency performance. For example, for frequencies ranging from about 5 gigahertz (GHz) to about 40GHz, the MOS capacitor may exhibit an insertion loss of greater than about-0.75 dB, in some embodiments greater than about-0.6 dB, in some embodiments greater than about-0.50 dB, and in some embodiments, greater than about-0.40 dB.

As a further example, the MOS capacitor may exhibit an insertion loss of greater than-1.15 dB, in some embodiments greater than about-1.0 dB, in some embodiments greater than about-0.75 dB, and in some embodiments greater than about-0.5 dB for frequencies ranging from about 5GHz to about 50 GHz.

As a further example, the MOS capacitor may exhibit an insertion loss of greater than-2.0 dB, in some embodiments greater than-1.5 dB, in some embodiments greater than-1.0 dB, and in some embodiments greater than-0.75 dB for frequencies ranging from about 5GHz to about 60 GHz.

The MOS capacitor may include a substrate comprising a semiconductor material such as silicon, gallium arsenide, germanium, silicon carbide, strontium titanate, and/or mixtures thereof. The substrate may be doped with one or more suitable dopants, such as boron, arsenic, phosphorus, gallium, aluminum, indium and antimony.

The capacitor may include an oxide layer formed on a surface of the substrate. The oxide layer may be or include silicon oxide and/or oxides of other example semiconductor materials described herein. The oxide layer may be grown in situ on the substrate. Photolithography (e.g., photolithography) techniques may be used to define the shape of the oxide layer. For example, portions of the oxide layer may be removed by etching, thereby forming the oxide layer in a desired shape.

The surface of the substrate may be generally smooth. For example, the surface of the substrate may be free of voids or trenches, or the like. The oxide layer may have a substantially uniform thickness over the surface of the oxide layer. For example, the thickness of the oxide layer may vary over the oxide layer by less than 20%, in some embodiments less than 10%, and in some embodiments, less than 5%.

The capacitor may include a conductive layer formed on at least a portion of the oxide layer. The conductive layer may be contained within an outer edge of the oxide layer. The conductive layer may not be in direct contact with the substrate and/or in direct electrical connection. The conductive layer may be or include a metal such as aluminum, copper, gold, silver, nickel, or mixtures thereof.

One or more protective layers may be formed on the surface of the substrate. In surface mounting capacitors, terminals may be exposed through these protective layers for electrical connection. Example materials for the protective layer include benzocyclobutene (BCB), polyimide, silicon oxynitride, aluminum oxide (Al 2O 3), silicon dioxide (SiO 2), silicon nitride (Si 3N 4), epoxy, glass, or another suitable material.

Various thin film techniques may be used to form the thin film layers, such as conductive layers or terminals, etc. Examples of such techniques that may be employed include chemical deposition (e.g., chemical vapor deposition), physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin film elements. Additional examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable thinning technique for forming thin film elements.

Each film layer may have a range of thicknesses. For example, the film layer may have the following thickness: the thickness may range from about 0.0375 microns (or microns) to about 40 microns, in some embodiments from about 0.1 microns to about 30 microns, in some embodiments from about 0.2 microns to about 20 microns, and in some embodiments, from about 0.4 microns to about 10 microns.

The capacitor may include a first terminal connected to a surface of the substrate. The second terminal may be connected to the conductive layer. As used herein, "connected with … …" may refer to components that are directly physically connected. "connected to … …" may also refer to the term: the items are physically connected by one or an intermediate conductive layer such that the items are in direct electrical connection (e.g., no resistive or dielectric layer between them). The first terminal may be formed on a surface of the substrate. The second terminal may be formed on the conductive layer.

Each of the first and second terminals may be exposed along a surface of the substrate for surface mounting the capacitor. For example, the capacitor may be configured as a grid array mount, such as a land grid array or a ball grid array, or the like.

The terminals may be connected and arranged such that the oxide layer covers less than the entire surface of the substrate. For example, the first terminal may be spaced apart from the second terminal in the Y direction. The edges of the oxide layer may be aligned with the X-direction, which is perpendicular to the Y-direction. The edges of the oxide layer may be spaced apart from the ends of the substrate in the Y-direction.

The first terminal may be connected to the surface of the substrate at a location along the surface of the substrate spaced apart from the oxide layer. For example, the first terminal may be located between an edge of the oxide layer 104 and an end of the substrate. The edge of the oxide layer may be spaced from the first terminal by a distance of greater than about 2 microns, in some embodiments greater than about 5 microns, in some embodiments greater than about 10 microns, and in some embodiments greater than about 15 microns.

The oxide layer may cover a first portion of the surface of the substrate that is different from a second portion of the surface of the substrate that is free of the oxide layer. The first terminal may be connected to the surface of the substrate within the second portion of the surface of the substrate. The first terminal may include a conductive material that directly contacts a surface of the substrate.

The capacitor may be configured as a grid array mount, such as a ball grid array mount or a land grid array mount. The terminals may be exposed along the surface and contained within the outer edges of the surface of the monolithic substrate. As another example, the substrate may have a pair of end surfaces perpendicular to the surface of the monolithic substrate. The pair of end faces may be devoid of terminations, the terminations including terminals. As yet another example, the first terminal, the second terminal layer, or both may be spaced a respective distance from the pair of opposing end edges of the surface of the monolithic substrate. The distance may be 10 microns or greater, in some embodiments 15 microns or greater, in some embodiments 20 microns or greater, in some embodiments 40 microns or greater, and in some embodiments 50 microns or greater.

Fig. 1A illustrates a perspective view of a capacitor 100 according to aspects of the present disclosure. Capacitor 100 may include a substrate 102 comprising a semiconductor material, such as silicon. The capacitor 100 may include an oxide layer 104 formed on a surface 106 of a substrate 102. Capacitor 100 may include a conductive layer 108 formed over at least a portion of oxide layer 104. Conductive layer 108 may be contained within an outer edge 109 of oxide layer 104. The conductive layer 108 may not be in direct contact with and/or in direct electrical connection with the substrate 102.

The first terminal 110 may be coupled to the surface 106 of the substrate 102. The second terminal 114 may be connected to the conductive layer 108. Each of the first terminal 110 and the second terminal 114 may be exposed along the surface 106 of the substrate 102 for surface mounting the capacitor 102. The first terminal 110 may be coplanar with the oxide layer 104. For example, each of the first terminal 110 and the oxide layer 104 may be formed separately on the surface 106 of the substrate 102.

The first terminal 110 may be spaced apart from the second terminal 114 in the Y-direction 116. The edges 118 of the oxide layer 104 may be aligned with an X-direction 120 that is perpendicular to the Y-direction 116. Edge 118 of oxide layer 104 may be spaced apart from end 121 of substrate 102 in Y-direction 116.

The first terminal 100 may be connected to the surface 106 of the substrate 102 at a location along the surface 106 of the substrate 102 that is spaced apart from the oxide layer 104. For example, the first terminal 100 may be located between the edge 118 of the oxide layer 104 and the end 121 of the substrate 102. The edge 118 of the oxide layer 104 may be spaced apart from the first terminal 110 by a distance 122. In some embodiments, distance 122 may be greater than about 2 microns.

Referring to fig. 1B, an oxide layer 104 may be formed within a first portion 124 of a surface 106 of a substrate 102. The first portion 124 of the surface 106 of the substrate 102 may be different from the second portion 126 of the surface 106 of the substrate 102. The second portion 126 of the surface 106 may be free of the oxide layer 104. The first terminal 110 may be connected to the surface 106 of the substrate 102 within the second portion 126 of the surface 106 of the substrate 102. In some embodiments, the first terminal 110 may directly contact the surface 106 of the substrate 102. However, in other embodiments, the first terminal 110 may be electrically connected to the surface 106 of the substrate through one or more suitable conductive layers between the first terminal 110 and the surface 106.

The first terminal 110 may comprise a conductive material such as gold, copper, another suitable metal, or other conductive material. The substrate 102 may comprise a semiconductor material, such as silicon. Oxide layer 104 may comprise silicon oxide.

The capacitor 100 may be configured as a grid array mount, such as a ball grid array mount or a land grid array mount. Terminals 110, 112 may be exposed along surface 106 and contained within an outer edge 128 of surface 106 of monolithic substrate 102 in an X-Y plane located in each of X-direction 120 and Y-direction 116.

As another example, the substrate 102 may have a pair of end faces 130, 132 that are perpendicular to the surface 106 of the monolithic substrate 102. The pair of end faces 130, 132 may be devoid of terminations, including terminals 110, 112. As yet another example, the first terminal 110, the second terminal layer 112, or both may be spaced apart from the pair of opposing end edges 130, 132 of the surface 106 of the monolithic substrate 102 by respective distances 133, 135. The distances 133, 135 may be 10 microns or greater.

Fig. 2 is a perspective view of a capacitor assembly 200 that includes the capacitor 100 of fig. 1A-1C and a mounting surface 202, such as a printed circuit board. The first terminal 110 of the capacitor 100 may be connected with a first conductive trace 204 of the mounting surface 202. The second terminal 114 of the capacitor 100 may be connected with the second conductive trace 206 of the mounting surface 202. As shown in fig. 2, the capacitor 100 may be configured as a flip chip such that the surface 106 (fig. 1A-1C) is opposite the mounting surface 202.

Fig. 3 illustrates a circuit board 300 including a capacitor 100 embedded therein, in accordance with aspects of the present disclosure. The circuit board 300 may include a circuit board substrate 307 that includes a mounting surface 304. The capacitor 100 may be at least partially embedded within a circuit board substrate 307 of the circuit board 300. The capacitor 100 may generally be configured similar to the transmission line capacitor 100 of fig. 1A-2.

The first via 312 may extend from the first terminal 110 toward the mounting surface 304 and connect to the first conductive layer 314. A first conductive layer 314 may be formed on the mounting surface 304 and electrically connect the first terminal 110 with the first conductive layer 314 on the mounting surface 304. The second via 316 may extend from the second terminal 114 toward the mounting surface 304 and connect to the second conductive layer 318. A second conductive layer 318 may be formed on the mounting surface 304 to electrically connect the second terminal 114 with the second conductive layer 318. Alternatively, the vias 112, 116 may extend toward the mounting surface 304 and connect with one or more intermediate layers (e.g., embedded within the circuit board substrate 307), which in turn may be electrically connected with the first conductive layer 314 and/or the second conductive layer 308. The first via 112 may form at least a portion of an electrical connection between the first terminal 110 and the first conductive layer 314. Similarly, the second via 316 may form at least a portion of an electrical connection between the second terminal 114 and the second conductive layer 318. Thus, conductive layers 314, 318 may be used to facilitate electrical connection with capacitor 100. However, it should be understood that in other embodiments, one or both of the terminals 110, 114 may be exposed along the mounting surface 304. In such embodiments, the circuit board 300 may be devoid of one or both of the vias 312, 316.

Referring to fig. 4, aspects of the present disclosure relate to a method 300 for forming a capacitor in accordance with aspects of the present disclosure. In general, the method 400 will be described herein with reference to the capacitor 100 of fig. 1A-1C. However, it should be understood that the disclosed method 400 may be implemented with any suitable capacitor. Moreover, although FIG. 4 depicts steps performed in a particular order for purposes of illustration and discussion, the methods discussed herein are not limited to any particular order or arrangement. Those of skill in the art with the disclosure provided herein will understand that the various steps of the methods disclosed herein may be omitted, rearranged, combined, and/or modified in various ways without departing from the scope of the disclosure.

The method 400 may include, at 402, forming an oxide layer 104 on a surface 106 of a substrate 102, the substrate comprising a semiconductor material. For example, the oxide layer 104 may be grown in situ on the substrate 106. Photolithography (e.g., photolithography) techniques may be used to define the shape of oxide layer 104. For example, portions of oxide layer 104 may be removed by etching such that oxide layer 104 is located within first portion 124 of surface 106 of substrate 102.

The method 400 may include, at 404, depositing a conductive layer 108 over at least a portion of the oxide layer 104. Conductive layer 108 may be contained within an outer edge 109 of oxide layer 104. The conductive layer 108 may not be in direct contact with and/or in direct electrical connection with the substrate 102.

The method 400 may include, at 406, depositing the first terminal 110 on the surface 106 of the substrate 102 such that the first terminal 110 is exposed along the surface 106 of the substrate 102 for surface mounting the capacitor 100.

The method 400 may include, at (408), depositing the second terminal 114 on the conductive layer 108 such that the second terminal 114 is exposed along the surface 106 of the substrate 102 for surface mounting the capacitor 100.

Fig. 5 shows a first insertion loss curve 502 of the capacitor 100 of fig. 1A to 1C compared to a second insertion loss curve 504 of a prior art MOS capacitor. The prior art capacitor may include an oxide layer formed on a surface of the substrate. The prior art capacitor may be disposed on the mounting surface such that the oxide layer is exposed along the top surface of the prior art capacitor. One or more wirebond connections may connect the oxide layer with the first conductive trace of the mounting surface. The substrate may contact and be electrically connected with the second conductive trace of the mounting surface.

For an input signal applied to the first terminal 110, insertion loss curves 502, 504 are generated using computer modeling of insertion loss of the capacitor 100 and prior art capacitors at the second terminal 114. For prior art capacitors, the second insertion loss curve 504 represents: insertion loss at the second conductive trace is for an input signal applied to the first conductive trace of the mounting surface. The second insertion loss curve 504 represents: for an input signal applied to the first conductive trace 204, the insertion loss of the capacitor 100 of the capacitor assembly 200 of fig. 2 at the second conductive trace 206.

The insertion loss curve 502 is greater than-1 decibel (dB) for frequencies in the range from about 5GHz to about 70 GHz; whereas for frequencies in the range from about 5GHz to about 60GHz, the insertion loss curve 502 is greater than about-0.5 dB; insertion loss curve 502 is greater than-0.35 dB for frequencies ranging from about 5GHz to 40 GHz; whereas for frequencies in the range from about 5GHz to 30GHz, the insertion loss curve 502 is greater than-0.30 dB.

Test method

The following sections provide example methods for testing insertion loss response curves of capacitors in accordance with aspects of the present disclosure. The insertion loss response curve of the capacitor may be measured using a Keithley 2400 series source measurement unit (Source Measure Unit, SMU) (e.g., keithley 2410-C SMU).

These and other modifications and variations to the present application may be practiced by those of ordinary skill in the art, without departing from the spirit and scope of the present application. Additionally, it should be understood that aspects of the various embodiments may be interchanged both in whole or in part. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the application so further described in such appended claims.

Application of

The capacitors described herein may be used in a variety of applications. The capacitor may be particularly useful in devices that process broadband radio frequency signals because the capacitor exhibits excellent performance at high frequencies (e.g., 20GHz or higher). Example devices include mobile devices (e.g., cell phones, tablet computers, etc.), cell towers, optical receiving subassemblies (Receiver Optical Sub Assembly, ROSA), optical transmitting subassemblies (Transmission Optical Sub Assembly, TOSA), and other Radio Frequency (RF) communication devices. Such devices may be particularly useful in military and space applications.

Claims

1. A capacitor, comprising:

a substrate comprising a semiconductor material;

an oxide layer formed on a surface of the substrate;

a conductive layer formed on at least a portion of the oxide layer;

a first terminal connected with the surface of the substrate; and

a second terminal connected to the conductive layer, wherein the oxide layer is connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal;

wherein each of the first and second terminals is exposed along the surface of the substrate for surface mounting the capacitor.

2. The capacitor of claim 1, wherein the first terminal is connected to the surface of the substrate at a location along the surface of the substrate spaced apart from the oxide layer.

3. The capacitor of claim 1, wherein:

the first terminal is spaced from the second terminal in the Y direction;

the oxide layer having an edge aligned with an X-direction, the X-direction being perpendicular to the Y-direction, the edge of the oxide layer being spaced from an end of the substrate in the Y-direction; and is also provided with

The first terminal is located between the edge of the oxide layer and the end of the substrate in the Y direction.

4. The capacitor of claim 1, wherein:

the oxide layer covers a first portion of the surface of the substrate that is different from a second portion of the surface of the substrate that is free of the oxide layer; and is also provided with

The first terminal is connected to the surface of the substrate within the second portion of the surface of the substrate.

5. The capacitor of claim 1, wherein the first terminal comprises a conductive material that directly contacts the surface of the substrate.

6. The capacitor of claim 1, wherein the semiconductor material of the substrate comprises silicon.

7. The capacitor of claim 1, wherein the oxide layer comprises silicon oxide.

8. The capacitor of claim 1, wherein the capacitor exhibits an insertion loss at the second terminal for an input signal applied to the first terminal, the insertion loss being greater than about-0.75 dB for frequencies ranging from about 5GHz to about 40 GHz.

9. The capacitor of claim 1, wherein the capacitor exhibits an insertion loss at the second terminal for an input signal applied to the first terminal, the insertion loss being greater than about-2 dB for frequencies ranging from about 5GHz to about 60 GHz.

10. A capacitor, comprising:

a substrate comprising a semiconductor material;

an oxide layer formed on a surface of the substrate;

a conductive layer formed on at least a portion of the oxide layer;

a first terminal connected with the surface of the substrate; and

a second terminal connected with the oxide layer, wherein the oxide layer is connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal;

wherein the capacitor exhibits an insertion loss at the second terminal and for an input signal applied to the first terminal, the insertion loss being greater than about-0.75 dB for frequencies ranging from about 5GHz to about 40 GHz.

11. The capacitor of claim 10, wherein the first terminal is connected to the surface of the substrate at a location along the surface of the substrate spaced apart from the oxide layer.

12. The capacitor as claimed in claim 10, wherein,

the first terminal is spaced from the second terminal in the Y direction;

13. The capacitor as claimed in claim 10, wherein,

14. The capacitor of claim 10, wherein the first terminal comprises a conductive material that directly contacts the surface of the substrate.

15. The capacitor of claim 10, wherein the semiconductor material of the substrate comprises silicon.

16. The capacitor of claim 10, wherein the oxide layer comprises silicon oxide.

17. The capacitor of claim 10, wherein the capacitor exhibits an insertion loss at the second terminal for an input signal applied to the first terminal, the insertion loss being greater than about-2 dB for frequencies ranging from about 5GHz to about 60 GHz.

18. A method of forming a capacitor, comprising:

forming an oxide layer on a surface of a substrate, the substrate comprising a semiconductor material;

depositing a conductive layer over at least a portion of the oxide layer;

depositing a first terminal on the surface of the substrate such that the first terminal is exposed along the surface of the substrate for surface mounting the capacitor; and

a second terminal is deposited on the conductive layer such that the second terminal is exposed along the surface of the substrate for surface mounting the capacitor.

19. The method of claim 18, wherein forming the oxide layer on the surface of the substrate comprises: forming the oxide layer within a first portion of the surface of the substrate that is different from a second portion of the surface of the substrate that is free of the oxide layer; and is also provided with

Depositing the first terminal includes: the first terminal is deposited within the second portion of the surface of the substrate.

20. A circuit board, comprising:

a circuit board substrate having a mounting surface;

a capacitor at least partially embedded within the circuit board substrate, the capacitor comprising:

a substrate comprising a semiconductor material;

an oxide layer formed on a surface of the substrate;

a conductive layer formed on at least a portion of the oxide layer;

a first terminal connected with the surface of the substrate; and

at least one via connected with one of the first terminal or the second terminal, the at least one via extending toward the mounting surface of the circuit board substrate.