CN117240255A

CN117240255A - CIC filter for SAR ADC and design method thereof

Info

Publication number: CN117240255A
Application number: CN202311257413.3A
Authority: CN
Inventors: 赵胜雷; 汤佳雁; 于龙洋; 崔宇轩; 张启龙; 张进成; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2023-09-26
Filing date: 2023-09-26
Publication date: 2023-12-15

Abstract

The application provides a CIC filter for an SAR ADC and a design method thereof, and the designed CIC filter can reduce the area of a capacitor array and the physical size of a comparator, realize higher integration level and smaller area occupation, reduce the design requirement of a preamplifier, reduce the power consumption of the preamplifier and save the consumption of hardware. The CIC filter provided by the application has relatively stable performance, is not influenced by factors such as ambient temperature, element parameter variation and aging, and the like, so that the SAR ADC based on the CIC filter provided by the application has advantages in long-term stability and reliability. The application can realize the unchanged sampling rate and improve the digital bit width and the precision of the ADC.

Description

CIC filter for SAR ADC and design method thereof

Technical Field

The application belongs to the technical field of circuit design, and particularly relates to a CIC filter for an SAR ADC and a design method thereof.

Background

Digital CIC filters are of great importance in the development of the ADC field. Initially CIC filters were introduced as a low cost, low power digital filtering solution to reject high frequency content in the input signal to reduce the requirements of the analog filter before the ADC. CIC filters evolve and evolve over time in the ADC field. Cascading multiple CICs to form a multi-stage CIC structure may enable higher order filtering. This helps to better suppress high frequency noise and improve signal quality.

The prior art generally adopts the following scheme:

1. a traditional pure SAR structure is used for realizing the high-precision ADC;

2. a mixed architecture of Pipeline-SAR is adopted to realize the high-precision ADC;

3. high accuracy of the ADC is realized by adopting methods such as noise shaping and the like;

4. ADC accuracy is improved by a digital decimation filter.

With the improvement of precision, the capacitance area of the SAR ADC is larger and larger, meanwhile, the ratio of the maximum capacitance value to the minimum capacitance value is multiplied, and more capacitance mismatch is brought while more power consumption is brought, so that the precision of the pure SAR structure and the Pipeline-SAR is greatly limited. Typically, the SAR ADC has a precision between 8 and 16 bits, and conventional methods have difficulty achieving SAR ADCs with 18 bits. The noise shaping principle and structure are complex, and meanwhile, the consumption of hardware is larger and the cost is higher. The digital CIC decimation filter can decimate the bandwidth of the signal in the frequency domain by reducing the sampling rate and filter out noise power in the high frequency range. But use reduces the sampling rate of the ADC, sacrificing the sampling rate in exchange for accuracy.

Disclosure of Invention

In order to solve the above problems in the prior art, the present application provides a CIC filter for SAR ADC and a design method thereof. The technical problems to be solved by the application are realized by the following technical scheme:

in a first aspect, the present application provides a CIC filter for a SAR ADC comprising: a 4-order integrator, a 4-order differentiator, and a frequency divider;

the output of the 4-order integrator is connected with the input end of the 4-order differentiator, and the input end of the frequency divider is connected with the frequency dividing end of the 4-order integrating arithmetic unit; the output end of the frequency divider is connected with the frequency dividing end of the 4-order differentiator; the input end of the frequency divider inputs a clock signal, and the output end of the frequency divider outputs a frequency division clock signal.

In a second aspect, the present application provides a method for designing a CIC filter for a SAR ADC, comprising:

CIC filters designed for SAR ADCs are paired in Modelsim;

generating a string of sine wave data in Matlab, and converting the sine wave data into digital data;

importing the digital data into the CIC filters, and simulating by a plurality of the CIC filters to obtain an output digital signal;

comparing the bit width of the output digital signal with the bit width of the input digital data, and confirming whether the CIC filter meets the design requirement.

The beneficial effects are that:

The present application will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a block diagram of a 4-order CIC filter provided by the present application;

FIG. 2 is a simulation graph of CIC amplitude-frequency response at normalized frequency provided by the application;

FIG. 3 is a functional simulation diagram of a 4-order CIC filter provided by the application;

FIG. 4 is a graph of 16-bit SAR ADC test results provided by the present application;

fig. 5 is a graph of the 18-bit SAR ADC FFT test results provided by the present application.

Detailed Description

The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.

As shown in fig. 1, the present application provides a CIC filter for a SAR ADC comprising: a 4-order integrator, a 4-order differentiator, and a frequency divider;

Wherein the sampling rate of the 4 th order integrator is K times the sampling rate of the 4 th order differentiator.

Noteworthy are: the interpolation operation of the filter may improve the quality of the signal by increasing the number of sample points, but may also amplify the duty cycle of the noise component in the signal spectrum. The decimation operation can reduce the power of the noise by reducing the sampling rate, as the noise is typically less power in the high frequency range. By using both the interpolation filter and the decimation filter, the quality of the signal as a whole can be improved while maintaining the same bandwidth as the original signal when the noise power introduced by the interpolation operation is relatively small. The interpolation and extraction sequences and the corresponding filtering operations are comprehensively considered, so that the optimal signal quality and noise suppression effect can be achieved.

The CIC filter is one of FIR filters, consisting of one or more pairs of integrating-comb filters. The CIC filter for the SAR ADC is a multistage cascade CIC filter, and the existing amplitude-frequency characteristics are expressed as follows:

where k represents the oversampling rate and L represents the number of stages of CIC filters for the SAR ADC.

If the CIC filters are cascaded in multiple stages, the stop band attenuation amplitude of the CIC filters is proportional to the cascade number L of the filters, and the stop band attenuation amplitude of the signals is increased by about 13.46dB when the CIC filters are added in one stage.

In order to ensure that the CIC filter can work correctly in a variable sampling frequency system, the bit width of the input data is W1, the bit width of the internal memory is W2, and the mathematical relationship exists between the input signal of the 4-order integrator and the output signal of the 4-order differentiator, which is expressed as:

W ₂ ＝W ₁ +Llog ₂ (RK)；

where W1 is the input data bit width of the filter, W2 is the maximum bit width of the internal registers, L is the number of stages of CIC filters for SAR ADC, K is the oversampling rate, and R is the differentiator order.

The block diagram of the CIC filter is designed as in fig. 1, where K represents the oversampling rate. The input signal passes through a 4-order integrating arithmetic unit and then passes through a 4-order differentiator to obtain an output result, wherein the sampling frequency of the differentiator is 1/K of the integrator. The ADC structure designed in the method has the advantages that the oversampling multiple is 4, the input digital bit width is 16, the order of the differentiator is 4, the CIC order is 4, the bit width of an internal register is 32, the output digital bit width is 20, 18 bits are intercepted, and finally, 18-bit-wide data are obtained, so that the design requirement is met.

Referring to fig. 2 to 5, the present application provides a method for designing a CIC filter for a SAR ADC, comprising:

CIC filters designed for SAR ADCs are paired in Modelsim;

as shown in connection with fig. 1, the CIC filter for SAR ADC simulated by the present application comprises: a 4-order integrator, a 4-order differentiator, and a frequency divider; the output of the 4-order integrator is connected with the input end of the 4-order differentiator, and the input end of the frequency divider is connected with the frequency dividing end of the 4-order integrating arithmetic unit; the output end of the frequency divider is connected with the frequency dividing end of the 4-order differentiator; the input end of the frequency divider inputs a clock signal, and the output end of the frequency divider outputs a frequency division clock signal. The sampling rate of the 4 th order integrator is K times that of the 4 th order differentiator. The design requirement is that the bit width satisfies the following formula:

W ₂ ＝W ₁ +Llog ₂ (RK)；

where W1 is the input data bit width of the CIC filter for the SAR ADC, W2 is the maximum bit width of the internal registers, L is the order of the CIC filter, K is the oversampling rate, and R is the order of the differentiator. The amplitude-frequency characteristics of the CIC filter for the SAR ADC are expressed as:

The designed 4-order CIC model was modeled under Matlab and then simulated. Fig. 2 is a simulation of the CIC amplitude-frequency response at normalized frequency, showing that the band attenuation of the CIC filter is about 45dB.

To verify the function of the CIC filter, a functional simulation of the CIC filter of the design is performed in Modelsim. Firstly, a CIC filter structure is realized in Modelism by Verilog, then a string of sine wave data is generated in Matlab, and the quantized digital data with 16 bits is imported into a CIC extraction filter, and a 20-bit digital signal is output by the filter. Fig. 3 is a functional simulation under Modelsim, where the input signal din is 16-bit data imported by Matlab and dout is an output 20-bit digital signal. It can be seen from fig. 3 that the amplitude of the output signal variation is approximately equal to the input signal, the output signal being delayed from the input signal.

The CIC filter is simulated by an analog circuit, a 16-bit SAR ADC is built by the CIC filter, the effective bit number is 14.82bits, the sampling rate is 2M, and the FFT test result is shown in figure 4.

The obtained 16-bit digital signal is connected with a multi-stage digital filter through an AMS digital-analog mixing mode, the number of stages of a decimation filter and the number of stages of an interpolation filter are both set to be 4, the decimation multiple is set to be 4, the interpolation multiple is set to be 2, and finally an 18-bit digital signal is output, and an FFT test result is shown in fig. 5, wherein the effective bit ENOB reaches 16.35bits, the sampling rate is 2M, the precision is improved while the speed is unchanged, and the function of expanding the 16-bit SAR ADC into an 18-bit SAR ADC is realized.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality.

The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims

1. A CIC filter for a SAR ADC, comprising: a 4-order integrator, a 4-order differentiator, and a frequency divider;

2. The CIC filter for SAR ADC of claim 1, wherein the sampling rate of said 4 th order integrator is K times the sampling rate of the 4 th order differentiator.

3. The CIC filter for SAR ADC of claim 1, wherein the input signal of said 4 th order integrator and the output signal of the 4 th order differentiator have a mathematical relationship expressed as:

W ₂ ＝W ₁ +Llog ₂ (RK)；

where W1 is the input data bit width of the CIC filter for the SAR ADC, W2 is the maximum bit width of the internal registers, L is the number of stages of the CIC filter for the SAR ADC, K is the oversampling rate, and R is the differentiator order.

4. The CIC filter for SAR ADC of claim 1, wherein the amplitude-frequency characteristic of the CIC filter for SAR ADC is expressed as:

5. A method of designing a CIC filter for a SAR ADC, comprising:

CIC filters designed for SAR ADCs are paired in Modelsim;

6. The method of designing a CIC filter for a SAR ADC of claim 5, wherein said CIC filter for a SAR ADC comprises: a 4-order integrator, a 4-order differentiator, and a frequency divider; the output of the 4-order integrator is connected with the input end of the 4-order differentiator, and the input end of the frequency divider is connected with the frequency dividing end of the 4-order integrating arithmetic unit; the output end of the frequency divider is connected with the frequency dividing end of the 4-order differentiator; the input end of the frequency divider inputs a clock signal, and the output end of the frequency divider outputs a frequency division clock signal.

7. The method for designing CIC filters for SAR ADC of claim 5, wherein the sampling rate of the 4 th order integrator is K times the sampling rate of the 4 th order differentiator.

8. The method of designing a CIC filter for a SAR ADC of claim 5, wherein said design requirement is that said bit width satisfies the following formula:

W ₂ ＝W ₁ +Llog ₂ (RK)；

where W1 is the input data bit width of the CIC filter for the SAR ADC, W2 is the maximum bit width of the internal registers, L is the order of the CIC filter, K is the oversampling rate, and R is the order of the differentiator.

9. The method for designing CIC filters for SAR ADC according to claim 5, wherein the amplitude-frequency characteristics of the CIC filters for SAR ADC are expressed as: