CN117238330A - Chip time sequence adjusting device and chip - Google Patents
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Abstract
The application relates to a chip time sequence adjusting device and a chip, wherein the device comprises at least two memory modules, and each memory module comprises a time sequence balancing unit and a plurality of memory library units; the time sequence balancing unit is respectively connected with the plurality of memory bank units, and is used for receiving the time sequence signals, carrying out delay fine compensation on the time sequence signals and then transmitting the time sequence signals to the memory bank units; and the storage library unit is used for storing data. The application solves the problem that the time sequences of the memory bank units at different positions in the chip array structure in the prior art cannot be balanced, and realizes the adjustment of the time sequences of the memory bank units at different positions in the chip.
Description
Technical Field
The present application relates to the field of microelectronic technologies, and in particular, to a chip timing adjustment device and a chip.
Background
The chip interior is generally composed of an array of memory bank cells (banks) and peripheral circuits. The memory cells are arranged in rows and columns, called "word lines" and "bit lines", respectively, to form an array structure of the chip. The peripheral circuits include row/column decoders, sense amplifiers, and read-write circuits, among other control circuits.
The memory cell has a large area and may be scattered at each corner of the chip. For the array structure of the whole chip, the distances from the time sequence signals to the memory bank units at different positions are different, so that the time sequence delays of the memory bank units at different positions are also different, and the time sequences of the memory bank units at different positions are not balanced.
Aiming at the problem that the time sequences of memory bank units at different positions are not balanced in the array structure of a chip in the related technology, no effective solution is proposed at present.
Disclosure of Invention
In this embodiment, a chip timing adjustment device and a chip are provided to solve the problem that in the chip array structure in the related art, the timings of the memory bank units at different positions are not balanced.
In a first aspect, in this embodiment, there is provided a chip timing adjustment apparatus, including at least two memory modules, the memory modules including a timing balance unit and a plurality of memory bank units;
the time sequence balancing unit is respectively connected with the plurality of memory bank units and is used for receiving time sequence signals, carrying out delay fine compensation on the time sequence signals and then transmitting the time sequence signals to the memory bank units;
the memory bank unit is used for storing data.
In some embodiments, the timing balancing unit is configured to perform delay fine compensation on the timing signal, so that delays of the timing signals received by the memory bank units at different positions in the memory module are the same.
In some of these embodiments, the timing balance unit is equal to chebyshev distances or euclidean distances between a plurality of the memory bank units.
In some embodiments thereof, further comprising at least one timing compensation module;
the time sequence compensation module is connected with the time sequence balance units in the adjacent storage modules; the time sequence compensation module is used for receiving time sequence signals, performing time delay coarse compensation on the time sequence signals and transmitting the time sequence signals to the time sequence balancing unit in the storage module.
In some embodiments, the memory module is connected with at least one timing compensation module, and the timing compensation module connected with one of the at least one timing compensation module is selected to perform timing signal after delay coarse compensation on the transmission of the memory module.
In some embodiments, the timing compensation module is connected to at least one adjacent memory module;
selecting the timing compensation module to be inactive, or active: and receiving the time sequence signal, performing delay coarse compensation and transmitting to at least one storage module.
In some embodiments, the timing compensation module is configured to perform delay coarse compensation on the timing signal, so that delays of the timing signals received by the memory modules at different positions in the chip timing adjustment device are the same.
In some of these embodiments, the memory cells are distributed in a matrix configuration in the memory module.
In some of these embodiments, the memory vault unit includes at least one memory subunit.
In a second aspect, in this embodiment, a chip timing adjustment chip is provided, in which the chip timing adjustment device described in the first aspect is built.
Compared with the related art, the chip time sequence adjusting device and the chip provided in the embodiment comprise at least two memory modules, wherein each memory module comprises a time sequence balancing unit and a plurality of memory library units; the time sequence balancing unit is respectively connected with the memory bank units, and is used for receiving time sequence signals, carrying out delay fine compensation on the time sequence signals and then transmitting the time sequence signals to the memory bank units; and the storage library unit is used for storing data. The device solves the problem that the time sequences of the memory bank units at different positions in the chip in the prior art cannot be balanced, and realizes the adjustment of the time sequences of the memory bank units at different positions in the chip.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a chip timing adjustment device according to an embodiment;
FIG. 2 is a schematic diagram of a chip timing adjustment device according to another embodiment;
FIG. 3 is a schematic diagram of a chip timing adjustment device according to another embodiment;
FIG. 4 is a timing signal transfer schematic diagram of a conventional chip;
FIG. 5 is a schematic diagram of a chip timing adjustment device according to a preferred embodiment;
FIG. 6 is a flow chart of a method of a chip timing adjustment device according to an embodiment;
fig. 7 is a schematic diagram of a hardware structure of a terminal of a chip timing adjustment method according to an embodiment.
In the figure: 10. a storage module; 11. a timing compensation module; 12. a storage library unit; 13. a timing balancing unit; 102. a processor; 104. a memory; 106. a transmission device; 108. and an input/output device.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used herein, are intended to encompass non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
Fig. 1 is a schematic structural diagram of a chip timing adjustment device according to the present application, and it should be noted that the interaction relationship between the memory bank units 12 in fig. 1 is not described in the present application. In this embodiment, the chip timing adjustment device includes at least two memory modules 10, and the memory modules 10 include a timing balance unit 13 and a plurality of memory bank units 12.
A memory bank unit 12 for storing data.
Specifically, the chip timing adjustment device in this embodiment includes at least two memory modules 10, where the memory modules 10 include a timing balance unit 13 and a plurality of memory bank units 12, and it should be noted that the chip timing adjustment device in this embodiment further includes peripheral circuits including a row/column decoder, a sense amplifier, a read/write circuit, and other control circuits. In the present application, the data caching and storage functions are realized mainly by the storage module 10.
In the memory module 10, the timing balancing unit 13 is connected to the plurality of memory bank units 12, and the timing balancing unit 13 is configured to receive the timing signal, delay the timing signal, and fine compensate the timing signal, and transmit the delayed timing signal to the memory bank units 12.
Specifically, the timing balance unit 13 receives the timing signal, performs delay fine compensation on the timing signal, and transmits the timing signal to the memory bank units 12, so that the delays of the timing signal reaching each memory bank unit 12 are equal or identical as far as possible, and delay fine compensation of the timing signal between the memory bank units 12 in the chip memory module 10 is realized, wherein the delay compensation function of the timing signal between the memory bank units 12 implemented by the timing balance unit 13 is defined as delay fine compensation. The timing signal in this embodiment is a clock signal generated by a clock source of the chip. In other embodiments, the timing signal may be another timing signal such as a crystal oscillator signal.
In other embodiments, the delay of the timing balancing unit 13 in the different memory modules 10 is finely compensated, and the delay of the timing signal reaching each memory bank unit 12 is adjusted, which is not required to be equal or consistent as much as possible between the memory bank units 12 in all the memory modules 10, but may be that the memory bank units 12 in the different memory modules 10 receive the timing signals with different delays according to the requirements, which is not limited by the present application.
A memory bank unit 12 for storing data.
Specifically, each memory cell 12 is connected to other memory cells 12, wherein the horizontal direction connection is referred to as a "word line" and the vertical direction connection is referred to as a "bit line"; in accessing data, a specific word line and bit line can be selected by an inputted address, the intersection of the word line and bit line is the selected memory cell 12, and then the data access operation is performed on the memory cell 12.
Through the chip time sequence adjusting device, the time sequence balancing unit 13 is respectively connected with the plurality of memory bank units 12, the time sequence balancing unit 13 is used for receiving time sequence signals, and the time sequence signals are transmitted to the memory bank units 12 after delay fine compensation, so that the problem that in a chip array structure in the prior art, the time sequences of the memory bank units 12 at different positions cannot be balanced is solved, and the time sequences of the memory bank units 12 at different positions in a chip are balanced.
In some embodiments, the timing balancing unit 13 is configured to perform delay fine compensation on the timing signal, so that delays of receiving the timing signal by the memory bank units 12 at different positions in the memory module 10 are the same.
Specifically, the timing balance unit 13 is placed in the memory module 10 such that the distances from each memory cell 12 to the timing balance unit 13 are equal, thereby making the time of the timing signal from the timing balance unit 13 to each memory cell 12 equal. The time delay balance unit 13 performs time delay fine compensation on the time sequence signals, so that the time delays of the time sequence signals received by the memory bank units 12 at different positions in the memory module 10 are the same, and further the time delay balance of the time sequence signals among the memory bank units 12 in the same memory module 10 is realized.
In some of these embodiments, the chebyshev distance or euclidean distance between the timing balance unit 13 and the plurality of memory cells 12 is equal.
Specifically, as shown in fig. 1, when the distance between the timing balance unit 13 and the memory cells 12 in the memory module 10 is chebyshev, it is assumed that m memory cells 12 are in the whole chip, m is a positive integer greater than or equal to 9, each memory cell 12 is regarded as a target point, the m points are uniformly distributed in an array, and nine adjacent target points are selected as the memory module 10, respectivelyThen for each memory module 10, since the nine target points are uniformly distributed in an array, the chebyshev distances from the center point to the eight adjacent target points are equal, replacing the memory bank unit 12 of the center point position with one timing balancing unit 13. A coordinate system is established by taking the center point of the memory module 10 and the position of the time sequence balancing unit 13 as an origin, and the coordinate of the time sequence balancing unit 13 is +.>Let the coordinates of one adjacent target point be +.>The timing balance unit 13 to eight adjacent targetsThe Chebyshev distance of the punctuation can be expressed asBy equalizing the chebyshev distances of the timing equalization unit 13 and the memory bank units 12 in the memory module 10, and further controlling the time of the timing signals from the timing equalization unit 13 to each memory bank unit 12 to be equal, delay equalization of the timing signals between the memory bank units 12 in the same memory module 10 is achieved.
FIG. 2 is a schematic diagram of a chip timing adjustment device according to the present embodiment, as shown in FIG. 2, when the distance between the timing balance unit 13 and the memory cells 12 in the memory module 10 is Euclidean distance, it is assumed that n memory cells 12 are in the whole chip, n is a positive integer greater than or equal to 4, each memory cell 12 is regarded as a target point, the n points are uniformly distributed in an array, four adjacent target points are selected as the memory module 10, and the target points are respectivelyTaking the point at which the diagonals of the memory module 10 intersect as the placement position of the timing balance unit 13, the euclidean distances of the timing balance unit 13 to the four adjacent target points are equal. By equalizing the euclidean distance of the timing equalization unit 13 and the memory cells 12 in the memory module 10, and further controlling the time of the timing signal from the timing equalization unit 13 to each memory cell 12 to be equal, delay equalization of the timing signal between the memory cells 12 in the same memory module 10 is achieved.
By the two different definitions of the distances between the time sequence balancing unit 13 and the memory bank units 12 in the memory module 10, a time delay balancing scheme of the time sequence signal is correspondingly formulated, so that chebyshev distances or euclidean distances between the time sequence balancing unit 13 and the memory bank units 12 are respectively equal, and the diversity and flexibility of the time delay balancing scheme are further improved.
In some of these embodiments, the chip timing adjustment device further includes at least one timing compensation module 11, where the timing compensation module 11 is connected to the timing balancing unit 13 in the adjacent memory module 10; the timing compensation module 11 is configured to receive the timing signal, perform delay coarse compensation on the timing signal, and transmit the timing signal to the timing balancing unit 13 in the memory module 10.
Specifically, the delay compensation function of the timing signals between the memory modules 10 implemented by the timing compensation module 11 is defined as delay coarse compensation, and the timing signals after the delay coarse compensation are transmitted to at least one memory module 10 through the timing compensation module 11, so that the accuracy of the timing signals is ensured.
In this embodiment, the time delay compensation module 11 performs time delay coarse compensation on the time sequence signals, so that the time delays of receiving the time sequence signals by the memory modules 10 at different positions in the time sequence adjusting device are the same. In other embodiments, the time sequence signals with different delays may be received by different memory modules 10 after the delay coarse compensation according to the requirement, which is not limited by the present application.
In some embodiments, the memory module 10 is connected to at least one timing compensation module 11, and one of the connected timing compensation modules 11 can be selected to perform delay coarse compensation on the transmission of the timing signal by the memory module 10.
In some of these embodiments, the timing compensation module 11 is connected to at least one adjacent memory module 10 and is capable of selecting the timing compensation module 11 to be inactive, or active: the timing signal is received and is transmitted to at least one memory module 10 after delay coarse compensation.
Specifically, fig. 3 is a schematic structural diagram of a chip timing adjustment device according to the present embodiment, as shown in fig. 3, a timing compensation module 11 receives a timing signal output by a clock source, performs delay coarse compensation according to the timing signal, and transmits the timing signal to a memory module 10 to compensate for delay of the timing signal between different memory modules 10, thereby solving the timing adjustment problem of the memory modules 10 at different positions.
Specifically, the timing compensation module 11 receives the timing signal output by the clock source, and transmits the timing signal after the coarse delay compensation to the timing balancing unit 13 in the memory module 10, where the timing balancing unit 13 balances the delays of the timing signals between the memory bank units 12 in the memory module 10 according to the timing signal, so as to realize the timing balancing of the memory bank units 12 in different positions in the chip.
In some embodiments, the timing compensation module 11 is configured to perform coarse delay compensation on the timing signal, so that delays of receiving the timing signal by the memory modules 10 at different positions in the chip timing adjustment device are the same.
Specifically, the timing compensation module 11 performs coarse delay compensation on the timing signal, so that the delays of receiving the timing signal by the memory modules 10 at different positions in the chip timing adjustment device are the same.
In some of these embodiments, the memory cells 12 are distributed in a matrix configuration within the memory module 10.
In particular, the memory cells 12 are distributed in a matrix configuration within the memory module 10, and the array of memory cells 12 typically takes the form of a square or matrix to reduce the overall chip area and facilitate access to data. Taking a chip with a storage capacity of 4K bits as an example, a total of 12 address lines are required to ensure that each memory cell 12 can be selected. If the array of memory cells 12 is arranged in a stripe pattern comprising only one column, a 12/4K bit decoder is required, but if the array is arranged in a square pattern comprising 64 rows and 64 columns, only a 6/64 bit row decoder and a 6/64 bit column decoder are required, the row and column decoders may be arranged on both sides of the array of memory cells 12, respectively, with a total of 4096 intersections of 64 rows and 64 columns, each corresponding to a memory bit. When the memory cells 12 are arranged in a long stripe shape, the connection between the memory cells 12 and the data input/output terminal becomes longer, and the longer the connection is, the larger the delay on the connection is, so that the longer the connection is, the slower the read/write speed and the inconsistency of the connection delays of different memory cells 12 are caused. Therefore, the memory cells 12 are distributed in a matrix structure in the memory module 10, which can reduce the chip area and facilitate the access of data.
In some of these embodiments, the memory vault unit 12 includes at least one memory subunit.
In particular, the memory subunit in this embodiment is specifically SRAM (Static RAM), i.e. static RAM, which is composed of transistors. These transistors do not need to be refreshed, but lose information when shut down or powered off; SRAM operates very fast, typically at speeds of 20ns or more. One memory cell 12 includes at least one memory cell (bitcell), and the memory cells in the memory cell 12 share a control logic (control logic), and a plurality of memory cells form a memory cell array (bitcell), that is, the memory cell 12, for storing data.
In some embodiments, the timing compensation module 11 and the timing balancing unit 13 may be implemented by EMA (extra margin adjust, delay adjustment circuit), DCO (data controlled oscillator), RC (resistor capacitor circuit), or the like according to specific application scenarios and requirements.
The present embodiment is described and illustrated below by way of preferred embodiments.
Fig. 4 is a timing signal transmission schematic diagram of a conventional chip, and fig. 5 is a schematic diagram of a chip timing adjustment device according to the preferred embodiment.
As shown in fig. 4, B1 to B9 are memory modules 10, B11 to B99 are memory bank units 12, and the memory bank units 12 in each memory module 10 are connected to adjacent other memory bank units 12. In fig. 4, each timing signal is connected to the memory cells 12 along the timing signal in each memory module 10 to realize the transmission of the timing signal to each memory module 10, but the present application is not limited to the specific location of the connection to the memory cells 12, for example, the locations of the memory cells 12 connected to the memory modules B1/B4 are different; inside the memory module 10, the timing signals are transferred through control paths arranged along rows and columns between the memory cells 12.
Wherein, the delay schematic value table of the memory bank unit 12 is shown in table 1, the row number indicates the number of the memory bank unit 12 in the memory module 10, and the column number indicates the memory module 10 where the memory bank unit 12 is located; for example, the 1 st row and 1 st column cell refers to the memory cell b11, and the 9 th row and 9 th column cell refers to the memory cell b99; the delay value calculating method specifically comprises the following steps: taking the delay value of b17 as 0 as a standard, adding 1 to the delay value of each time the time sequence signal passes through one memory bank unit 12, adding 10 to the delay value of each time the time sequence signal passes through one memory module 10; as can be seen from the connection relationship of the control channels, the time sequence signal passes through one memory bank unit 12 in the memory module 10, and means that the time sequence signal reaches the next memory bank unit 12 through the memory bank unit 12; the time sequence signal passing through one memory module 10 means that the time sequence signal passes through the path length of one memory module 10 to reach the next memory module 10.
It should be noted that, table 1 is a schematic delay value, and in practical applications, the delay values passing through different memory cells 12/memory modules 10 may be different, and may be obtained through simulation, and the embodiment shown in fig. 4 is only an ideal timing control device of a conventional chip.
TABLE 1
In order to solve the delay problem of each memory bank unit 12 in fig. 4, the conventional chip layout is improved to the chip time sequence adjusting device shown in fig. 5, B1 to B9 are memory modules 10, S1 to S12 are time sequence compensating modules 11, B11 to B99 are memory bank units 12, E1 to E9 are time sequence balancing units 13, and the memory modules 10 in fig. 5 are connected with adjacent time sequence compensating modules 11; the timing compensation modules 11 are respectively connected to control paths for the propagation of timing signals; the timing balance unit 13 is connected to the adjacent memory bank unit 12 and the adjacent timing compensation module 11. In the preferred embodiment, 1 timing compensation module 11 is disposed between two adjacent memory modules 10, i.e. s1\s2\s6\s7\s11\s12 in fig. 5, and the memory modules 10 of the first row and the second row share one clock signal, and the memory modules 10 of the third row and the fourth row (not shown) share one clock signal, so that the timing compensation module 11 is disposed between the memory modules 10 of the first row and the second row, the third row and the fourth row (not shown), i.e. s3\s4\s5\s8\s9\s11\s12 in fig. 5, so as to avoid the problem that the timing compensation module 11 is insufficient.
The s1\s2\s6\s7\s11\s12 in fig. 5 may be moved to a position where the timing signals pass, that is, S3, S1, S6, S4, S2, S7, S5 are all disposed along the first timing signal line, and S8, S11, S9, S12, S10 are respectively disposed along the second timing signal line, so for convenience of drawing and description, the schematic of fig. 5 is adopted; in fig. 5, each time sequence signal passes through the corresponding time sequence compensation module 11 and then is connected with each memory module 10, so that coarse delay compensation is realized, and the delay reaching each memory module 10 is equal; the time sequence compensation module 11 is connected with the corresponding time sequence balancing unit 13 in the memory module 10, and the time sequence balancing unit 13 in the memory module 10 is reached after the time delay coarse compensation of the time sequence signal; the time sequence signals after the time delay coarse compensation are respectively transmitted to each storage library unit 12 after the time delay fine compensation is carried out by an internal time sequence balancing unit 13 in the storage module 10; in each memory module 10, the memory bank units 12 in the middle of the original positions are replaced by the placement time sequence balancing units 13, and the time sequence balancing units 13 are controlled to be equal to the chebyshev distance/Euclidean distance of each memory bank unit 12, so that the time sequences output from the time sequence balancing units 13 to the memory bank units 12 are equal, and the time delay fine compensation is completed; it should be noted that the present preferred embodiment is only an ideal improved chip timing adjustment device, and is only used to illustrate the timing compensation principle of the timing adjustment device of the present application, and the present application is not limited to the replacement of the placement timing balancing unit 13 with the originally placed memory bank unit 12, as long as the delay from the timing balancing unit 13 to each memory module 10 is ensured to be equal or consistent as possible.
TABLE 2
Table 2 is a schematic value table of time delay coarse compensation of the time sequence compensation module 11 according to the preferred embodiment for the corresponding memory module 10, wherein in table 2, the row number represents the memory module 10, the column number represents the time sequence compensation module 11, and the corresponding cell represents the time sequence compensation value of the time sequence compensation module 11 of the column for the memory module 10 of the row; the delay values can be referred to in table 1. In the cell of table 2, "/" indicates that the timing compensation module 11 corresponding to the cell does not perform the coarse delay compensation on the memory module 10 corresponding to the cell.
TABLE 3 Table 3
Table 3 is a schematic value table of delay fine compensation of the time-sequence balancing unit 13 in the memory module 10 to the memory cell 12, in which the row number in table 3 indicates the memory cell 12 in the memory module 10, the column number indicates the time-sequence balancing unit 13 in the memory module 10, and the corresponding cell indicates the time-sequence compensation value of the time-sequence balancing unit 13 in the memory module 10 to the memory cell 12; for example, the 1 st row and 1 st column values refer to the delay values compensated by the timing balance unit E1 in the memory module B1 to the memory bank unit B11, and the 9 th row and 9 th column values refer to the delay values compensated by the timing balance unit E9 in the memory module B9 to the memory bank unit B99; because the time sequence balancing unit 13 is equal to the chebyshev distance/the euclidean distance of each memory bank unit 12 in each memory module 10, the time sequence balancing unit 13 is used for indicating that the delay fine compensation value of each memory bank unit 12 is 1; the time sequence balance of all the memory cells 12 is achieved through the time delay coarse compensation of the time sequence compensation module 11 and the time delay fine compensation of the time sequence balance unit 13 in the preferred embodiment.
Therefore, the chip timing adjustment device of the preferred embodiment compensates the time delay of the timing signals between the different memory modules 10 through the timing compensation module 11, balances the time delay of the timing signals between the surrounding memory bank units 12 through the timing balancing unit 13, thereby solving the problem that the timing of the memory bank units 12 at different positions is not balanced in the chip array structure in the prior art, and realizing the adjustment of the timing of the memory bank units 12 at different positions in the chip.
The embodiment also provides a chip time sequence adjusting method. Fig. 6 is a flowchart of a timing balancing method in the chip of the present embodiment, as shown in fig. 6, the flowchart includes the following steps:
step S301, performing delay coarse compensation on signal delay of time sequence signals among different memory modules.
Step S302, the time sequence balance unit of the memory module receives the time sequence signal, and the time sequence signal is transmitted to the memory bank unit after delay fine compensation.
Specifically, the signal delays of time sequence signals among different memory modules are subjected to delay coarse compensation, so that the delays among the memory modules are consistent or equal as much as possible; and outputting the time sequence signal subjected to the time delay coarse compensation to a time sequence balancing unit of the memory module, and transmitting the time sequence signal to a memory bank unit after performing time delay fine compensation on the time sequence signal through the time sequence balancing unit. Through the steps, firstly, the time delay coarse compensation is carried out on different memory modules, and then the time sequence signal of the memory bank units in the memory modules is carried out with the time delay fine compensation, so that the problem that the time sequences of the memory bank units at different positions are not balanced in a chip array structure in the prior art is solved, and the time sequences of the memory bank units at different positions in a chip are balanced.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or similar computing device. For example, the chip timing balancing method of the present embodiment is shown in fig. 7. As shown in fig. 7, the terminal may include one or more (only one is shown in fig. 7) processors 102 and a memory 104 for storing data, wherein the processors 102 may include, but are not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely illustrative and is not intended to limit the structure of the terminal. For example, the terminal may also include more or fewer components than shown in fig. 7, or have a different configuration than shown in fig. 7.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to the above-described chip timing balancing method in the present embodiment, and the processor 102 executes the computer program stored in the memory 104 to perform various functional applications and data processing, that is, implement the above-described method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
There is also provided in this embodiment a computer device comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the computer device may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, performing delay coarse compensation on signal delay of time sequence signals among different storage modules.
S2, receiving the time sequence signal through a time sequence balancing unit of the memory module, and transmitting the time sequence signal to the memory bank unit after delay fine compensation.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
In this embodiment, a chip timing adjustment chip incorporating any of the chip timing adjustment devices of the above embodiments may be provided.
In addition, in combination with the chip timing balancing method provided in the above embodiment, a storage medium may be provided in this embodiment. The storage medium has a computer program stored thereon; the computer program, when executed by a processor, implements the chip timing balancing method described in the above embodiments.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure in accordance with the embodiments provided herein.
It is to be understood that the drawings are merely illustrative of some embodiments of the present application and that it is possible for those skilled in the art to adapt the present application to other similar situations without the need for inventive work. In addition, it should be appreciated that while the development effort might be complex and lengthy, it will nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and further having the benefit of this disclosure.
The term "embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (10)
1. The chip time sequence adjusting device is characterized by comprising at least two memory modules, wherein each memory module comprises a time sequence balancing unit and a plurality of memory library units;
the time sequence balancing unit is respectively connected with the plurality of memory bank units and is used for receiving time sequence signals, carrying out delay fine compensation on the time sequence signals and then transmitting the time sequence signals to the memory bank units;
the memory bank unit is used for storing data.
2. The chip timing adjustment device according to claim 1, wherein the timing balancing unit is configured to perform delay fine compensation on the timing signals, so that delays of the timing signals received by the memory bank units at different positions in the memory module are the same.
3. The chip timing adjustment apparatus according to claim 2, wherein chebyshev distances or euclidean distances between the timing balance unit and the plurality of memory bank units are equal.
4. The chip timing adjustment device of claim 1, further comprising at least one timing compensation module;
the time sequence compensation module is connected with the time sequence balance units in the adjacent storage modules; the time sequence compensation module is used for receiving time sequence signals, performing time delay coarse compensation on the time sequence signals and transmitting the time sequence signals to the time sequence balancing unit in the storage module.
5. The chip timing adjustment device according to claim 4, wherein the memory module is connected with at least one of the timing compensation modules, and the timing compensation module connected to one of the memory modules is selected to perform timing signal after delay coarse compensation on the transmission of the memory module.
6. The chip timing adjustment device of claim 4, wherein the timing compensation module is coupled to at least one adjacent memory module;
selecting the timing compensation module to be inactive, or active: and receiving the time sequence signal, performing delay coarse compensation and transmitting to at least one storage module.
7. The chip timing adjustment device of claim 4, wherein the timing compensation module is configured to perform coarse delay compensation on the timing signal, so that delays of the timing signals received by the memory modules at different positions in the chip timing adjustment device are the same.
8. The chip timing adjustment device according to claim 1, wherein the memory bank units are distributed in a matrix structure in the memory module.
9. The chip timing adjustment device of claim 1, wherein the memory bank unit comprises at least one memory subunit.
10. A chip, wherein the chip timing adjustment device according to any one of claims 1 to 9 is incorporated.
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