CN117234994A - Dynamically configurable cross switch interconnection structure circuit - Google Patents

Abstract

A dynamically configurable crossbar interconnect circuit capable of automatically switching transfer paths; the transfer paths can be dynamically switched, and can be changed within a single clock cycle instead of being statically maintained for the conventional crossbar interconnect; the method comprises the steps that input data can be aggregated and multiplexed, the aggregation refers to the aggregation of the data of different input ports to one output port, the sequential output is designated, and the multiplexing refers to the dispersion of the data of one input port to a plurality of output ports; the input data can be sorted, and the input data can be selected according to a certain rule. The invention is suitable for the cross switch interconnection of the multi-core processor chip, and can lead the cross switch interconnection structure to realize data transmission more flexibly and efficiently.

Description

Dynamically configurable cross switch interconnection structure circuit

Technical Field

The invention relates to a dynamically configurable cross switch interconnection structure circuit, in particular to an embedded cross switch on-chip interconnection structure which has high requirements on-chip data bandwidth and data transfer delay, complex data transfer paths and more integrated processor cores.

Background

As the number of integrated cores of a multi-core processor chip increases further, so does the communication requirements associated therewith. On-chip interconnect structures are an important direction of multi-core system research. The current on-chip interconnect can be largely divided into three types, namely bus interconnect, network-on-chip interconnect and crossbar interconnect.

The shared bus structure is simple, and when the communication requirement is smaller, a higher working frequency can be realized. However, since only one processor core can perform a data transmission task at a unit time, when the number of integrated processor cores increases, the delay overhead of the structure increases sharply, and the improvement of bandwidth and throughput rate is limited.

The network-on-chip interconnection is a network topology based on message switching, and each node in the network is connected with a router. The router is connected with other adjacent routers through local interconnection lines. The communication between the nodes is realized through a plurality of hops, and the global interconnection line can be converted into the local interconnection line, so that the power consumption and the transmission line effect caused by the global interconnection line can be effectively solved, but the transmission delay is very large when the data is transmitted on the network on chip. Thus, network-on-chip interconnects are mainly used in the case of hundreds of processor cores integrated in a chip.

The crossbar interconnect provides the greatest possible connection between the various processor cores, corresponding to each processor core on the bus having an independent set of bus structures. The cross switch interconnection is a special topology, the connection between any two nodes in the topology structure does not need to pass through other nodes, and the distance between any two nodes is 1. An n x m crossbar interconnect has n input ports and m output ports, each input line and all output lines having a junction with a switch: for selecting whether to close or open the crossover point. To ensure the correctness of the outputs, it is provided that each output can only be connected to one input, while one input can be connected to a plurality of outputs. The cross switch interconnection is simplified to be point-to-point connection in hardware realization, the internal bandwidth is high, the expandability is good, and the high-capacity data exchange can be provided. However, the current cross switch interconnection design also has obvious defects:

(1) The method directly connects the sender with the specific receiver, once the connection is established, the connection relation is kept unchanged in the whole data transmission process, and the flexibility is lacked;

(2) The function of the method is that only one channel is established between one input and one output, so that data is transmitted downwards, and flexible transmission channels can not be established between a plurality of inputs and one output, between one input and a plurality of outputs or between a plurality of inputs and a plurality of outputs;

the present invention is primarily directed to improving upon these two deficiencies.

Disclosure of Invention

The invention solves the technical problems that: the circuit of the cross switch interconnection structure is suitable for cross switch interconnection of a multi-core processor chip, and can enable the cross switch interconnection structure to realize data transmission more flexibly and efficiently.

The invention solves the technical problems by the following technical proposal:

a dynamically configurable crossbar interconnect structure circuit, comprising: a first input buffer unit 101, a second input buffer unit 102, a third input buffer unit 103, a crossbar matrix 100, an input control unit 104, a configuration buffer unit 105, a configuration update control unit 106, and an index pointer 107;

the first input buffer unit 101, the second input buffer unit 102 and the third input buffer unit 103 are implemented by adopting FIFO units, and respectively buffer three paths of input data;

the input control unit 104 analyzes the configuration data input by the configuration buffer unit 105, reads the data of the three input buffer units under the guidance of the analysis result, and outputs the data to the crossbar 100;

the configuration buffer unit 105 outputs the configuration data of the location register corresponding to the index pointer to the crossbar 100, the input control unit 104, and the configuration update control unit 106 under the action of the index pointer 107;

the configuration update control unit 106 analyzes the configuration data output from the configuration buffer unit 105, and the analysis result updates the index pointer 107;

the index pointer 107 registers address information of configuration data to be read out from the configuration buffer unit in the next clock cycle;

the crossbar matrix 100 performs multiplexing on input data under control of configuration data output from the configuration buffer unit 105, and controls path gating and output.

Further, the first input buffer unit 101, the second input buffer unit 102 and the third input buffer unit 103 are implemented by FIFO units; the input control unit 104 and the crossbar switch matrix 100 are combined logic units, wherein the crossbar switch matrix 100 is realized by a multiplexer; the configuration buffer unit 105 is a register group, and the index pointer 107 is a register; the configuration update control unit 106 is a sequential logic unit.

Further, the configuration data of the position register corresponding to the index pointer comprises switch control information of a cross switch matrix, selection information of input data, arrangement information of output data and index pointer change rule information.

Further, the configuration update control unit 106 analyzes the configuration data output from the configuration buffer unit 105, and the analysis result updates the index pointer 107, specifically:

(1) In the analysis process, firstly judging whether the configuration data is valid or not, if so, entering the step (2), otherwise, suspending the analysis process and waiting for the configuration data to be valid;

(2) Judging whether the index pointer needs to be cleared, if so, outputting zero by the index pointer, and then entering the step (3); if zero clearing is not needed, directly outputting index pointer data;

(3) Judging whether to execute the cyclic configuration according to the configuration data, if the cyclic configuration is executed, recording the number of times of the cyclic configuration, comparing the number of times with the number of times of the cyclic configuration designated in the configuration data, and outputting the next address of the configuration information to an index pointer if the number of times of the cyclic configuration is equal to the number of times of the cyclic configuration designated in the configuration data; if not, outputting a configuration initial index address contained in the configuration data to an index pointer; if loop configuration is not performed, the next address of the configuration information is directly output to the index pointer.

Further, a control closed loop is formed among the configuration buffer unit 105, the index pointer 107 and the configuration update control unit 106, so as to realize automatic control.

Further, the configuration buffer unit 105 includes a configuration buffer register set 205 and a configuration register 200;

the configuration buffer register set 205 includes a plurality of configuration buffer registers, the configuration buffer register set 205 receives the output of the index pointer as address information input, selects the data of the corresponding address in the configuration buffer register set, and writes the data into the configuration register 200;

the data information in the configuration register 200 is output as configuration data.

Further, in the configuration register 200 and the configuration buffer register set 205, the configuration data format is the same, including a configuration valid bit 210, a configuration reset valid bit 211, a loop configuration field 250, an output 1 selection configuration field 220, an output 2 selection configuration field 230, and an output 3 selection configuration field 240;

the output 1 selection configuration field, the output 2 selection configuration field and the output 3 selection configuration field define three paths of output data line transmission rules of the cross switch matrix;

configuration valid bit 210, only if this bit is a '1', indicates that the configuration data in this register is valid;

configuring a reset valid bit 211, when the bit is '1', indicating that the configuration data in the register is the last valid configuration data, and the data in the later configuration buffer register is invalid; when this bit is '0', it indicates that the configuration data in this register is not the last valid configuration data, and the data in the later configuration buffer register is valid.

Further, the output 1 select configuration field 220 controls the first path data and its transmission path of the crossbar matrix output, including an output 1 select configuration valid bit 221, an output 1 data forced invalid bit 222, an output 1 strong timing valid bit 223, and an output 1 multi-path select bit 224;

output 1 selects configuration valid bit 221, which indicates that the configuration data in the output 1 select configuration field is valid only if the bit is '1';

the output 1 data forces the invalid bit 222, which when it is '1' indicates that the first way data output by the crossbar matrix needs to be forced to all '0'.

An output 1 strong timing valid bit 223, when this bit is '1', indicating that the configuration update control unit can update the configuration index pointer only after the output 1 completes one data transfer, and reads the next configuration buffer register;

the output 1 multiplexing bit 224, which is a binary data of bit width 2, defines the path selection of the crossbar matrix.

Further, the output 2 select configuration field 230 controls the second path of data and the transfer path of the crossbar matrix output, including an output 2 select configuration valid bit 231, an output 2 data forced invalid bit 232, an output 2 strong timing valid bit 233, and an output 2 multiple select bit 234;

output 2 selects configuration valid bit 231, only if this bit is '1', indicating that the configuration data in this output 2 select configuration field is valid; an output 2 data forced invalid bit 232, which when it is '1', indicates that the second path data output by the crossbar matrix needs to be forcedly set to all '0'; outputting a 2 strong timing valid bit 233, when the bit is '1', which indicates that the configuration update control unit can update the configuration index pointer only after the output 2 completes one data transfer, and reading the next configuration buffer register; output 2 multiplexing bits 234, which are binary data of bit width 2, define the path selection of the crossbar matrix;

the output 3 select configuration field 240 controls the third path of data and transfer paths of the crossbar matrix output, including an output 3 select configuration valid bit 241, an output 3 data force invalid bit 242, an output 3 strong timing valid bit 243, and an output 3 multiple select bit 244;

output 3 selects the configuration valid bit, only if this bit is '1', indicating that this output 3 selects the configuration data in the configuration field to be valid; outputting 3 a data forced invalid bit, wherein when the bit is '1', the third path of data output by the cross switch matrix is required to be forcedly set to be all '0'; outputting 3 strong time sequence valid bit, when the bit is '1', the configuration updating control unit can update the configuration index pointer only after the output 3 completes one data transmission, and reading the next configuration buffer register; the output 3 multiple select bits, which are binary data of bit width 2, define the path selection of the crossbar matrix.

Further, the loop configuration field 250 includes a loop configuration valid bit 251, a loop number specifying bit 252, and a loop start address 253;

a loop configuration valid bit 251, which indicates that the configuration data in the register is to be configured in a loop only when the bit is '1', and the address corresponding to the register is the end address of each loop configuration; when the bit in the configuration register is '1', the update control unit 106 needs to be configured to determine the number of cycles executed, and once the number of cycles specified by the cycle number specifying bit 252 is reached, the index pointer is updated to point to the subsequent configuration buffer register; if the number of loops specified by loop number specification bit 252 is reached, the configuration index pointer is updated to point to the loop start address specified by loop start address 253.

Furthermore, the invention also provides a multi-core processor chip, a plurality of processor cores are integrated in the chip, the processor cores are connected by utilizing the dynamically configurable cross switch interconnection structure circuit, and the input and the output of the dynamically configurable cross switch interconnection structure circuit are respectively connected with the processor cores to realize data transmission among the processor cores.

Furthermore, the invention also provides a system-on-chip, wherein the system-on-chip is integrated with a CPU, a DSP and a plurality of different IP cores, the dynamically configurable cross switch interconnection structure circuit is used for connecting the plurality of IP cores, and at the moment, the input and the output of the dynamically configurable cross switch interconnection structure circuit are respectively connected with the IP cores, so that inter-core data transmission is realized.

Compared with the prior art, the invention has the advantages that:

(1) The cross switch interconnection structure is designed with a configuration buffer unit, a configuration index pointer and a configuration update control unit, wherein the configuration update control unit can analyze input data of the configuration buffer unit, the analyzed result is given to the index pointer, and the output of the configuration buffer unit is changed through the index pointer, so that the transmission path between the input and the output of the cross switch is changed. A closed loop for control can be formed among the configuration buffer unit, the configuration index pointer and the configuration update control unit, so that the aim of automatic control is fulfilled, and external intervention is not needed any more; in addition, the configuration index pointer can be continuously changed in a single period, so that the dynamic change of a transmission path can be realized, and the purposes of flexible and efficient data transmission are achieved.

(2) In order to reduce the capacity of the configuration buffer unit, the configuration data format defines the cyclic configuration field, so that the data in the configuration buffer can be recycled in a certain range, the capacity of the configuration buffer unit is reduced, and the area and the power consumption of the interconnection structure can be directly reduced.

(3) The cross switch interconnection structure designs a strong time sequence valid bit in each output selection configuration field, when the bit is '1', only after the input data appointed by the multi-path selection bit of the output selection configuration field is valid and transmitted to be output, the configuration buffer unit is updated, otherwise, the configuration buffer unit is in a state of waiting for appointed input data, through the design, the input data can be output according to a certain sequence, the front-back relation of the data is adjusted, and the processing work of the data in later period is simplified.

(4) In the cross switch interconnection structure, a forced invalid bit is designed for each output selection configuration field, when the bit is '1', input data appointed by a multi-path selection bit of the output selection configuration field is lost, and the output becomes all '0', so that the output data can be sorted according to a certain rule, some data are removed, and the processing work of the data in the later period is simplified.

Drawings

FIG. 1 is a schematic circuit diagram of a crossbar interconnect structure of the present invention;

fig. 2 is a block diagram of a configuration buffer unit.

Detailed Description

The invention aims to design a cross switch interconnection structure suitable for a multi-core processor chip, so that the cross switch interconnection structure achieves the following three purposes:

(1) The cross switch interconnection structure can automatically switch the transmission path, and the transmission path can be switched without intervention of an external control signal required by the traditional cross switch interconnection;

(2) The cross switch interconnection structure can dynamically switch the transmission path, and can change the transmission path in a single clock period instead of the static state of the traditional cross switch interconnection;

(3) The cross switch interconnection structure can aggregate and multiplex input data, wherein aggregation refers to aggregation of data of different input ports to one output port, sequential output is designated, and multiplexing refers to dispersion of data of one input port to a plurality of output ports; rather than the data of one input port of a conventional crossbar interconnect corresponds to one output port;

(4) The cross switch interconnection structure can sort the input data, and select the input data according to a certain rule, for example, every four input data are divided into a group, the cross switch interconnection structure can normally output the first three data, but the fourth data is subjected to invalid data processing, which is a function which is not possessed by the traditional cross switch interconnection;

through the design of the functions, the cross switch interconnection structure can be more flexible and efficient in data transmission.

According to the cross switch interconnection structure, an input buffer unit, an input control unit, a configuration buffer unit, a configuration update control unit and an index pointer are added on the basis of traditional cross switch interconnection.

Fig. 1 is a schematic circuit diagram of a crossbar interconnect structure according to the present invention. The circuit comprises: a first input buffer unit 101, a second input buffer unit 102, a third input buffer unit 103, a crossbar matrix 100, an input control unit 104, a configuration buffer unit 105, a configuration update control unit 106, and an index pointer 107. The input buffer unit 101 is implemented by a FIFO (first in first out) unit, and has an input connected to the input data 108 and an output connected to the input control unit 104.

The input buffer unit 102 is implemented as a FIFO (first in first out) unit, and has an input connected to the input data 109 and an output connected to the input control unit 104.

The input buffer unit 103 is implemented by a FIFO (first in first out) unit, and has an input connected to the input data 110 and an output connected to the input control unit 104.

The input control unit 104 is a combinational logic unit, and is responsible for analyzing the configuration information input by the configuration buffer unit 105, and under the guidance of the analysis result, reads in the data input by the configuration buffers denoted by 101, 102, and 103 and outputs the data. The input of the input control unit is connected to the configuration buffers denoted 101, 102, 103 respectively, the output is 3 data lines in total, all connected to the crossbar matrix 100, wherein the data denoted 121 is controlled to be read from the configuration buffer 101, the data denoted 122 is controlled to be read from the configuration buffer 102, and the data denoted 123 is controlled to be read from the configuration buffer 103.

The configuration buffer unit 105 is a register group, and can output configuration data of a position register corresponding to the index pointer under the action of the index pointer 107, where the configuration data includes switch control information of a crossbar, selection information of input data, arrangement information of output data, and index pointer change rule information. The configuration buffer unit inputs index pointer 107, and outputs are respectively connected to input control unit 104, configuration update control unit 106, and crossbar 100.

The configuration update control unit 106 is a timing logic unit, and is responsible for analyzing the configuration data input by the configuration buffer unit 105, and outputting the analysis result to the configuration index pointer. In the analysis process, firstly judging whether the configuration data is valid or not; judging whether the configuration index pointer needs to be cleared, and if so, outputting zero to the configuration index pointer; and finally judging whether to execute the cyclic configuration according to the configuration data, if the cyclic configuration is executed, recording the number of times of the cyclic configuration, comparing the number of times with the number of times of the cyclic configuration appointed in the configuration data, outputting the next address of the configuration information to the configuration index pointer, and if the next address of the configuration information is not equal, outputting the configuration initial index address contained in the configuration data to the configuration index pointer. The configuration update control unit has an input connected to the configuration buffer unit 105 and an output connected to the configuration index pointer 107.

The configuration index pointer 107 is a register that registers address information of configuration data to be read out from the configuration buffer unit in the next clock cycle. The configuration index pointer has an input connected to the configuration update control unit 106 and an output connected to the configuration buffer unit 105 via a data line 120.

The data line numbered 120 connects the configuration index pointer 107 register and the configuration buffer unit 105, respectively.

The crossbar 100 is a conventional crossbar interconnect structure, and is implemented by using a multiplexer, where when data from an input port is to be transferred to an output port, a control signal of the multiplexer is required to control path gating, and inputs of the crossbar are respectively connected to data lines 121, 122, and 123 output from the input control unit, and the configuration buffer unit 105, and output data respectively referenced 111 to 113.

Data lines 121, 122, 123 are connected to the input control unit 104 and the crossbar 100, respectively.

Fig. 2 is a block diagram of a configuration buffer unit, which includes a configuration buffer register set, a configuration register, input index pointer data, and output configuration data. The configuration buffer register group is numbered 205, the configuration register is numbered 200, the index pointer data line is numbered 120, and the output configuration data line is numbered 206.

The configuration buffer register group is composed of a plurality of configuration buffer registers such as a configuration buffer register 0, a configuration buffer register 1, a configuration buffer register 2 and the like, wherein:

a configuration buffer register numbered 201, configuration buffer register 0;

a configuration buffer register denoted 202, configuration buffer register 1;

a configuration buffer register denoted by reference numeral 203, which is configuration buffer register 2;

a configuration buffer register numbered 204, which is a configuration buffer register n (n is an integer greater than 3);

the configuration buffer register group 205 is composed of configuration buffer registers denoted by reference numerals 201 to 204, and an index pointer data line denoted by reference numeral 120 is configured as address information input, and data of a corresponding address in the configuration buffer register group is selected and written into the configuration register 200. The configuration buffer register set has an input of a configuration index pointer data line, numbered 120, and an output coupled to configuration register 200.

The configuration register 200 has an input connected to the configuration buffer register group 205, and data information in the register as configuration data output 206, which is connected to the input control unit 104, the configuration update control unit 106, and the crossbar 100, respectively.

In the configuration register and the configuration buffer register, the same configuration data format is provided, including configuration valid bit 210, configuration reset valid bit 211, loop configuration field numbered 250, output 1 selection configuration field numbered 220, output 2 selection configuration field numbered 230, and output 3 selection configuration field numbered 240. Output 1 select configuration field defines the output data line transfer rule numbered 111, output 2 select configuration field defines the output data line transfer rule numbered 112, and output 3 select configuration field defines the output data line transfer rule numbered 113.

Configuration valid bit 210 indicates that the configuration data in this register is valid only if this bit is '1'.

A configuration reset valid bit 211, when this bit is '1', indicates that the configuration data in this register is the last valid configuration data, and the data in the later configuration cache register is invalid; when this bit is '0', it indicates that the configuration data in this register is not the last valid configuration data, and the data in the later configuration buffer registers are valid and should be read out sequentially.

The output 1 select configuration field 220 controls the data and its path of the crossbar matrix output, numbered 111, consisting of an output 1 select configuration valid bit, numbered 222, an output 1 data force invalid bit, numbered 223, an output 1 strong timing valid bit, numbered 224, and an output 1 multiplexing bit.

Output 1 selects configuration valid bit 221, which only indicates that the configuration data in this output 1 select configuration field is valid if this bit is '1'.

Outputting the 1 data force invalid bit 222, when this bit is '1', indicates that the data numbered 111 output by the crossbar matrix needs to be forcedly set to all '0'.

The output 1 is a strong timing valid bit 223, which when it is '1' indicates that the configuration update control unit can update the configuration index pointer only after the output 1 completes one data transfer, and reads the next configuration buffer.

Output 1 multiplexing bit 224 is a binary data of bit width 2 defining the path selection of the crossbar matrix, e.g., if the data is "01", output 1 labeled 111 establishes a transmission path with input labeled 121, and if the data is "10", output 1 labeled 111 establishes a transmission path with input labeled 122.

The output 2 select configuration field 230 controls the data and transfer paths of the crossbar matrix output labeled 112, consisting of output 2 select configuration valid bit labeled 231, output 2 data force invalid bit labeled 232, output 2 strong timing valid bit labeled 233, output 2 multiplexing select bit labeled 234.

Output 2 selects configuration valid bit 231, which only indicates that the configuration data in this output 2 select configuration field is valid if this bit is '1'.

The 2 data force invalid bit 232 is output and when this bit is '1', it is indicated that the data of 112 output by the crossbar matrix needs to be forced to all '0'.

The output 2 strong timing valid bit 233, when this bit is '1', indicates that the configuration update control unit can update the configuration index pointer only after the output 2 completes one data transfer, and reads the next configuration buffer register.

Output 2 multiplexing bit 234 is a binary data of bit width 2 defining the path selection of the crossbar matrix, e.g., if the data is "01", output 2 labeled 112 establishes a transmission path with input labeled 121, and if the data is "10", output 2 labeled 112 establishes a transmission path with input labeled 122.

The output 3 select configuration field 240 controls the data and transfer paths of the crossbar matrix output labeled 113, consisting of an output 3 select configuration valid bit labeled 241, an output 3 data force invalid bit labeled 242, an output 3 strong timing valid bit labeled 243, and an output 3 multiplexing bit labeled 244.

Output 3 selects configuration valid bit 241, only if this bit is '1', indicating that the configuration data in this output 3 select configuration field is valid.

The output 3 data force invalidate bit 242, when this bit is '1', indicates that the data labeled 113 output by the crossbar matrix needs to be forced to all '0'.

The output 3 is a strong timing valid bit 243, and when this bit is '1', it indicates that the configuration update control unit can update the configuration index pointer and read the next configuration buffer register only after the output 3 completes one data transfer.

Output 3 multiplexing bit 244 is a binary data of bit width 2 defining the path selection of the crossbar matrix, e.g., if the data is "01", output 3 labeled 113 establishes a transmission path with input labeled 121, and if the data is "10", output 3 labeled 113 establishes a transmission path with input labeled 122.

The loop configuration field 250 is composed of a loop configuration valid bit, numbered 251, a loop number designation bit, numbered 252, and a loop start address, numbered 253.

A loop configuration valid bit 251, which indicates that the configuration data in the register is to be configured in a loop only when the bit is '1', and the address corresponding to the register is the end address of each loop configuration, and when the bit is '1' in the configuration register, the configuration update control unit 106 is required to determine the number of executed loops, and once the number of loops designated by reference numeral 252 is reached, the configuration index pointer is updated to point to the configuration buffer register; if the number of loops specified at reference numeral 252 is reached, the configuration index pointer is updated to point to the loop start address specified at reference numeral 253.

The cycle number assignment bit 252 is a binary data having a bit width of 4, and defines the number of cycle configurations.

The cycle start address designating bit 253 is a binary data having a bit width of 4, and defines an index start address of each cycle configuration, for example, if the data is "0000", the index start address indicating the cycle configuration is a configuration buffer register denoted by reference numeral 201, and if the data is "0010", the index start address indicating the cycle configuration is a configuration buffer register denoted by reference numeral 203.

The cross switch interconnection structure designed according to the scheme mainly comprises the following embodiments in chip design:

(1) In the multi-core processor, a plurality of processor cores are integrated in a chip, the cross switch interconnection structure is used for connecting the plurality of processor cores, at the moment, the input and the output of the interconnection structure are respectively connected with the processor cores, and the high-throughput rate rapid transmission of data among the cores can be realized. The number of input and output ports at this time is not limited to three, and is cut or expanded according to actual requirements.

(2) In a system-on-a-chip (SoC), a CPU, a DSP and a plurality of different IP cores are integrated in the chip, the cross switch interconnection structure is utilized to connect the plurality of IP cores, at the moment, the input and the output of the interconnection structure are respectively connected with the IP cores, and the high-throughput rate rapid transmission of data between the cores can be realized. The number of input and output ports at this time is not limited to three, and is cut or expanded according to actual requirements.

(3) In the dynamic reconfigurable chip, a plurality of data processing acceleration engines and a plurality of storage modules are integrated in the chip, the cross switch interconnection structure is used for connecting the acceleration engines, the storage modules and other unit modules, and the cross switch interconnection structure is connected into a network, so that the data can be rapidly transferred on the network, among the acceleration engines and in the storage modules at a high throughput rate. By utilizing the characteristic that the transmission path of the cross switch interconnection structure can be dynamically changed, the dynamic reconfiguration of the data path is realized in the dynamic reconfigurable chip, and at the moment, the number of input ports and output ports of the cross switch interconnection structure is generally designed into four and are arranged in an up-down left-right mode.

What is not described in detail in the present invention is a known technology to those skilled in the art.

Claims (12)

1. A dynamically configurable crossbar interconnect structure circuit, comprising: a first input buffer unit (101), a second input buffer unit (102), a third input buffer unit (103), a crossbar matrix (100), an input control unit (104), a configuration buffer unit (105), a configuration update control unit (106) and an index pointer (107);

the first input buffer unit (101), the second input buffer unit (102) and the third input buffer unit (103) are realized by adopting FIFO units, and three paths of input data are buffered respectively;

the input control unit (104) analyzes the configuration data input by the configuration buffer unit (105), reads the data of the three input buffer units under the guidance of the analysis result and outputs the data to the cross switch matrix (100);

the configuration buffer unit (105) outputs the configuration data of the position register corresponding to the index pointer to the cross switch matrix (100), the input control unit (104) and the configuration update control unit (106) under the action of the index pointer (107);

the configuration updating control unit (106) analyzes the configuration data output by the configuration caching unit (105), and the analysis result updates the index pointer (107);

the index pointer (107) registers address information of configuration data to be read out from the configuration buffer unit in the next clock cycle;

the crossbar (100) performs multiplexing on input data under the control of configuration data output by the configuration buffer unit (105), and controls path gating and output.

2. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 1, wherein: the first input buffer unit (101), the second input buffer unit (102) and the third input buffer unit (103) are realized by adopting FIFO units; the input control unit (104) and the cross switch matrix (100) are combined logic units, wherein the cross switch matrix (100) is realized by adopting a multiplexer; the configuration buffer unit (105) is a register group, and the index pointer (107) is a register; the configuration update control unit (106) is a sequential logic unit.

3. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 1, wherein: the configuration data of the position register corresponding to the index pointer comprises switch control information of a cross switch matrix, selection information of input data, arrangement information of output data and index pointer change rule information.

4. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 1, wherein: the configuration update control unit (106) analyzes the configuration data output by the configuration buffer unit (105), and the analysis result updates the index pointer (107), specifically:

(1) In the analysis process, firstly judging whether the configuration data is valid or not, if so, entering the step (2), otherwise, suspending the analysis process and waiting for the configuration data to be valid;

(2) Judging whether the index pointer needs to be cleared, if so, outputting zero by the index pointer, and then entering the step (3); if zero clearing is not needed, directly outputting index pointer data;

(3) Judging whether to execute the cyclic configuration according to the configuration data, if the cyclic configuration is executed, recording the number of times of the cyclic configuration, comparing the number of times with the number of times of the cyclic configuration designated in the configuration data, and outputting the next address of the configuration information to an index pointer if the number of times of the cyclic configuration is equal to the number of times of the cyclic configuration designated in the configuration data; if not, outputting a configuration initial index address contained in the configuration data to an index pointer; if loop configuration is not performed, the next address of the configuration information is directly output to the index pointer.

5. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 1, wherein: and a control closed loop is formed among the configuration buffer unit (105), the index pointer (107) and the configuration update control unit (106) so as to realize automatic control.

6. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 1, wherein: the configuration buffer unit (105) comprises a configuration buffer register group (205) and a configuration register (200);

the configuration buffer register group (205) comprises a plurality of configuration buffer registers, the configuration buffer register group (205) receives the output of the index pointer as address information input, selects data of a corresponding address in the configuration buffer register group, and writes the data into the configuration register (200);

the data information in the configuration register (200) is outputted as configuration data.

7. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 6, wherein: in the configuration register (200) and the configuration buffer register group (205), the configuration data format is the same, and the configuration data format comprises configuration valid bits (210), configuration reset valid bits (211), a loop configuration field (250), an output 1 selection configuration field (220), an output 2 selection configuration field (230) and an output 3 selection configuration field (240);

the output 1 selection configuration field, the output 2 selection configuration field and the output 3 selection configuration field define three paths of output data line transmission rules of the cross switch matrix;

a configuration valid bit (210) indicating that the configuration data in the register is valid only if the bit is '1';

configuring a reset valid bit (211), when the bit is '1', indicating that the configuration data in the register is the last valid configuration data, and the data in the later configuration buffer register is invalid; when this bit is '0', it indicates that the configuration data in this register is not the last valid configuration data, and the data in the later configuration buffer register is valid.

8. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 7, wherein: an output 1 selection configuration field (220) controls the first path data and the transmission path of the first path data output by the cross switch matrix, and comprises an output 1 selection configuration valid bit (221), an output 1 data forced invalid bit (222), an output 1 strong time sequence valid bit (223) and an output 1 multi-path selection bit (224);

an output 1 select configuration valid bit (221), only if the bit is '1', indicating that the configuration data in the output 1 select configuration field is valid;

an output 1 data force invalid bit (222) which, when it is '1', indicates that the first way of data output by the crossbar matrix needs to be forced to all '0'.

An output 1 strong timing valid bit (223), when this bit is '1', indicating that the configuration update control unit can update the configuration index pointer only after the output 1 completes one data transfer, and reads the next configuration buffer register;

the output 1 multiplexing bit (224), which is a binary data of bit width 2, defines the routing of the crossbar matrix.

9. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 7, wherein: an output 2 selection configuration field (230) controls a second path of data and a transfer path of the crossbar matrix output, including an output 2 selection configuration valid bit (231), an output 2 data forced invalid bit (232), an output 2 strong timing valid bit (233), and an output 2 multiplexing selection bit (234);

output 2 selects the configuration valid bit (231), only if the bit is '1', indicating that the configuration data in the output 2 select configuration field is valid; outputting a 2 data forced invalid bit (232) indicating that the second path of data output by the crossbar matrix needs to be forcedly set to all '0' when the bit is '1'; outputting a 2 strong timing valid bit (233), when the bit is '1', indicating that the configuration update control unit can update the configuration index pointer only after the output 2 completes one data transfer, and reading the next configuration buffer register; output 2 multiplexing bits (234), which are binary data of bit width 2, defining the path selection of the crossbar matrix;

an output 3 select configuration field (240) controls a third path of data and a transfer path of the crossbar matrix output, including an output 3 select configuration valid bit (241), an output 3 data forced invalid bit (242), an output 3 strong timing valid bit (243), and an output 3 multiplexing select bit (244);

output 3 selects the configuration valid bit, only if this bit is '1', indicating that this output 3 selects the configuration data in the configuration field to be valid; outputting 3 a data forced invalid bit, wherein when the bit is '1', the third path of data output by the cross switch matrix is required to be forcedly set to be all '0'; outputting 3 strong time sequence valid bit, when the bit is '1', the configuration updating control unit can update the configuration index pointer only after the output 3 completes one data transmission, and reading the next configuration buffer register; the output 3 multiple select bits, which are binary data of bit width 2, define the path selection of the crossbar matrix.

10. A dynamically configurable crossbar interconnect structure circuit in accordance with claim 7, wherein: the loop configuration field (250) includes a loop configuration valid bit (251), a loop number assignment bit (252), and a loop start address (253);

a loop configuration valid bit (251) which indicates that the configuration data in the register is required to be configured in a loop only when the bit is '1', and the address corresponding to the register is the end address of each loop configuration; when the bit in the configuration register is '1', the configuration update control unit (106) is required to judge the executed cycle number, and once the cycle number appointed by the cycle number appointed bit (252) is reached, the index pointer is updated to lead the index pointer to point to the subsequent configuration cache register; if the number of loops specified by the loop number specifying bit (252) is reached, the configuration index pointer is updated to point to the loop start address specified by the loop start address (253).

11. A multi-core processor chip, characterized by: the chip is integrated with a plurality of processor cores, the plurality of processor cores are connected by the dynamically configurable cross switch interconnection structure circuit as claimed in any one of claims 1 to 10, and the input and the output of the dynamically configurable cross switch interconnection structure circuit are respectively connected with the processor cores to realize data transmission among the processor cores.

12. A system-on-chip, characterized by: integrating CPU, DSP and a plurality of different IP cores in a system-on-chip, connecting the plurality of IP cores by using the dynamically configurable cross switch interconnection structure circuit according to any one of claims 1-10, wherein the input and the output of the dynamically configurable cross switch interconnection structure circuit are respectively connected with the IP cores, so as to realize inter-core data transfer.