CN117234965A

CN117234965A - Memory management method and device, electronic equipment and storage medium

Info

Publication number: CN117234965A
Application number: CN202310920096.2A
Authority: CN
Inventors: 刘阳
Original assignee: Spreadtrum Communications Tianjin Co Ltd
Current assignee: Spreadtrum Communications Tianjin Co Ltd
Priority date: 2023-07-25
Filing date: 2023-07-25
Publication date: 2023-12-15

Abstract

The embodiment of the application provides a memory management method, a memory management device, electronic equipment and a storage medium, wherein a storage address interval is added between each image pixel block during caching, so that an output new cache image directly covers an old cache image, and the occupation of the memory space of the equipment is saved. The memory management method comprises the following steps: calculating a first byte size corresponding to the input first cache image and a second byte size corresponding to the output second cache image; calculating a first byte maximum between a first pixel block of the first cached image and a second pixel block of the second cached image; taking the maximum value of the first byte as a first interval of storage first addresses of two adjacent first pixel blocks, and writing the first pixel blocks into a readable and writable memory one by one based on the first interval; the first pixel blocks are read and processed one by one, and the corresponding second pixel blocks are written one by one based on the storage head address of each first pixel block.

Description

Memory management method and device, electronic equipment and storage medium

[ field of technology ]

The embodiment of the application relates to the technical field of terminals, in particular to a memory management method, a memory management device, electronic equipment and a storage medium.

[ background Art ]

In the process of processing an image or video by a terminal device, it is often required to buffer the image or video into an allocated address in a device memory, then process the buffered image or video data by using a specific process, and after the processing is completed, write an output new image or new video into a new address additionally allocated in the memory. And (3) until the processing operation of the specific process on the image or the video is completed, clearing the buffer image of the old image or the old video for input, and simultaneously writing the output new image or the buffer image of the new video into the storage disk of the device from the memory.

When this memory management strategy is used to process a large-sized or large-sized image or video, the old cache image for input and the new cache image for output are easily stored in the device memory together, so that the limited memory space is fully occupied, and the memory space is insufficient.

[ application ]

The embodiment of the application provides a memory management method, a memory management device, electronic equipment and a storage medium, wherein when an image is cached in the memory of the equipment, a proper storage address interval is added between pixel blocks of each image, so that an output new cache image can timely cover an old cache image which is not required to be read any more, the integral reading of the old cache image is not influenced, and the occupation of the memory space of the equipment is effectively saved.

In a first aspect, an embodiment of the present application provides a memory management method, applied to a terminal side, where a readable and writable memory exists, the method includes:

calculating a first byte size corresponding to the input first cache image and a second byte size corresponding to the output second cache image;

calculating a first byte maximum between a first pixel block of the first cached image and a second pixel block of the second cached image according to the first byte size and the second byte size, wherein the first pixel block is used for generating the second pixel block;

taking the maximum value of the first byte as a first interval of storage first addresses of two adjacent first pixel blocks, and taking a set base address as a starting point, and writing the first pixel blocks into the readable and writable memory one by one based on the first interval;

and reading and processing the first pixel blocks one by taking the set base address as a starting point, and writing the corresponding second pixel blocks one by one based on the storage head address of each first pixel block until the writing of the second cache image is completed.

In the embodiment of the application, the first buffer image and the second buffer image share one memory space by setting the storage head address interval between every two adjacent first pixel blocks before writing the first buffer image and directly using the second pixel block to cover the read first pixel block after writing the first pixel block without influencing the reading action of the next first pixel block, thereby achieving the effect of saving the memory more than the strategy of separately storing the new buffer image and the old buffer image in the traditional image processing strategy.

Optionally, the calculating a first byte maximum between the first pixel block of the first buffered image and the second pixel block of the second buffered image according to the first byte size and the second byte size includes:

responding to the first pixel block containing a first pixel, the second pixel block containing a second pixel, and calculating a first maximum value between bytes occupied by the first pixel and bytes occupied by the second pixel according to the first byte size and the second byte size;

determining the first maximum value as the first byte maximum value; or,

responsive to the first pixel block including a plurality of first pixels, the second pixel block including a single second pixel, calculating a second maximum between a sum of bytes occupied by the plurality of first pixels and bytes occupied by the single second pixel according to the first byte size and the second byte size;

determining the second maximum value as the first byte maximum value; or,

in response to the first pixel block including a single first pixel, the second pixel block including a plurality of second pixels, calculating a third maximum between a byte occupied by the single first pixel and a sum of bytes occupied by the plurality of second pixels according to the first byte size and the second byte size;

The third maximum value is determined to be the first byte maximum value.

In the embodiment of the application, by judging whether the generation relation between the pixels in the first pixel block and the pixels in the second pixel block is one-to-one, one-to-many or many-to-one and adopting different storage head address interval setting strategies according to different generation relations, the writing position of the second pixel block just can meet the condition of covering or partially covering the corresponding first pixel block and the reading condition of the next first pixel block is not influenced, and the flexibility of memory occupation optimization in image processing is enhanced.

Optionally, after the calculating, the method further includes:

calculating a fourth byte size corresponding to the first pixel block and a third byte size expected to be occupied by a difference pixel block generated by the first pixel block and the second pixel block through difference processing according to the first byte size and the second byte size;

taking the sum of the fourth byte size and the corresponding third byte size as a second interval of storage head addresses of two adjacent first pixel blocks;

Writing the first pixel blocks into the readable and writable memory one by one based on the second interval by taking the set base address as a starting point;

reading and processing the first pixel blocks one by one with the set base address as a starting point, and calculating the corresponding difference pixel blocks based on the current first pixel block and the second pixel block in response to the corresponding second pixel block output;

and writing the corresponding difference pixel blocks one by one based on the storage end address of each first pixel block until the difference pixel blocks are completely written.

In the embodiment of the application, the direct storage of the second pixel block is changed into the calculation of the pixel value difference value of the second pixel block and the first pixel block in the form of the difference pixel block, and the difference pixel block is stored in the pixel data of the first pixel block, so that the characteristic that the byte occupation of the difference pixel block is generally far smaller than the pixel data per se is utilized to effectively compress the image data volume, and the memory space distributed to the first cache image and the second cache image is saved.

Optionally, the writing the corresponding difference pixel blocks one by one based on the storage end address of each first pixel block until the writing of the difference pixel blocks is completed, and the method further includes:

Reading each difference pixel block in turn;

storing each difference pixel block into a memory at the terminal side respectively until all the difference pixel blocks are stored; or,

sequentially reading each first pixel block and the corresponding difference pixel block;

and calculating the corresponding second pixel blocks based on each first pixel block and the corresponding difference pixel block, and storing the calculated second pixel blocks into the memory until all the second pixel blocks are calculated and stored.

In the embodiment of the application, by respectively providing two strategies of directly storing the difference pixel block into the memory, generating the second cache image according to the difference pixel block and the first cache image and storing the second cache image into the memory, the memory can be saved, and meanwhile, a proper image data storage scheme can be selected according to the user requirement, so that the universality of the scheme for generating the difference pixel block pixel by pixel is enhanced.

Optionally, the first buffer image and the second buffer image are both video buffer data, and after calculating a first byte size corresponding to the first buffer image as input and a second byte size corresponding to the second buffer image as output, the method further includes:

According to the first byte size and the second byte size, byte maximum values between each first frame set in the first cache image and a corresponding second frame set in the second cache image are calculated in sequence to obtain a plurality of second byte maximum values, and the first frame sets are used for generating the second frame sets;

setting storage head address intervals of two adjacent first frame sets according to the maximum value of each second byte in sequence to obtain a plurality of third intervals;

based on each third interval, the corresponding first frame set is written into the readable and writable memory one by taking the set base address as a starting point;

and reading and processing the first frame sets one by taking the set base address as a starting point, and writing the corresponding second frame sets one by one based on the storage head address of each first frame set until the writing of the second cache image is completed.

In the embodiment of the application, when the image data is video data, the strategy of setting the head address interval by pixel blocks is changed into setting the storage head address interval by frame sets, so that the calculated amount of writing operation when the head address interval is set by pixel blocks can be effectively reduced, the read first frame set can be timely covered by the newly generated second frame set, and the memory saving effect same as that of the head address interval set by pixel blocks can be realized.

Optionally, after calculating the first byte maximum value between the first pixel block of the first cached image and the second pixel block of the second cached image according to the first byte size and the second byte size, the method further includes:

based on the set base address, a plurality of cache partitions are distributed in the readable and writable memory, the sum of the sizes of the cache partitions is at least the maximum value between the first byte size and the second byte size, and the size of each cache partition is an integer multiple of the maximum value of the first byte;

establishing a mapping relation between the plurality of cache partitions and the first pixel block in the first cache image;

the writing the first pixel blocks into the readable and writable memory one by one based on a first interval with the first byte maximum value as a first interval of storage head addresses of two adjacent first pixel blocks and a set base address as a starting point includes:

taking the first byte maximum value as the first interval;

based on the first interval, writing the first pixel blocks into the corresponding cache partitions in the readable and writable memory one by one according to the mapping relation between the first pixel blocks and the cache partitions;

The step of reading and processing the first pixel blocks one by one with the set base address as a starting point, and writing the corresponding second pixel blocks one by one based on the storage head address of each first pixel block until the writing of the second cache image is completed comprises the following steps:

reading and processing the first pixel blocks in the corresponding cache partition one by one according to the storage head address of the first pixel blocks by taking the set base address as a starting point;

and writing the second pixel blocks into the cache partitions corresponding to the first pixel blocks one by one based on the storage head address of each first pixel block until the second cache image writing is completed.

In the embodiment of the application, the first pixel blocks are respectively stored by defining a plurality of cache partitions, so that when the first pixel blocks are required to be stored in a blocking way, enough storage first address intervals are reserved between two adjacent first pixel blocks, the writing condition of a subsequent second cache image is met, and the second pixel blocks can be normally stored in the cache partitions in a mode of covering the first pixel blocks; and the first cache image can be completely stored in different cache partitions, so that pixel data overflow and data fragmentation are avoided, and the locality characteristics of the memory are better utilized.

In a second aspect, an embodiment of the present application further provides a memory management device, provided at a terminal side, where a readable and writable memory exists, the device includes:

a calculation unit for calculating a first byte size corresponding to the first buffered image as input and a second byte size corresponding to the second buffered image as output;

the computing unit is further configured to compute a first byte maximum value between a first pixel block of the first cached image and a second pixel block of the second cached image according to the first byte size and the second byte size, where the first pixel block is used to generate the second pixel block;

the memory read-write unit is used for taking the maximum value of the first byte as a first interval of storage head addresses of two adjacent first pixel blocks, taking a set base address as a starting point, and writing the first pixel blocks into the readable-writable memory one by one based on the first interval;

the memory read-write unit is further configured to read and process the first pixel blocks one by one with the set base address as a starting point, and write the corresponding second pixel blocks one by one based on a storage first address of each first pixel block until the writing of the second cache image is completed.

Optionally, the computing unit is specifically configured to:

determining the first maximum value as the first byte maximum value; or,

determining the second maximum value as the first byte maximum value; or,

the third maximum value is determined to be the first byte maximum value.

Optionally, the apparatus further includes:

the calculating unit is further configured to calculate a fourth byte size corresponding to the first pixel block and a third byte size that is expected to be occupied by a difference pixel block generated by the difference processing of the first pixel block and the second pixel block according to the first byte size and the second byte size;

a first address interval setting unit, configured to use a sum of the fourth byte size and the corresponding third byte size as a second interval of storing first addresses of two adjacent first pixel blocks;

the memory read-write unit is further configured to write the first pixel blocks into the readable-writable memory one by one based on the second interval with the set base address as a starting point;

the memory read-write unit is further configured to read and process the first pixel blocks one by one with the set base address as a starting point, and calculate the corresponding difference pixel blocks based on the current first pixel block and the second pixel block in response to the corresponding second pixel block output;

the memory read-write unit is further configured to write the corresponding difference pixel blocks one by one based on the storage end address of each first pixel block until all writing of the difference pixel blocks is completed.

Optionally, the apparatus further includes:

a reading unit for sequentially reading each of the difference pixel blocks;

the storage unit is used for storing each difference pixel block into the memory at the terminal side respectively until all the difference pixel blocks are stored; or,

the reading unit is further configured to sequentially read each first pixel block and the corresponding difference pixel block;

the storage unit is further configured to calculate a corresponding second pixel block based on each of the first pixel blocks and the corresponding difference pixel block, and store the calculated second pixel block into the memory until all the second pixel blocks are calculated and stored.

Optionally, the first buffered image and the second buffered image are both video buffered data, and the calculating unit is further configured to sequentially calculate byte maxima between each first frame set in the first buffered image and a corresponding second frame set in the second buffered image according to the first byte size and the second byte size, to obtain a plurality of second byte maxima, where the first frame set is used to generate the second frame set;

The first address interval setting unit is further configured to set storage first address intervals of two adjacent first frame sets according to each maximum value of the second byte in sequence, so as to obtain a plurality of third intervals;

the memory read-write unit is further configured to write the corresponding first frame set into the readable-writable memory one by one based on each third interval with a set base address as a starting point;

the memory read-write unit is further configured to read and process the first frame sets one by one with the set base address as a starting point, and write the corresponding second frame sets one by one based on a storage first address of each first frame set until the writing of the second buffer image is completed.

Optionally, the apparatus further includes:

a cache partition establishing unit, configured to allocate a plurality of cache partitions in the readable and writable memory based on the set base address, where a sum of sizes of the plurality of cache partitions is at least a maximum value between the first byte size and the second byte size, and a size of each cache partition is an integer multiple of the maximum value of the first byte;

the pixel mapping unit establishes a mapping relation between the plurality of cache partitions and the first pixel block in the first cache image;

The memory read-write unit is specifically configured to:

taking the first byte maximum value as the first interval;

In a third aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes at least one processor and a memory connected to the at least one processor, where the at least one processor is configured to implement the steps of the method according to any one of the first aspects when executing a computer program stored in the memory.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method according to any of the first aspects.

It should be understood that, the second to fourth aspects of the embodiments of the present application are similar to the technical solutions of the first aspect of the embodiments of the present application, and the beneficial effects obtained by each aspect and the corresponding possible implementation manner are not repeated.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a memory management method according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating a method for determining a storage head address interval according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating another method for determining a storage head address interval according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating another method for determining a storage head address interval according to an embodiment of the present application;

FIGS. 5 (a) -5 (b) are schematic diagrams illustrating a memory read/write effect when setting a storage head address interval based on a first byte maximum value according to an embodiment of the present application;

Fig. 6 is a flow chart of a memory management method based on a differential image according to an embodiment of the present application;

FIG. 7 is a schematic diagram showing the effect of a method for storing a second buffered image based on a difference pixel block according to an embodiment of the present application;

fig. 8 is a schematic flow chart of a second buffered image writing method based on a difference pixel block according to an embodiment of the present application;

fig. 9 is a flowchart of another method for writing a second buffered image based on a difference pixel block according to an embodiment of the present application;

fig. 10 is a flowchart of a memory management method for video cache data according to an embodiment of the present application;

FIG. 11 is a flow chart of a memory management method based on multiple cache partitions according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a memory management device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

[ detailed description ] of the application

For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present disclosure.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

At present, in the process of processing an image or video by a terminal device, it is often required to buffer the image or video to an allocated address in a device memory, then process the buffered image or video data by using a specific process, and after the processing is completed, write an output new image or new video to a new address additionally allocated in the memory. And (3) until the processing operation of the specific process on the image or the video is completed, clearing the buffer image of the old image or the old video for input, and simultaneously writing the output new image or the buffer image of the new video into the storage disk of the device from the memory.

When the memory management strategy is used for processing images and videos with larger volume or more volume, the old cache images for input and the new cache images for output are stored in the memory of the device together, so that the limited memory space is fully occupied, and the memory space is insufficient.

In view of this, the embodiment of the present application provides a memory management method, according to the byte size of the new cache image as output and the byte size of the old cache image as input, adding a proper storage address interval between every two pixel blocks of the old cache image when the old cache image is written into the memory, so that the new cache image as output can timely cover the old cache image which has been read, and meanwhile, the whole reading of the old cache image is not affected, and occupation of the memory space of the device is effectively saved.

It should be understood that, in the embodiment of the present application, the image file to be processed, the first cached image, the second cached image and the processed image file may be picture or video data stored in units of pixels in an unlimited format, or may be a moving picture stored in a graphics exchange format or any other format. The first cache image is in the form of cache data after the image file to be processed in the terminal side memory is written into the readable and writable memory, the second cache image is in the form of cache image stored in the readable and writable memory after image processing, and the processed image file is in the form of image file after the second cache image is written into the terminal side memory.

In addition, the "first pixel block" and the "second pixel block" in the embodiments of the present application may be regarded as the minimum unit in one image processing flow, where the first pixel block is the minimum unit in the first buffered image as input, the second pixel block is the minimum unit in the second buffered image as output, one or more first pixel blocks exist in the first buffered image, and one or more second pixel blocks exist in the second buffered image. For example, when the first buffered image is obtained by interpolation and amplification calculation, there is a one-to-many relationship between the pixels of the first buffered image and the pixels of the second buffered image, so that the first pixel block needs to include one pixel, and the second pixel block needs to include a plurality of corresponding pixels. Similar situations are numerous and will not be described in detail here.

The following describes the scheme provided by the embodiment of the application with reference to the attached drawings.

Referring to fig. 1, a memory management method according to an embodiment of the present application is applied to a terminal side, and the terminal side includes, but is not limited to: desktop computers, notebook computers, palm top computers, cell phones, tablet computers, smart watches, smart glasses, smart speakers, or other portable devices that support media transfer protocols. The method comprises the following steps:

Step 101: a first byte size corresponding to the first buffered image as input and a second byte size corresponding to the second buffered image as output are calculated.

In the embodiment of the application, the first byte size is generally obtained by reading an image file to be processed corresponding to the first cache image in a memory at the terminal side; the second byte size is generally based on the first byte size, and the processed image volume is estimated according to the specific processing flow and the first byte size by acquiring the specific processing flow of the image. Because the specific processing flow of the image is in a known state after the user designates a certain image for processing, the numerical values of the first byte size and the second byte size are also easy to obtain, and the calculation process is not repeated.

Step 102: and calculating a first byte maximum value between a first pixel block of the first cache image and a second pixel block of the second cache image according to the first byte size and the second byte size, wherein the first pixel block is used for generating the second pixel block.

Since in the conventional operation of image processing, the first buffered image is used only for generating the second buffered image after processing, this process is generally completed by a single process, and the single process is released after the processing is completed, the data of the first buffered image is not repeatedly read after being read once. Therefore, after a certain first pixel block is read, a new second pixel block can be used to cover the read first pixel block, so as to achieve the purpose of saving the memory. In order to match with the memory management policy, the first cache image and the second cache image should not be stored in two memory spaces respectively, but share one memory space. Further, when the image file to be processed is written into the readable and writable memory to obtain the first cached image, a reasonable storage head address interval should be set between two adjacent first pixel blocks. For this purpose, it is necessary to calculate the appropriate value corresponding to the storage header address interval, so as to ensure that the second pixel block only covers the first pixel block that has been read, and does not erroneously cover the first pixel block that has not been read, regardless of the size relationship between the first pixel block and the second pixel block. In this regard, in the embodiment of the present application, a first byte maximum value between a first pixel block of a first buffered image and a second pixel block of a second buffered image is used as a reference value for storing a first address interval.

Specifically, when the byte occupation of the first pixel block is greater than or equal to the second pixel block, no matter where the second pixel block starts to be covered from the read first pixel block, as long as the storage first address and the storage last address of the second pixel block do not exceed the range of the section stored by the first pixel block, the second pixel block can be ensured to cover the corresponding read first pixel block, and the normal execution of the strategy of not covering the unread adjacent first pixel block. At this time, the byte size of the first pixel block is the first byte maximum value, and the storage head address interval as two adjacent first pixel blocks does not cause any problem.

When the byte occupation of the first pixel block is smaller than that of the second pixel block, the second pixel block can not cover the adjacent unread first pixel blocks when being written from the storage head address of the first pixel block only by ensuring that the storage head address interval between the two adjacent first pixel blocks is the byte size of the second pixel block. At this time, the byte size corresponding to the second pixel block is the maximum value of the first byte, and the storage head address interval as two adjacent first pixel blocks does not cause any problem.

Therefore, from the above analysis, it is preferable to set the first byte maximum value as the reference value for storing the head address interval.

It should be noted that, in the actual application process, since the first cached image and the second cached image are both obtained from the image file to be processed in the terminal side memory, the pixel number of the image file to be processed can already be obtained through the corresponding image metadata information, and the specific processing flow of the first cached image is also in a known state. Therefore, given the first byte size and the second byte size, it is possible to determine, based on the number of pixels of the image file to be processed and the specific processing flow of the image processing, how many pixels are included in the first pixel block and the second pixel block, and how many byte sizes the two pixel blocks occupy.

After the first pixel block and the second pixel block are obtained and each of the first pixel block and the second pixel block should include several pixels, a storage head address interval between two adjacent first pixel blocks needs to be specifically set according to a pixel correspondence between the first pixel block and the second pixel block.

Fig. 2 is a flowchart of a method for determining a storage head address interval according to an embodiment of the present application. As a possible implementation, step 102 may be implemented by performing sub-steps 1021 through 1022.

Step 1021: and in response to the first pixel block containing the first pixel and the second pixel block containing the second pixel, calculating a first maximum value between the bytes occupied by the first pixel and the bytes occupied by the second pixel according to the first byte size and the second byte size.

Step 1022: the first maximum value is determined as a first byte maximum value.

In the embodiment of the application, the first pixel block and the second pixel block may have a plurality of pixel correspondence according to different specific processing flows of image processing. And among them, one-to-one generation is the most common correspondence. An example of a corresponding one-to-one generation is in a color depth change operation of an image where a first pixel only needs to change color values to obtain a corresponding second pixel.

Under the one-to-one generated corresponding relation, the first byte maximum value used for determining the storage head address interval of the adjacent first pixel block is the byte occupation maximum value between the first pixel and the second pixel.

Fig. 3 is a flowchart of another method for determining a storage head address interval according to an embodiment of the present application. As another possible implementation, step 102 may be implemented by performing sub-steps 1023 to 1024.

Step 1023: in response to the first pixel block including a plurality of first pixels and the second pixel block including a single second pixel, a second maximum value between a sum of bytes occupied by the plurality of first pixels and bytes occupied by the single second pixel is calculated based on the first byte size and the second byte size.

Step 1024: the second maximum is determined to be the first byte maximum.

For the pixel correspondence between the first pixel block and the second pixel block in the embodiment of the present application, there is also a case of one-to-one generation. A common example of this is in image scaling, image pyramid generation operations, where a plurality of first pixels are used to calculate a corresponding second pixel.

Under this many-to-one correspondence, the first byte maximum value used to determine the storage head address interval of the adjacent first pixel block should be the maximum value among the sum of the byte occupancy of the plurality of first pixels and the byte occupancy of the single second pixel.

Fig. 4 is a flowchart of another method for determining a storage head address interval according to an embodiment of the present application. As another possible implementation, step 102 may be implemented by performing sub-steps 1025 to 1026.

Step 1025: in response to the first pixel block including a single first pixel, the second pixel block including a plurality of second pixels, a third maximum between a byte occupied by the single first pixel and a sum of bytes occupied by the plurality of second pixels is calculated based on the first byte size and the second byte size.

Step 1026: the third maximum is determined to be the first byte maximum.

For the pixel correspondence between the first pixel block and the second pixel block in the embodiment of the present application, there is also a one-to-many generation case. A common example of this is that in an interpolation enlargement operation of an image, one first pixel is used to calculate a plurality of corresponding second pixels.

And in such a one-to-many correspondence, the first byte maximum value used to determine the storage head address interval of the adjacent first pixel block should be the maximum value among the sum of the byte occupancy of a single first pixel and the byte occupancy of a plurality of second pixels.

After the first byte maximum value is calculated, a first interval between storage head addresses of two adjacent first pixel blocks is determined based on the first byte maximum value, and the first cache image is written into the readable and writable memory based on the first interval.

Step 103: the first byte maximum value is taken as a first interval of storage first addresses of two adjacent first pixel blocks, the first pixel blocks are written into the readable and writable memory one by one based on the first interval by taking a set base address as a starting point.

In the embodiment of the present application, since the explanation has been made above regarding why the first byte maximum value is used as the reference value for setting the storage head address interval, only the specific mechanism by which the first buffered image is written into the readable and writable memory based on the first byte maximum value, and the difference in buffering effect generated in the readable and writable memory due to the difference in the size relationship between the first pixel block and the second pixel block after the first interval is determined based on the first byte maximum value will be discussed herein.

Firstly, for the situation that the image file to be processed needs to be read and the first cache image needs to be written in the readable and writable memory, a specific writing mechanism of the first cache image is as follows: presetting a fixed first interval according to a first byte maximum value between a first pixel block and a second pixel block; then, when the program at the terminal side starts to read the first pixel block of the first cached image, the dynamic calculation of the storage head address of each pixel block according to the first interval can be synchronously started, and the writing is continued by jumping to the storage head address of the next first pixel block after writing one first pixel block according to the calculated storage head address.

In some embodiments, a first interval is added between the storage head addresses of two adjacent first pixel blocks, and a method of directly writing a blank byte may be used. That is, after the first interval is calculated, it is carried forward to calculate how many additional blank bytes need to be inserted to meet the constraint that "a first interval exists between the storage head addresses of two adjacent first pixel blocks", and corresponding blank bytes are additionally inserted after the first pixel blocks are written according to the calculated value, and then the writing of the next first pixel block is executed. In particular, this blank byte may be a repeated "0x00" (i.e., 0 in decimal) because its corresponding character in the ASCII code is a null character, which is not easily ambiguous in reading the first pixel block. According to the write-in and read-out strategies of the memory, the corresponding content of the blank byte can be correspondingly adjusted, and the adjustment modes are various and are not repeated here.

After the first interval is set based on the first byte maximum value between the first pixel block and the second pixel block, when the first byte maximum value is taken as the storage address interval in the memory management method in the following manner with reference to the accompanying drawings, the memory saving effects generated by the different size relations of the first pixel block and the second pixel block are respectively discussed in a classification manner:

fig. 5 (a) -5 (b) are schematic diagrams illustrating a memory read/write effect when setting a storage head address interval based on a first byte maximum value in an embodiment of the present application. In fig. 5 (a), the first buffered image (1) already exists in the readable and writable memory, and the first buffered image (1) includes a plurality of first pixel blocks, including the first pixel block (2) that has just been read, and the bytes occupied by the second pixel block (3) of the second buffered image to be written are greater than or equal to the first pixel block (2). Since the first interval (4) is set based on the first byte maximum (i.e. the byte occupied by the second pixel block (3)), and the first interval (4) is equal to the byte size of the second pixel block (3) at this time, the second pixel block (3) can just write to and cover the first pixel block (2) without affecting the reading of the next first pixel block.

In fig. 5 (b), the first buffered image (1) is stored in the readable and writable memory, and the first buffered image (6) includes a plurality of first pixel blocks including the first pixel block (5) just read, and the second pixel block (5) to be written occupies less bytes than the first pixel block (6) in the first buffered data (1). Since the first interval (7) is set based on the first byte maximum, i.e. the byte occupied by the first pixel block (6), and the writing of the second pixel block (5) only covers part of the first pixel block (6), the reading of the next first pixel block is not affected.

After the writing of the first cache image is executed, image processing is needed to be executed according to the first cache image, and the output second cache image is written into the memory space occupied by the first cache image in a pixel-by-pixel coverage mode, so that the purpose of saving memory is achieved.

Step 104: and reading and processing the first pixel blocks one by taking the set base address as a starting point, and writing the corresponding second pixel blocks one by one based on the storage head address of each first pixel block until the writing of the second cache image is completed.

In the embodiment of the present application, similar to the write mechanism of the first pixel block, a special mechanism for jumping to read is also required to be set for reading the first pixel block due to the change of the memory management policy. The mechanism needs to skip a specific byte amount after each read, and the specific byte amount needs to be determined according to the specific values of the first interval and the byte size of the first pixel block.

Specifically, firstly, according to the difference value between the first interval and the first pixel block (if the size of the first pixel block is larger than that of the second pixel block, that is, the first pixel block is equal to the first interval, the specific byte amount to be skipped is 0), the specific byte amount to be skipped after the previous first pixel block is read is determined, so that nonsensical bytes outside the data of the first pixel block are ensured not to be read. Then, after the number of bytes corresponding to the complete first pixel block is read, the next first pixel block is read after jumping to one or more bytes equal to the specific number of bytes (when the first pixel block is equal to the first interval, it is considered that no jump is required to be performed), and the next first pixel block is read.

In some embodiments, a reading mechanism corresponding to the blank byte in the foregoing may be set, so that when the first buffered image is read based on the set base address, the value corresponding to the blank byte is directly filtered, and other data unrelated to the blank byte is retained, so that the data of the first pixel block is completely read, and other bytes unrelated to the first buffered image may be filtered.

And after the first pixel block of the first buffered image is read and image processing is performed in the program on the terminal side, the output second pixel block may also be written by a writing mechanism similar to the reading mechanism of the first pixel block in the foregoing. For example, after the second pixel block is read, a fixed amount of jumps is also determined based on the first interval and the byte size corresponding to the second pixel block, and the jump is made to the address to be written by the next second pixel block based on the amount of jumps. Because the writing mechanism of the second pixel block is similar to the reading mechanism of the first pixel block, the description is omitted herein.

In some embodiments, the second cached image is also used to generate a third cached image, or further, the third cached image is also used to generate a fourth cached image, and so on. On this premise, the storage head address interval of the first pixel block needs to be set by determining the maximum value of the bytes occupied by the pixel block based on the first pixel block, the second pixel block, the third pixel block corresponding to the third buffered image, and the like, and taking the maximum value as the first byte maximum value.

In some embodiments, if the first pixel block is required to be repeatedly invoked after the second pixel block is generated, such as for additional processing to generate a third cached image, etc. At this time, it is obviously disadvantageous to directly overlay the data of the first pixel block, so that a more appropriate memory management policy is required to arrange the storage of the first pixel block and the second pixel block.

Fig. 6 is a flow chart of a memory management method based on differential image according to an embodiment of the present application. After performing step 101, steps 105 to 109 may be further performed.

Step 105: and calculating a fourth byte size corresponding to the first pixel block and a third byte size expected to be occupied by the difference pixel blocks generated by the first pixel block and the second pixel block through the difference processing according to the first byte size and the second byte size.

Step 106: the sum of the fourth byte size and the corresponding third byte size is taken as a second interval of the storage head addresses of the adjacent two first pixel blocks.

Step 107: the first pixel blocks are written into the readable and writable memory one by one based on the second interval with the set base address as the starting point.

Step 108: the first pixel blocks are read and processed one by one starting from the set base address, and corresponding difference pixel blocks are calculated based on the current first pixel block and the second pixel block in response to the corresponding second pixel block output.

Step 109: and writing the corresponding difference pixel blocks one by one based on the storage end address of each first pixel block until the whole writing of the difference pixel blocks is completed.

In some image processing flows, the first pixel block, after being read, processed, and generated into the second pixel block, also needs to be repeatedly invoked to generate other data. At this time, the current memory management policy needs to be adjusted, so that the data of the first pixel block is not directly covered by the second pixel block while the memory occupation is saved as much as possible. In this regard, the embodiment of the present application adopts a manner of generating the differential image, so that the second pixel block is compressed into the differential pixel block with fewer occupied bytes, thereby simplifying the volume of the second buffer image and achieving the effect of saving the memory occupation.

First, in the embodiment of the present application, the differential image stores the pixel value of each second pixel in the second pixel block, but the pixel value variation of each second pixel relative to the corresponding first pixel, because the second buffered image is generated based on the first buffered image, and in the image processing, the variation from the first pixel to the second pixel is generally much smaller in value than the pixel value of the second pixel itself, so that the bytes occupied by the differential pixel block are often also smaller in value than the bytes occupied by the pixels of the second pixel. The difference pixel blocks generated based on this method have in most cases a smaller byte occupancy than the second byte size.

It should be noted that the method of generating the differential pixel block is different from the conventional method of generating a differential image based on the difference in pixel values between two pixels. The difference is that in the conventional method, the differential encoding of the differential image is calculated based on one picture, namely, the trend of all the pixels is predicted based on the first pixel of one picture, and the error value obtained by comparing the predicted value with the actual value is used as the differential encoding to generate the differential image smaller than the volume of the picture, so that the volume compression of the single picture is completed.

In the embodiment of the present application, since the second pixel block to be compressed is generated based on the first pixel block, another application mode of the differential image may be adopted: and directly carrying out pixel value difference on the first pixel in the first pixel block and the second pixel in the corresponding second pixel block, so as to obtain a pixel value difference value between the second pixel and the corresponding first pixel, and further obtain a difference pixel block of the second pixel relative to the first pixel. For example, if the first pixel and the second pixel are both gray images with 8-bit color depth and the range of pixel values is [0, 255], the value of the difference pixel block obtained by differencing the first pixel and the second pixel is within [ -255, 255], and the value records the difference value of the first pixel and the second pixel on the pixel value; if the first pixel and the second pixel are color images with 24-bit color depth and have color components with the value ranges of red, green and blue of [0, 255], the difference pixel block obtained by differencing the first pixel, the green and the blue is also a component with the value of the difference pixel block within the range of [ -255, 255], and each component records the specific size difference value of the first pixel and the second pixel on the color component.

In some embodiments, the first pixel and the second pixel have different color depths, and in this case, if the pixel value difference is directly calculated to generate a difference pixel block, pixel information may be lost. Therefore, when calculating the difference pixel block, an additional component may be set for the pixel with lower color depth, such as setting an additional transparency component for the first pixel with 24 bit depth (since the default transparency range is also 0 to 255, the transparency value when the three-channel to four-channel is directly set to 255), so that the second pixel can generate the difference pixel block by differencing from the first pixel without losing information; color quantization techniques may also be used to preserve its most critical color information for pixels with higher color depths, such that its color components are reduced within a tolerable range of information loss, and a difference pixel block is calculated based on the color quantized pixels and the corresponding lower depth pixels. The specific calculation mode can be flexibly adjusted according to the use scene.

It should be understood that, although the first pixels and the second pixels have pixel value differences, the bytes occupied by the pixel values (i.e., the number of bits of the pixel values) are all of a fixed size, and the data corresponding to each first pixel in the first buffered image occupies the same byte, and each second pixel in the second buffered image is the same. Therefore, the difference pixel blocks obtained by performing the difference on the basis should also have the same byte occupation (if the byte occupation is different, the byte occupation can be directly stored without any processing, or the difference pixel blocks of different pixels can have the same byte occupation by filling the empty space in a mode of appropriately supplementing 0 in front of the difference pixel blocks, such as a mode of '9' → '09').

In the memory management strategy based on the difference pixel blocks, since the first pixel block writing mechanism of writing and skipping is established in the foregoing, the principle of the first pixel block writing mechanism does not change after the difference pixel blocks are adopted to replace the second pixel blocks for writing. Therefore, the sum of the fourth byte size corresponding to the first pixel block and the third byte size corresponding to the differential pixel block (since the first byte size, the second byte size and the pixel number of the image to be processed are known, the third byte size and the fourth byte size are obviously easy to calculate) is determined as the second interval of the storage head addresses of two adjacent first pixel blocks, and the corresponding specific byte amount is calculated based on the second interval, so that the jump of the specific byte amount is normally executed when the first pixel block is written, and the requirement that the first pixel block and the differential pixel block are written into the readable and writable memory together in the subsequent image processing process can be met, and meanwhile, the first pixel block cannot be covered.

After the first cache image is written, the processing can be performed based on the first cache image and a differential image corresponding to the second cache image can be generated so as to execute a memory management strategy based on the differential pixel block.

In the embodiment of the application, when the first pixel block is read and the second pixel block is generated, the output second pixel block does not directly execute writing, but the difference pixel block is calculated together with the first pixel block, and the obtained difference pixel block is directly stored in the storage end address of the first pixel block, so that the effect of writing the difference pixel block into the readable and writable memory instead of the second pixel block on the premise of not covering the first pixel block is realized.

Specifically, fig. 7 is an effect diagram of a method for storing a second buffered image based on a difference pixel block according to an embodiment of the present application. When the first pixel block (1) is written into the readable and writable memory, the storage head address interval (namely the second interval (2)) of the adjacent first pixel block is set as the sum of the byte size occupied by the difference pixel block and the first pixel block, so that when the second pixel block is output, the corresponding difference pixel block (3) is obtained after the pixel value of the second pixel block is subjected to the difference between the second pixel block and the corresponding first pixel block (1), and the end address of the first pixel block (1) is stored, and the effect that the second pixel block is written into the readable and writable memory in the form of the difference pixel block on the premise that the data of any first pixel block (1) is not covered is realized.

Fig. 8 is a flowchart of a second buffered image writing method based on a difference pixel block according to an embodiment of the present application, as a possible implementation manner, after step 109, steps 110 to 111 may be further performed:

step 110: each difference pixel block is read in turn.

Step 111: and storing each difference pixel block into a memory at the terminal side respectively until all the difference pixel blocks are stored.

In the embodiment of the application, after the differential image between the first cache image and the second cache image is obtained, different storage modes can be adopted according to the requirements of users.

For example, after the first pixel block is processed and the second pixel block is obtained, if the user wants that the byte occupation of the processed image file obtained after the image processing can be further reduced, the second buffer image is not written into the memory any more, but the difference pixel blocks are written into the memory one by one directly based on the storage end address of the first pixel block, so that the difference image is used for storing instead of the processed image file.

It should be appreciated that in this storage mode, the image file to be processed may not be deleted so that the processed image file can be restored based on the image file to be processed and the difference image when viewing and editing the processed image file.

Fig. 9 is a flowchart of another method for writing a second buffered image based on a difference pixel block according to the embodiment of the present application, as a possible implementation manner, after step 109, steps 112 to 113 may be further performed.

Step 112: and reading each first pixel block and the corresponding difference pixel block in turn.

Step 113: based on each first pixel block and the corresponding difference pixel block, calculating the corresponding second pixel block, and storing the calculated second pixel blocks into a memory until all second pixel blocks are calculated and stored.

In the embodiment of the application, after the first pixel block is processed and the second pixel block is obtained, if a user hopes that the finally obtained processed image file can be executed independently of the image file to be processed, the second pixel block is restored based on the difference pixel block and the corresponding first pixel block when the second pixel block is written into the memory, and the second pixel blocks are written into the memory one by one, so that the restored second buffer image is directly written into the memory as the processed image file.

In addition, when the data format of the image file to be processed is video, a storage mode different from the mode of setting the storage head address interval pixel by pixel block can be adopted, and the same memory saving effect can be achieved on the premise of reducing the granularity of the written data and the calculated amount of the writing operation.

Fig. 10 is a flowchart of a memory management method for video cache data according to an embodiment of the present application. As a possible implementation, after step 101, steps 114 to 117 may be further performed.

Step 114: and according to the first byte size and the second byte size, sequentially calculating byte maximum values between each first frame set in the first cache image and the corresponding second frame set in the second cache image to obtain a plurality of second byte maximum values, wherein the first frame set is used for generating the second frame set.

Step 115: and setting storage head address intervals of two adjacent first frame sets according to the maximum value of each second byte in sequence to obtain a plurality of third intervals.

Step 116: based on each third interval, the corresponding first frame set is written into the readable and writable memory one by taking the set base address as a starting point.

Step 117: and reading and processing the first frame sets one by taking the set base address as a starting point, and writing the corresponding second frame sets one by one based on the storage head address of each first frame set until the writing of the second cache image is completed.

In the embodiment of the application, based on the method idea of setting a proper interval between the storage first addresses of two adjacent pixel blocks, when the image file to be processed is a video file, the byte occupation of each first frame set in the first cache image and the byte occupation of each second frame set in the second cache image can be further calculated based on the specific processing flow of video processing, the video frame number and the frame sizes of different frames; and then calculating a second byte maximum value between each first frame set and the corresponding second frame set to obtain a plurality of second byte maximum values.

It should be appreciated that since the size of the pixels is fixed throughout the same image file; the video file includes key frames and non-key frames, and possible frame rates, picture sharpness differences, etc. between different segments, the byte occupancy between different frames may not be equal. Therefore, it is necessary to completely calculate the second byte maximum value between each first frame set and the corresponding second frame set, and set the storage head address intervals of the two adjacent frame sets according to the different second byte maximum values, so as to ensure that the problems of error coverage, unwritten blank byte waste, disordered writing sequence and the like do not occur when writing frame data.

And then, determining the maximum values of the second bytes as storage head address intervals of two adjacent frame sets, obtaining a plurality of third intervals, and writing the corresponding first frame sets one by one based on each third interval. Since the following operation flows and steps 103 to 104 are not essentially different in technical principle, but the minimum unit of reading, processing and writing is changed from the pixel block to the frame set, the following method is not described here again.

In some embodiments, the memory management policy stored based on the frame set is equally applicable to the manner of using the differential image, where each third interval is determined based on a sum of a byte size of the corresponding frame set and a byte size of the corresponding differential frame set.

Furthermore, based on the different systems and hardware at different terminal sides, the same piece of image data may need to be written into different cache partitions for processing, and an additional processing policy needs to be set according to this situation.

Fig. 11 is a flowchart of a memory management method based on multiple cache partitions according to an embodiment of the present application. As a possible implementation, steps 118 to 119 may be further performed after step 102.

Step 118: based on the set base address, a plurality of cache partitions are distributed in the readable and writable memory, the sum of the sizes of the cache partitions is at least the maximum value between the first byte size and the second byte size, and the size of each cache partition is an integer multiple of the maximum value of the first byte.

Step 119: and establishing a mapping relation between the plurality of cache partitions and a first pixel block in the first cache image.

Meanwhile, step 103 may be further implemented by performing sub-steps 1041 to 1042.

Step 1041: the first byte maximum is taken as a first interval.

Step 1042: based on the first interval, the first pixel blocks are written into the corresponding cache partitions in the readable and writable memory one by one according to the mapping relation between the first pixel blocks and the cache partitions.

Meanwhile, step 104 may be further implemented by performing sub-steps 1043 to 1044.

Step 1043: and taking the set base address as a starting point, and reading and processing the first pixel blocks in the corresponding cache partitions one by one according to the storage head addresses of the first pixel blocks.

Step 1044: and writing the second pixel blocks into the cache partition corresponding to the first pixel blocks one by one based on the storage head address of each first pixel block until the writing of the second cache image is completed.

In the embodiment of the application, because the terminal side is different according to the specific processing flow of hardware, a system or an image, the requirement of setting the cache partition to process the first cache image in a blocking manner may exist. Therefore, in order to meet the requirement that the terminal side uses a plurality of cache partitions to store the first cache image in the image processing, a plurality of cache partitions capable of just accommodating the first cache image should be established first, and since the first cache image and the second cache image need to share a storage space, the cache partitions are set to at least ensure that the larger one of the first cache image and the second cache image can be completely stored. Meanwhile, the pixel blocks corresponding to the larger image also have to be completely stored in a certain cache partition, so that errors are avoided in the processing process of generating the second cache image by the first cache image due to data overflow.

In summary, from the aspect of allocation of the storage address, in order to meet the image processing requirement of the terminal side and enable the first cache image and the second cache image to be written into the set cache partitions, the plurality of cache partitions at least meet two conditions: (1) The sum of the sizes of the plurality of cache partitions is the maximum value of the first byte size and the second byte size; (2) The size of each cache partition is an integer multiple of the first byte maximum.

After establishing a plurality of cache partitions based on the two conditions, each first pixel block in the first cache image can be pre-allocated to the corresponding cache partition based on the set base address (i.e. the mapping relationship between the first pixel block and the plurality of cache partitions is established). The allocation is generally performed according to the default read sequence of the pixels and the default address high-low sequence of the cache partition, and because the specific allocation modes are more various, the details are not repeated here.

In addition, since the mapping relationship between the first pixel block and the cache partition has been established based on the set base address in the subsequent writing process of the first cache image, the writing method similar to step 103 may be directly performed based on this mapping relationship, which is not repeated here.

After the first pixel blocks in the first cached image are written into the corresponding cache partitions one by one, the second pixel blocks need to be further written according to the storage head address of each first pixel block. Because the terminal side generally creates the corresponding index item when actually creating the cache partition, and is used for recording the information such as the storage head address and the occupied byte size of the data stored in the plurality of cache partitions, the second pixel block can be directly written into the cache partition where the corresponding first pixel block is located according to the manner similar to the step 104 based on the storage head address of the first pixel block stored in the information recorded in the index item until the writing of all the second pixel blocks in the second cache image is completed.

In some embodiments, if the first pixel block is not used to generate the second pixel block, such as image clipping, image segmentation, or only a portion of pixels is changed, the second buffered image can be obtained normally without changing the portion of the first pixel block that is not used.

For this case, using multiple cache partitions to store the first cached image and ignoring the case where all the first pixel blocks in a certain cache partition do not need to be processed is a viable approach.

First, the method includes the steps of. According to the specific processing flow of the image, counting whether first pixel blocks needing to be processed exist in all first pixel blocks in the first cached image or not, and searching a cache partition where the first pixel blocks needing to be processed are located. After the corresponding cache partitions are found, the read, processing, and write-in overwriting of the corresponding second pixel blocks are performed on all of the first pixel blocks in the cache partitions. In the case that there is no first pixel block in the cache partition that needs to perform image processing, the cache partition is directly ignored because all the first pixel blocks in the cache partition do not need to be read.

By the processing strategy, the calculated amount of image processing can be effectively reduced, and the reading, processing and writing of the first cache image and the second cache image can be completed more quickly.

Referring to fig. 12, based on the same inventive concept, an embodiment of the present application further provides a memory management device, provided at a terminal side, where a readable and writable memory exists, the device includes:

a calculating unit 201, configured to calculate a first byte size corresponding to a first buffered image as input and a second byte size corresponding to a second buffered image as output;

The calculating unit 201 is further configured to calculate a first byte maximum value between a first pixel block of the first buffered image and a second pixel block of the second buffered image according to the first byte size and the second byte size, where the first pixel block is used to generate the second pixel block;

a memory read/write unit 202, configured to write the first pixel blocks into the readable/writable memory one by one based on a first interval with the first byte maximum value as a first interval of storage first addresses of two adjacent first pixel blocks and with a set base address as a starting point;

the memory read/write unit 202 is further configured to read and process the first pixel blocks one by one with the set base address as a starting point, and write the corresponding second pixel blocks one by one based on the storage first address of each first pixel block until the writing of the second buffered image is completed.

Optionally, the computing unit 201 is specifically configured to:

determining the first maximum value as a first byte maximum value; or,

in response to the first pixel block containing a plurality of first pixels, the second pixel block containing a single second pixel, calculating a second maximum value between a sum of bytes occupied by the plurality of first pixels and bytes occupied by the single second pixel according to the first byte size and the second byte size;

Determining the second maximum value as the first byte maximum value; or,

in response to the first pixel block containing a single first pixel, the second pixel block containing a plurality of second pixels, calculating a third maximum value between the byte occupied by the single first pixel and the sum of the bytes occupied by the plurality of second pixels according to the first byte size and the second byte size;

the third maximum is determined to be the first byte maximum.

Optionally, the apparatus further comprises:

the calculating unit 201 is further configured to calculate, according to the first byte size and the second byte size, a fourth byte size corresponding to the first pixel block, and a third byte size expected to be occupied by a difference pixel block generated by the difference processing of the first pixel block and the second pixel block;

a first address interval setting unit, configured to use a sum of a fourth byte size and a corresponding third byte size as a second interval for storing first addresses of two adjacent first pixel blocks;

the memory read/write unit 202 is further configured to write the first pixel blocks into the readable/writable memory one by one based on the second interval, with the set base address as a starting point;

the memory read/write unit 202 specifically is configured to:

reading and processing the first pixel blocks one by one with the set base address as a starting point, and responding to the output of the corresponding second pixel blocks, and calculating corresponding difference pixel blocks based on the current first pixel blocks and the second pixel blocks;

And writing the corresponding difference pixel blocks one by one based on the storage end address of each first pixel block until the whole writing of the difference pixel blocks is completed.

Optionally, the apparatus further comprises:

a reading unit for sequentially reading each difference pixel block;

the reading unit is also used for sequentially reading each first pixel block and the corresponding difference pixel block;

and the storage unit is also used for calculating corresponding second pixel blocks based on each first pixel block and the corresponding difference pixel block and storing the calculated second pixel blocks into the memory until all the second pixel blocks are calculated and stored.

Optionally, the first buffer image and the second buffer image are both video buffer data, and the calculating unit 201 is further configured to sequentially calculate byte maximum values between each first frame set in the first buffer image and a second frame set in the corresponding second buffer image according to the first byte size and the second byte size, so as to obtain a plurality of second byte maximum values, where the first frame set is used to generate the second frame set;

The first address interval setting unit is further used for setting storage first address intervals of two corresponding adjacent first frame sets according to the maximum value of each second byte in sequence to obtain a plurality of third intervals;

the memory read-write unit 202 is further configured to write the corresponding first frame set into the readable-writable memory one by one based on each third interval with the set base address as a starting point;

the memory read/write unit 202 is further configured to read and process the first frame sets one by one with the set base address as a starting point, and write the corresponding second frame sets one by one based on the storage head address of each first frame set until the writing of the second buffered image is completed.

Optionally, the apparatus further comprises:

the system comprises a cache partition establishing unit, a first byte storing unit and a second byte storing unit, wherein the cache partition establishing unit is used for distributing a plurality of cache partitions in a readable and writable memory based on a set base address, the sum of the sizes of the plurality of cache partitions is at least the maximum value between the first byte size and the second byte size, and the size of each cache partition is an integer multiple of the maximum value of the first byte;

the pixel mapping unit establishes a mapping relation between a plurality of cache partitions and a first pixel block in the first cache image;

the memory read/write unit 202 specifically is configured to:

taking the first byte maximum value as a first interval;

Based on the first interval, writing the first pixel blocks into corresponding cache partitions in the readable and writable memory one by one according to the mapping relation between the first pixel blocks and the cache partitions;

reading and processing the first pixel blocks in the corresponding cache partitions one by one according to the storage first addresses of the first pixel blocks by taking the set base address as a starting point;

and writing the second pixel blocks into the cache partition corresponding to the first pixel blocks one by one based on the storage head address of each first pixel block until the writing of the second cache image is completed.

Referring to fig. 13, based on the same inventive concept, an electronic device 300 is further provided, where the electronic device 300 may include at least one processor, and the at least one processor is configured to execute a computer program stored in a memory, to implement the steps of the memory management method shown in fig. 1 to 4, 6 and 8 to 11 provided in the embodiment of the present application.

In the alternative, the processor may be a central processing unit, a specific ASIC, or one or more integrated circuits for controlling the execution of the program.

Optionally, the electronic device 300 may further include a memory coupled to the at least one processor, the memory may include ROM, RAM, and disk memory. The memory is used for storing data required by the processor when running, i.e. instructions executable by at least one processor, and the at least one processor performs the methods shown in fig. 1-4, 6 and 8-11 by executing the instructions stored by the memory. Wherein the number of memories is one or more.

The physical devices corresponding to the computing unit 201 and the memory read/write unit 202 may be the aforementioned processors. The electronic device may be used to perform the methods provided by the embodiments shown in fig. 1-4, 6 and 8-11. Therefore, for the functions that can be implemented by each functional module in the electronic device, reference may be made to corresponding descriptions in the embodiments shown in fig. 1-4, fig. 6 and fig. 8-11, which are not repeated.

The electronic device 300 may be an intelligent electronic device such as a smart phone or a tablet computer, and the form of the electronic device is not limited in this embodiment.

By way of example, fig. 13 illustrates a schematic diagram of an electronic device 300 using a smart phone as an example, as shown in fig. 13, the electronic device 300 may include a processor 310, an external memory interface 320, an internal memory 321, a universal serial bus (universal serial bus, USB) interface 330, a charge management module 340, a power management module 341, a battery 342, an antenna 1, an antenna 2, a mobile communication module 350, a wireless communication module 360, an audio module 370, a speaker 370A, a receiver 370B, a microphone 370C, an earphone interface 370D, a sensor module 380, keys 390, a motor 391, an indicator 392, a camera 393, a display screen 394, and a user identification card (subscriber identification module, SIM) card interface 395, etc.

It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 300. In other embodiments of the application, electronic device 300 may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 310 may include one or more processing units, such as: the processor 310 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 310 for storing instructions and data. In some embodiments, the memory in the processor 310 is a cache memory. The memory may hold instructions or data that the processor 310 has just used or recycled. If the processor 310 needs to reuse the instruction or data, it may be called directly from the memory. Repeated accesses are avoided and the latency of the processor 310 is reduced, thereby improving the efficiency of the system.

In some embodiments, processor 310 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The charge management module 340 is configured to receive a charge input from a charger.

The power management module 341 is configured to connect the battery 342, the charge management module 340 and the processor 310.

In some embodiments, antenna 1 and mobile communication module 350 of electronic device 100 are coupled, and antenna 2 and wireless communication module 360 are coupled, such that electronic device 300 may communicate with a network and other devices via wireless communication techniques. The wireless communication techniques may include the Global System for Mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The electronic device 300 implements display functions through a GPU, a display screen 394, an application processor, and the like.

The display screen 394 is used for displaying images, videos, and the like. The display screen 394 includes a display panel.

The ISP is used to process the data fed back by camera 393.

Camera 393 is used to capture still images or video.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 300 is selecting a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.

Video codecs are used to compress or decompress digital video. The electronic device 300 may support one or more video codecs. Thus, the electronic device 300 may play or record video in a variety of encoding formats, such as: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The external memory interface 320 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 300. The external memory card communicates with the processor 310 through an external memory interface 320 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 321 may be used to store computer executable program code comprising instructions. The internal memory 321 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device 300 (e.g., audio data, phonebook, etc.), and so on. In addition, the internal memory 321 may include a high-speed random access memory, and may also include a nonvolatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 310 performs various functional applications of the electronic device 300 and data processing by executing instructions stored in the internal memory 321, and/or instructions stored in a memory provided in the processor.

The electronic device 300 may implement audio functionality through an audio module 370, a speaker 370A, a receiver 370B, a microphone 370C, an ear-headphone interface 370D, and an application processor, among others. Such as music playing, recording, etc.

The audio module 370 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal.

Speaker 370A, also known as a "horn," is used to convert audio electrical signals into sound signals.

A receiver 370B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal.

Microphone 370C, also referred to as a "microphone," is used to convert sound signals into electrical signals.

The earphone interface 370D is for connecting a wired earphone. The headset interface 370D may be a USB interface 330 or a 3.5mm open mobile electronic device platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The keys 390 include a power on key, a volume key, etc.

The motor 391 may generate a vibration alert.

The indicator 392 may be an indicator light, which may be used to indicate a state of charge, a change in charge, a message indicating a missed call, a notification, etc.

The SIM card interface 395 is for interfacing with a SIM card. In some embodiments, the electronic device 300 employs esims, namely: an embedded SIM card. The eSIM card can be embedded in the electronic device 300 and cannot be separated from the electronic device 300.

The embodiment of the application also provides a computer storage medium, wherein the computer storage medium stores computer instructions, and when the computer instructions run on a computer, the computer is caused to perform the methods as described in fig. 1-4, 6 and 8-11.

The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. The memory management method is characterized by being applied to a terminal side, wherein a readable and writable memory exists on the terminal side, and the method comprises the following steps:

2. The method of claim 1, wherein calculating a first byte maximum between a first pixel block of the first cached image and a second pixel block of the second cached image based on the first byte size and the second byte size comprises:

determining the first maximum value as the first byte maximum value; or,

Determining the second maximum value as the first byte maximum value; or,

the third maximum value is determined to be the first byte maximum value.

3. The method of claim 1, wherein after the calculating the first byte size corresponding to the first buffered image as input and the second byte size corresponding to the second buffered image as output, the method further comprises:

4. A method according to claim 3, wherein said writing of the corresponding difference pixel blocks one by one is based on the stored end address of each of the first pixel blocks until after the completion of all writing of the difference pixel blocks, the method further comprising:

reading each difference pixel block in turn;

5. The method of claim 1, wherein the first buffered image and the second buffered image are both video buffered data, and wherein after the calculating the first byte size corresponding to the first buffered image as input and the second byte size corresponding to the second buffered image as output, the method further comprises:

6. The method of claim 1, wherein the calculating a first byte maximum between a first pixel block of the first cached image and a second pixel block of the second cached image based on the first byte size and the second byte size, the first pixel block being used after generating the second pixel block, the method further comprises:

taking the first byte maximum value as the first interval;

7. A memory management device, disposed on a terminal side, where a readable and writable memory exists, the device comprising:

8. The apparatus according to claim 7, wherein the computing unit is specifically configured to:

determining the first maximum value as the first byte maximum value; or,

Determining the second maximum value as the first byte maximum value; or,

the third maximum value is determined to be the first byte maximum value.

9. An electronic device comprising at least one processor and a memory coupled to the at least one processor, the at least one processor being configured to implement the steps of the method of any of claims 1-6 when executing a computer program stored in the memory.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any of claims 1-6.