CN117234349A

CN117234349A - Capacitance sensing device and capacitance sensing method

Info

Publication number: CN117234349A
Application number: CN202210648173.9A
Authority: CN
Inventors: 蔡旭铭
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2023-12-15

Abstract

Embodiments of the present disclosure relate to a capacitive sensing apparatus and a capacitive sensing method. The capacitive sensing device includes switching circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second inputs and an output, and a feedback capacitor. The feedback capacitor is coupled between the first input terminal and the output terminal of the amplifier circuit, and the first input terminal is coupled to the capacitor to be tested. The switching circuitry transmits the first voltage to the second input terminal and couples the first input terminal to the output terminal in the first stage, and transmits the second voltage to the second input terminal in the second stage, and adjusts the output voltage of the output terminal in the third stage. The counter circuit starts counting in a third stage and stops counting according to the control signal to generate a count value capable of reflecting the capacitance change of the capacitor to be measured. The comparator circuit generates a control signal according to the output voltage and the second reference voltage in a third stage.

Description

Capacitance sensing device and capacitance sensing method

Technical Field

The present disclosure relates to a capacitive sensing device, and more particularly, to a capacitive sensing device and a capacitive sensing method capable of sensing a change in capacitance of a touch device.

Background

Touch devices are commonly found in electronic products for various applications. Touch input is received by using a touch element connected to a specific potential (e.g., ground) in a self-capacitive touch device. In some related art, the capacitive sensing circuit has a high circuit complexity, and the capacitive sensing circuit directly amplifies the charge variation on the touch device by using an amplifier, and directly outputs a signal generated by the amplifier as a sensing signal. However, in the above technique, the amplifier may amplify noise in the system together so that the output becomes supersaturated. Thus, the operation of the sensing circuit will fail, and it cannot be effectively identified whether the touch input is received.

Disclosure of Invention

In some embodiments, it is an object of the present invention (but not limited to) to provide a capacitive sensing device and a capacitive sensing method for confirming a change of capacitance by using a counter, so as to overcome the above-mentioned drawbacks of the prior art.

In some embodiments, a capacitive sensing device includes an amplifier circuit, a feedback capacitor, switching circuitry, a counter circuit, and a comparator circuit. The first input of the amplifier circuit is coupled to the capacitor under test. The feedback capacitor is coupled between the first input terminal and the output terminal of the amplifier circuit. The switching circuitry is configured to transmit a first reference voltage to a second input of the amplifier circuit and couple the first input to the output in a first stage, to transmit a second reference voltage to the second input in a second stage, and to adjust an output voltage of the output in a third stage. The counter circuit is used for starting counting in a third stage and stopping counting according to the control signal to generate a count value, wherein the count value is used for reflecting the capacitance change of the capacitor to be tested. The comparator circuit is used for generating a control signal according to the output voltage and the second reference voltage in a third stage.

In some embodiments, the capacitive sensing method includes the following operations: in a first stage, transmitting a first reference voltage to a first input terminal of an amplifier circuit, and coupling a second input terminal of the amplifier circuit to an output terminal of the amplifier circuit, wherein the second input terminal is coupled to the output terminal via a feedback capacitor and coupled to ground via a capacitor under test; transmitting a second reference voltage to the first input terminal in a second stage; in a third stage, adjusting the output voltage of the output end and generating a control signal according to the output voltage and the second reference voltage; and starting counting when entering the third stage, and stopping counting according to the control signal to generate a count value, wherein the count value is used for reflecting the capacitance change of the capacitor to be tested.

The features, implementation and effects of the present invention are described in detail below with reference to the preferred embodiments of the present invention in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a capacitive sensing device according to some embodiments of the present disclosure;

FIG. 2A is a schematic circuit diagram of the capacitive sensing device of FIG. 1, drawn according to some embodiments of the present disclosure;

FIG. 2B is a schematic diagram of waveforms of the signals and voltages of FIG. 2A according to some embodiments of the present disclosure;

FIG. 3A is a schematic circuit diagram of the capacitive sensing device of FIG. 1, drawn according to some embodiments of the present disclosure;

FIG. 3B is a schematic diagram of waveforms of the signals and voltages of FIG. 2A according to some embodiments of the present disclosure; and

fig. 4 is a flow chart of a capacitive sensing method according to some embodiments of the present disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The foregoing words are defined in commonly used dictionaries, and any examples of use of words in this document, including any discussion herein, are intended to be illustrative only and should not be interpreted as limiting the scope and meaning of the present disclosure. Similarly, the present disclosure is not limited to the various embodiments shown in this specification.

As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other. As used herein, the term "circuitry" may be a single system formed of at least one circuit, and the term "circuitry" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. First, second, third, etc. words are used herein to describe and identify various components. Accordingly, a first component may also be referred to herein as a second component without departing from the intent of the present disclosure. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.

Fig. 1 is a schematic diagram of a capacitive sensing device 100 according to some embodiments of the present disclosure. In some embodiments, the capacitive sensing device 100 can sense the capacitance variation of the capacitor under test CT. In some embodiments, the capacitor under test CT may be, but is not limited to, a touch device in a touch screen. For example, the capacitor CT to be measured may be a self-capacitance touch device. The capacitive sensing device 100 can sense whether the capacitance of the capacitor CT to be detected changes to determine whether the capacitor CT to be detected is touched.

In some embodiments, the capacitive sensing device 100 includes an amplifier circuit 110, switching circuitry 120, a counter circuit 130, a comparator circuit 140, a digital control circuit 150, and a feedback capacitor CFB. The first input (e.g., a negative input) of the amplifier circuit 110 is coupled to the capacitor under test CT, and the other end of the capacitor under test CT is coupled to ground. A second input (e.g., a positive input) of the amplifier circuit 110 is coupled to the switching circuitry 120 for sequentially receiving the reference voltage VREF1 and the reference voltage VREF2 at different stages. The feedback capacitor CFB is coupled between the negative input and the output of the amplifier circuit 110.

Switching circuitry 120 transmits reference voltage VREF1 to the positive input of amplifier circuit 110 in a first stage (e.g., stage P1 of fig. 2B or 3B) and couples the negative input of amplifier circuit 110 to the output of amplifier circuit 110. Switching circuitry 120 transmits reference voltage VREF2 to the positive input of amplifier circuit 110 in a second stage (e.g., stage P2 in fig. 2B or fig. 3B) and adjusts output voltage VO at the output of amplifier circuit 110 in a third stage (e.g., stage P3 in fig. 2B or fig. 3B). In some embodiments, the switching circuitry 120 may perform the above-described operations at different stages according to the plurality of signals S1-S4.

The counter circuit 130 starts counting in the third stage, and stops counting according to the control signal SC and outputs the count value CNT, wherein the count value CNT can be used to reflect the capacitance change of the capacitor CT to be measured.

The comparator circuit 140 generates the control signal SC according to the output voltage VO and the reference voltage VREF2 in the third stage. In the present embodiment, the comparator circuit 140 detects whether the output voltage VO is less than or equal to the reference voltage VREF2 in the third stage, and generates the control signal SC when the output voltage VO is less than or equal to the reference voltage VREF2. The digital control circuit 150 can generate the signals S1 to S4 according to the control signal SC in the third stage, and determine whether the capacitance value of the capacitor CT to be tested changes according to the count value CNT. For example, the digital control circuit 150 may confirm whether to switch the plurality of signals S1 to S4 according to the control signal SC in the third stage, and generate the enable signal EN to control the counter circuit 130 to start counting when entering the third stage. If the count value CNT exceeds the preset range (or is different from the default value), the digital control circuit 150 can determine that the capacitance of the capacitor CT to be tested changes, i.e. the capacitor CT to be tested is touched. In some embodiments, digital control circuit 150 may be implemented by, but not limited to, several logic circuits executing a finite state machine or by digital signal processing circuitry.

Fig. 2A is a circuit diagram of the capacitive sensing device 100 of fig. 1, drawn according to some embodiments of the disclosure. In this example, reference voltage VREF1 is lower than reference voltage VREF2, and switching circuitry 120 is configured to switch current I in the third stage _int To the negative input of the amplifier circuit 110 to regulate the output voltage VO.

Specifically, the switching circuitry 120 includes a plurality of switches SW1 to SW4 and a current source circuit 210. A first terminal of the switch SW1 receives the reference voltage VREF1, a second terminal of the switch SW1 is coupled to the positive input terminal of the amplifier circuit 110, and a control terminal (not shown) of the switch SW1 receives the signal S1. The switch SW1 is turned on in the first stage according to the signal S1 to transmit the reference voltage VREF1 to the positive input terminal of the amplifier circuit 110. A first terminal of the switch SW2 is coupled to the negative input terminal of the amplifier circuit 110, a second terminal of the switch SW2 is coupled to the output terminal of the amplifier circuit 110, and a control terminal (not shown) of the switch SW2 receives the signal S2. The switch SW2 is turned on in the first stage according to the signal S2 to couple the negative input terminal of the amplifier circuit 110 toAn output of the amplifier circuit 110. In other words, when the switch SW2 is turned on, the negative input terminal and the output terminal of the amplifier circuit 110 have the same level. A first terminal of the switch SW3 receives the reference voltage VREF2, a second terminal of the switch SW3 is coupled to the positive input terminal of the amplifier circuit 110, and a control terminal (not shown) of the switch SW3 receives the signal S3. The switch SW3 is turned on in the second stage according to the signal S3 to transmit the reference voltage VREF2 to the positive input terminal of the amplifier circuit 110. A first terminal of the switch SW4 is coupled to the current source circuit 210, a second terminal of the switch SW4 is coupled to the negative input terminal of the amplifier circuit 110, and a control terminal (not shown) of the switch SW4 receives the signal S4. The switch SW4 is turned on in the third stage according to the signal S3 to couple the current source circuit 210 to the negative input terminal of the amplifier circuit 110. In this way, the current source circuit 210 can supply the current I via the switch SW4 _int To the negative input of the amplifier circuit 110 to regulate the output voltage VO.

Fig. 2B is a schematic diagram of waveforms of the signals and voltages in fig. 2A according to some embodiments of the present disclosure. For describing the operation of the capacitive sensing device 100, please refer to fig. 2A and fig. 2B together. Fig. 2B shows two consecutive sensing periods, in which the capacitor under test CT is not touched (no capacitance change is generated) in the 1 st sensing period, and is touched (capacitance change is generated) in the 2 nd sensing period.

At time T1, signals S1 and S2 switch to an enable level (e.g., high). In the stage P1 where the signals S1 and S2 have the enable level, the switches SW1 and SW2 are turned on. In this way, the switch SW1 transmits the reference voltage VREF1 to the positive input of the amplifier circuit 110, and the switch SW2 couples the negative input of the amplifier circuit 110 to its output. Because of the virtual ground characteristic, the level of the negative input terminal of the amplifier circuit 110 is the same as the level of the positive input terminal of the amplifier circuit 110, so that the levels of the negative input terminal, the positive input terminal and the output terminal of the amplifier circuit 110 are all the reference voltage VREF1, wherein the voltage at the negative input terminal of the amplifier circuit 110 is denoted as the voltage VA. By the above operation, in the stage P1, the capacitor CT to be measured is charged by the reference voltage VREF1 to store the charge amount ct×vref1, and the voltage across the two ends of the feedback capacitor CFB is 0, so that the feedback capacitor CFB does not store the charge. In the stage P1, the output voltage VO is the same as the reference voltage VREF1 and is lower than the reference voltage VREF2. Thus, the comparator circuit 140 outputs the control signal SC having the first level (e.g., high level). Since the digital control circuit 150 does not operate according to the control signal SC in the stage P1, the digital control circuit 150 does not malfunction.

At time T2, signals S1 and S2 switch to a disable level (e.g., low), and signal S3 switches to an enable level (e.g., high). At time T3, signal S4 switches to an enable level (e.g., high). In a phase P2 between time T2 and time T3, switch SW1 is turned off in response to signal S1, switch SW2 is turned off in response to signal S2, and switch SW3 is turned on in response to signal S3. Thus, in stage P2, the switch SW1 stops transmitting the reference voltage VREF1 to the positive input terminal of the amplifier circuit 110, the switch SW3 transmits the reference voltage VREF2 to the positive input terminal of the amplifier circuit 110, and the negative input terminal of the amplifier circuit 110 is no longer coupled to the output terminal of the amplifier circuit 110 through the switch SW 2. Due to the nature of virtual ground, the level of the negative input of the amplifier circuit will rise to the reference voltage VREF2 during stage P2. By the above operation, the capacitor to be measured CT is charged by the reference voltage VREF2 and stores an amount of charge ct×vref2, and the voltage difference between the two ends of the feedback capacitor CFB is the difference between the reference voltage VREF2 and the output voltage VO, so the feedback capacitor CFB stores an amount of charge cfb× (VREF 2-VO). In addition, in the phase P2, the output voltage VO is briefly higher than the reference voltage VREF2 in response to the voltage variation. Thus, the comparator circuit 140 outputs the control signal SC having the second level (e.g., low level). Since the digital control circuit 150 does not operate according to the control signal SC in the stage P2, the digital control circuit 150 does not malfunction.

In the operations of the stage P1 and the stage P2, based on the law of conservation of charge, it can be known that the amount of charge increased by the capacitor CT to be measured should be the same as the amount of charge decreased by the feedback capacitor CFB, which can be expressed as the following formula (1):

VREF2×CT-VREF1×CT＝(VREF2-VO)×CFB…(1)

further, it can be deduced from the above formula (1) that the output voltage VO should conform to the following formula (2):

in phase P3, where signal S4 has an enable level (e.g., high), switch SW3 is continuously turned on in response to signal S3, and switch SW4 is turned on in response to signal S4. In this way, the switch SW3 continuously transmits the reference voltage VREF2 to the positive input terminal of the amplifier circuit 110, and the current source circuit 210 can supply the current I through the switch SW4 _int To the negative input of the amplifier circuit 110 to regulate the output voltage VO. Upon entering phase P3, the counter circuit 130 may begin counting based on the enable signal EN. When the level of the output voltage VO is adjusted to be equal to (or lower than) the reference voltage VREF2 (i.e., time T4), the comparator circuit 140 outputs the control signal SC having a high level. In response to the control signal SC, the counter circuit 130 stops counting and outputs a count value CNT to the digital control circuit 150 to determine whether the capacitance change occurs in the capacitor CT. In the above operation, the amount of charge stored in the capacitor under test CT is unchanged, and the amount of charge stored in the feedback capacitor CFB is changed from cfb× (VREF 2-VO) to cfb× (VREF 2-VREF 2). Therefore, based on the law of conservation of charge, it can be known that the charge variation of the feedback capacitor CFB should be the same as the charge amount provided by the current source circuit 210, which can be expressed as the following formula (3), wherein T is the amount of the charge that the switch SW4 starts to be turned on (i.e. the current source circuit 210 starts to supply the current I _int A negative input terminal to the amplifier circuit 110) to a stage between the output voltage VO being adjusted to be equal to (or lower than) the reference voltage VREF2:

I _int ×T＝(VREF2-VREF2)×CFB-(VREF2-VO)×CFB…(3)

from the formula (2) and the formula (3), the following formula (4) can be deduced:

as can be seen from equation (4), due to reference voltage VREF1, reference voltage VREF2, and current I _int Are all fixedThe value of the phase T is proportional to the capacitance of the capacitor CT to be measured. Since the counter circuit 130 starts counting in the phase P3 and stops counting when the output voltage VO is equal to the reference voltage VREF2, the count value CNT generated by the counter circuit 130 is used to indicate the time duration of the phase T. If the count value CNT does not exceed the predetermined range (or is the same as the predetermined value), it means that the capacitor CT is not touched and no capacitance change occurs. Furthermore, based on equation (4), it can be known that the time period of the phase T is proportional to the voltage difference between the reference voltage VREF1 and the reference voltage VREF2. In other words, the count value CNT is proportional to the voltage difference between the reference voltage VREF1 and the reference voltage VREF2. In some embodiments, the values of the reference voltage VREF1 and the reference voltage VREF2 can be adjusted according to the actual requirements of the system.

Similarly, in the 2 nd sensing period, the capacitive sensing apparatus 100 can repeatedly perform the same operation to confirm whether the capacitance change occurs in the capacitor CT under test. As described above, in the 2 nd sensing period, the capacitor CT to be measured is touched to increase its capacitance. The phase P2 of the output voltage VO in the 2 nd sensing period rises to a higher level than the 1 st sensing period. Therefore, in the stage P3, the output voltage VO needs more time to drop to the reference voltage VREF2. Thus, the period of time of the phase T becomes longer and the count value CNT becomes higher. In other words, the count value CNT is proportional to the capacitance change of the capacitor CT. If the count value CNT exceeds the predetermined range (or is higher than the predetermined value), it represents that the capacitor CT to be tested is touched to generate a capacitance change.

Fig. 3A is a circuit diagram of the capacitive sensing device 100 of fig. 1, drawn according to some embodiments of the disclosure. In this example, the reference voltage VREF2 is lower than the reference voltage VREF1, and the switching circuitry 120 is configured to draw the current I from the negative input of the amplifier circuit 110 in the third stage, as compared to FIG. 2A _int To ground to regulate the output voltage VO.

In detail, unlike the current source circuit 210 of fig. 2A, in this example, the current source circuit 210 is coupled to ground from the negative input terminal of the amplifier circuit 110 via the switch SW4 to draw from the negative input terminal of the amplifier circuit 110Current I _int To ground to regulate the output voltage VO.

FIG. 3B is a schematic diagram of waveforms of the signals and voltages of FIG. 3A according to some embodiments of the present disclosure. Similar to fig. 2B, fig. 3B shows two consecutive sensing periods, in which the capacitor under test CT is not touched (no capacitance change is generated) in the 1 st sensing period and is touched (capacitance change is generated) in the 2 nd sensing period. As described above, in the example of fig. 3A, the reference voltage VREF2 is set lower than the reference voltage VREF1. Therefore, the comparator circuit outputs the control signal SC with a low level when the output voltage VO is equal to (or higher than) the reference voltage VREF2, so the counter circuit 130 may be set to stop counting in response to the control signal SC with a low level.

Since reference voltage VREF2 is lower than reference voltage VREF1, output voltage VO is lower from reference voltage VREF1 during stage P2. In the stage P3, the level of the output voltage VO gradually rises to be equal to or higher than the reference voltage VREF2 through the adjustment of the current source circuit 210. The operation of the switches SW1 to SW4 and the change of the charge amount of each of the capacitor under test CT and the feedback capacitor CFB are the same as those described in fig. 2B, and thus the description thereof will not be repeated here. In this example, the phase T is a phase between when the switch SW4 of fig. 3A starts to turn on and the output voltage VO is adjusted to be equal to (or higher than) the reference voltage VREF2. In fig. 3B, if the capacitor CT to be measured is touched to increase the capacitance, the output voltage VO drops to a lower level in the stage P2. Therefore, in the stage P3, the output voltage VO needs more time to rise to the reference voltage VREF2. In other words, the period of time of the phase T becomes longer and the count value CNT becomes higher. Therefore, whether the capacitance value of the capacitor CT to be tested changes or not can be judged according to the count value CNT. The detailed operation and charge derivation of fig. 3B is similar to that of fig. 2B, and thus the detailed description thereof will not be repeated here.

Fig. 4 is a flow chart of a capacitive sensing method 400, drawn according to some embodiments of the present disclosure. In operation S410, in a first stage, a first reference voltage is transmitted to a first input terminal of an amplifier circuit, and a second input terminal of the amplifier circuit is coupled to an output terminal of the amplifier circuit, wherein the second input terminal is further coupled to the output terminal via a feedback capacitor and coupled to ground via a capacitor under test. In operation S420, in a second phase, a second reference voltage is transmitted to the first input terminal. In operation S430, in a third stage, an output voltage of the output terminal is adjusted, and a control signal is generated according to the output voltage and the second reference voltage. In operation S440, the counting is started when the third stage is entered, and the counting is stopped according to the control signal to generate a count value, wherein the count value is used to reflect the capacitance change of the capacitor to be tested.

The above description of the operations of the capacitive sensing method 400 can refer to the above embodiments, and thus will not be repeated herein. The above-described operations are merely examples and are not limited to being performed in the order in this example. The various operations under the capacitive sensing method 400 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure. Alternatively, one or more operations under the capacitive sensing method 400 may be performed simultaneously or partially simultaneously.

In summary, the capacitance sensing device and the capacitance sensing method provided in some embodiments of the present disclosure can utilize a counter to generate a count value that can be used to reflect whether the capacitance of the capacitor to be measured changes. Thus, the count value is monitored to determine whether the capacitor to be tested is touched.

Although the embodiments of the present disclosure have been described in detail, these embodiments are not intended to be limiting, and those of ordinary skill in the art will appreciate that many modifications are possible in light of the disclosure's teachings or teachings, and that many modifications are possible within the scope of the disclosure, i.e., the scope of the disclosure is defined by the claims.

Reference numerals

100: capacitance sensing device

110: amplifier circuit

120: switching circuit system

130: counter circuit

140: comparator circuit

150: digital control circuit

210: current source circuit

400: capacitance sensing method

CFB: feedback capacitor

CNT: count value

CT: capacitor to be measured

EN: enable signal

I _int : electric current

P1 to P3: stage(s)

S1-S4: signal signal

S410, S420, S430, S440: operation of

SC: control signal

SW1 to SW4: switch

T: stage(s)

T1 to T4: time of

VA: voltage (V)

VO: output voltage

VREF1, VREF2: reference voltage

Claims

1. A capacitive sensing device, comprising:

an amplifier circuit, wherein a first input of the amplifier circuit is coupled to a capacitor under test;

a feedback capacitor coupled between the first input and an output of the amplifier circuit;

switching circuitry to transmit a first reference voltage to a second input of the amplifier circuit in a first stage and to couple the first input to the output, and to transmit a second reference voltage to the second input in a second stage and to adjust an output voltage of the output in a third stage;

the counter circuit is used for starting counting in the third stage and stopping counting according to a control signal to generate a count value, wherein the count value is used for reflecting the capacitance change of the capacitor to be tested; and

and the comparator circuit is used for generating the control signal according to the output voltage and the second reference voltage in the third stage.

2. The capacitive sensing device of claim 1, wherein the first reference voltage is lower than the second reference voltage, and the switching circuitry is to transmit current to the first input to adjust the output voltage in the third phase.

3. The capacitive sensing device of claim 1, wherein the second reference voltage is lower than the first reference voltage, and the switching circuitry is to draw current from the first input to ground to adjust the output voltage in the third phase.

4. The capacitive sensing device of claim 1, wherein the switching circuitry comprises:

a first switch for conducting in the first phase to transmit the first reference voltage to the second input terminal;

a second switch for conducting in the first phase to couple the first input terminal to the output terminal;

a third switch for conducting in the second stage to transmit the second reference voltage to the second input terminal;

a current source circuit; and

a fourth switch for conducting in the third stage to couple the current source circuit to the first input terminal to adjust the output voltage.

5. The capacitive sensing device of claim 4, wherein the first reference voltage is lower than the second reference voltage, and the current source circuit is configured to transmit current to the first input via the fourth switch.

6. The capacitive sensing device of claim 4, wherein the second reference voltage is lower than the first reference voltage and the current source circuit is to draw current from the first input to ground via the fourth switch.

7. The capacitance sensing device of claim 1, wherein a capacitance change of the capacitor under test is proportional to the count value.

8. The capacitance sensing device according to claim 1, wherein the count value indicates a length of time between when the counter circuit starts counting to a stage when the output voltage is less than or equal to the second reference voltage, or indicates a length of time between when the counter circuit starts counting to a stage when the output voltage is greater than or equal to the second reference voltage.

9. The capacitive sensing device of claim 1, wherein the count value is proportional to a voltage difference between the first reference voltage and the second reference voltage.

10. A capacitive sensing method, comprising:

in a first stage, transmitting a first reference voltage to a first input of an amplifier circuit and coupling a second input of the amplifier circuit to an output of the amplifier circuit, wherein the second input is coupled to the output via a feedback capacitor and to ground via a capacitor under test;

transmitting a second reference voltage to the first input terminal in a second stage;

in a third stage, adjusting the output voltage of the output end, and generating a control signal according to the output voltage and the second reference voltage; and

and starting counting when entering the third stage, and stopping counting according to the control signal to generate a count value, wherein the count value is used for reflecting the capacitance change of the capacitor to be tested.