CN117223293A - High-speed low-power consumption pixel bias circuit - Google Patents

High-speed low-power consumption pixel bias circuit Download PDF

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CN117223293A
CN117223293A CN202280025448.1A CN202280025448A CN117223293A CN 117223293 A CN117223293 A CN 117223293A CN 202280025448 A CN202280025448 A CN 202280025448A CN 117223293 A CN117223293 A CN 117223293A
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capacitor
current
inverter
terminal
switch
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樱木高正
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The present application may provide an imaging sensor circuit disposed in pixels located at a specific row and a specific column in a pixel array. The imaging sensor circuit may include a reading unit for reading data of a pixel, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line; and the feedback unit is used for feeding back the boost current to the output line, wherein the feedback unit comprises a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch and a current mirror element. In the imaging sensor circuit, a part of the current on the output line is used as the input current of the feedback unit, the boost current can be generated through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch and the current mirror element, and the boost current can be used for discharging the parasitic capacitor.

Description

High-speed low-power consumption pixel bias circuit
Technical Field
The present application relates to the field of imaging devices, and more particularly, to an imaging sensor and a driving method thereof, which can reduce the settling time of the pixel output of the imaging sensor.
Background
In recent years, with the advancement of social informatization, broadband communication technology has rapidly progressed. Such developments make it easier to process relatively large amounts of data, and therefore, image information is frequently transmitted. In this case, a digital camera is dominant as an imaging device for acquiring image information, and most cellular phones now have such an imaging function. The core function of the digital camera is a charge-coupled device (CCD) imaging sensor or a complementary metal oxide semiconductor (complementary metal-oxide semiconductor, CMOS) imaging sensor, which has been developed for various applications such as mobile devices, monitoring devices, and in-vehicle devices.
There is an increasing demand for high-speed, low-power, high-resolution imaging sensors, whether CCD imaging sensors or CMOS imaging sensors. One of the approaches to implementing high speed, low power consumption and high resolution imaging sensors is to provide feedback current to the output signal lines of the pixels through one or more additional feedback circuits. However, this approach encounters three difficulties as described below.
That is, the implementation of such high-speed imaging sensors typically requires a significant amount of power consumption. The reason for the large power consumption is that such an implementation generally requires a large bias current in order to discharge parasitic capacitance on the pixel output signal line as soon as possible, and in order to have a large transconductance of the pixel output transistor as a source follower.
In addition, in a large signal response time, the settling time (t settle ) And bias current (I) bias ) And parasitic capacitance (C) para ) Proportional (t) settle ∝C para /I bias ). On the other hand, in the small signal response time, the settling time (t settle ) And g is equal to m -1 Proportional to parasitic capacitance (t settle ∝C para /g m ) Wherein g m Is the transconductance of the pixel output transistor. In addition, g m And bias current (I) bias ) Is proportional to the square root of (c). For example, the larger the bias current, the shorter the settling time, and then the larger the power consumption, even if the settling time is reduced by feeding the bias current to the signal output line of the pixelAs well as the same. Thus, settling time and power consumption are in a trade-off relationship. In this regard, several techniques have been proposed to mitigate this tradeoff between power consumption and settling time by providing a readout circuit for the pixel with one or more additional circuits that may temporarily increase the bias current.
Among the CCD imaging sensor and the CMOS imaging sensor, the CMOS imaging sensor is convenient because the CMOS imaging sensor is easy to integrate peripheral CMOS circuits at the same time, and various types of image processing functions can be integrated into a single chip. However, the CMOS imaging sensor generates a larger fixed pattern noise (fixed pattern noise, FPN) and thermal noise than the CCD imaging sensor due to variations in the drive transistor elements. In particular, CMOS imaging sensors can generate fixed pattern noise (fixed pattern noise, FPN) due to variations in the threshold of MOSFETs used in the pixel cell circuits. The change in bias current may increase the value of FPN. That is, the method of providing the feedback current to the output signal line of the pixel through one or more additional feedback circuits may have serious side effects, i.e., the signal-to-noise ratio of the imager may be lowered due to the larger FPN.
Two examples are listed below to illustrate a method of providing feedback current to an output signal line of a pixel through one or more additional feedback circuits.
According to japanese laid-open patent publication No. 2011-234243 (document 1), a high-speed pixel readout circuit can be realized by adding a source follower transistor, a capacitor, a reference current source, and a current mirror element (as shown in fig. 10). The high-speed pixel readout circuit in document 1 can temporarily increase the pixel bias current during the fall of the pixel output voltage.
According to U.S. Pat. No. 9,729,807 B2 (document 2), a high-speed pixel readout circuit can be realized by adding an additional feedback circuit including one capacitor, two current mirrors, and one voltage source (as shown in fig. 11), which can reduce the settling time of the imaging sensor circuit. The high-speed pixel readout circuit in document 2 can detect a transition current of a capacitance connected between a pixel output signal line and a voltage source to detect a rate of drop of a voltage on the pixel output signal line. The detected transition current is fed back to the pixel output signal line through two current mirrors. The current fed back to the pixel output signal line increases the bias current of the pixel output signal line.
However, the high-speed pixel readout circuit in document 1 has drawbacks in that the high-speed pixel readout circuit increases power consumption, die size, and fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor device. The high-speed pixel readout circuit in document 1 requires an additional current source and a capacitance of a large capacitance value that cannot be reduced. Thus, when the additional current source is used in an imaging sensor circuit having an irreducible large number of columns, the current variation from the additional current source will cause the FPN to become large. That is, since the output of the current mirror element is directly connected (not ac coupled) to the pixel output signal line, a change in the pixel output signal line voltage will change the output current of the current mirror element, which may result in an increase in the FPN of the imaging sensor device. Further, since the output of the current mirror element is directly connected to the pixel output signal line, a change in the mirror ratio of the current mirror element fluctuates the pixel bias current and results in a larger FPN. Furthermore, adding an additional current source that is substantially normally open will result in a significant increase in power consumption of the imaging sensor circuit.
As in document 1, the high-speed pixel readout circuit in document 2 can also increase the value of FPN. This is because the high-speed pixel readout circuit includes two sets of current mirror elements, and the outputs of the two current mirror elements are directly connected to the pixel output signal line. The mirror ratio of the two current mirrors may vary with variations in the manufacturing process and more importantly with variations in the DC voltage level on the pixel output signal line. That is, since the outputs of the two current mirror elements are directly connected to the pixel output signal line, a change in the pixel output signal line voltage will change the output current of the current mirror element. Further, since the outputs of the two current mirror elements are directly connected to the pixel output signal line, a variation in the mirror ratio will cause a fluctuation in the pixel bias current, resulting in an increase in FPN. The increase in power consumption of the high-speed pixel readout circuit in document 2 brings another problem in that the voltage source includes an operational amplifier to operate at a large bandwidth which cannot be reduced. Therefore, the high-speed pixel readout circuit in document 2 will require a not small bias current. The die size occupied by the voltage source circuit and the capacitor can also present problems.
Disclosure of Invention
In view of the above challenges, various embodiments of the present application are directed to an imaging sensor circuit and a driving method thereof, which can reduce settling time of an imaging sensor pixel output.
In a first aspect, the present application provides an imaging sensor circuit comprising:
and a reading unit configured to read data of a pixel, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line.
And the feedback unit is used for feeding back the boost current to the output line, wherein the feedback unit comprises a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch and a current mirror element.
Wherein the boost current is generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, the boost current being used to discharge the parasitic capacitance.
As described above, the conventional method of providing the feedback current to the output signal line of the pixel through one or more additional feedback circuits may have serious side effects in that data obtained from the pixel may be strongly disturbed by the large FPN.
Part of the fixed pattern noise (fixed pattern noise, FPN) may be caused by variations in the manufacturing process of the transistor used as a source follower. On the other hand, the current mirror ratio of the current mirror element 7 may also vary due to variations in the manufacturing process. In addition, in addition to the change in the current mirror ratio voltage or the like of the current mirror element, the change in the output current of the current mirror element may also be caused by the voltage dependence of the output voltage of the current mirror element. Since the voltage dependence itself may be quite large and the variation of the voltage dependence may also be quite large, the value of FPN may be relatively large when feeding back the DC component of the output current of the current mirror element. Further, since the output voltage of the current mirror element may significantly depend on the output voltage characteristics of the pixel, a change in the pixel threshold value may affect the output voltage of the current mirror element. Accordingly, when the DC component of the output current of the current mirror element is fed back to the output pixel signal line, the value of FPN can be larger. Therefore, the feedback unit in the imaging sensor circuit according to the embodiment of the present application needs not to feedback any Direct Current (DC) component of the feedback current back to the pixel output signal line.
The imaging sensor circuit according to the first aspect of the present application may include a feedback unit of a simple structure including two inverters, one current mirror, and three capacitors. The capacitance values of these three capacitors may be much smaller than those of the capacitors of the conventional art. Of the two inverters in the feedback unit, the input terminal of the inverter on the input side of the feedback unit is connected to the pixel output signal line through a capacitor. Accordingly, a feedback unit in the imaging sensor circuit may provide a pixel output signal line without a Direct Current (DC) component. The imaging sensor circuit according to the first aspect of the present application can ensure that the feedback current generated by the feedback unit does not increase the value of the fixed pattern noise (fixed pattern noise, FPN) due to variations in the transistors for the source follower gates that occur at the time of manufacture. In addition, since the capacitance values of the three capacitors can be much smaller than those of the capacitors in the conventional art, the imaging sensor circuit according to the embodiment of the present application can save power consumption as compared with the conventional art. Furthermore, the die size of the two inverters may also be much smaller than in the conventional art.
In a possible implementation manner of the first aspect, the input terminal of the first inverter may be connected to one terminal of the first capacitor, one terminal of the second capacitor and one terminal of the first switch, and the output terminal of the first inverter may be connected to the other terminal of the second capacitor, the other terminal of the first switch and the input terminal of the second inverter.
Wherein the input of the second inverter may be connected to one terminal of the third capacitor and one terminal of the second switch, and the output of the second inverter may be connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input of the current mirror element.
Wherein an output of the current mirror element may be connected to the output line and to the other terminal of the first capacitor.
In a possible implementation manner of the first aspect, the imaging sensor circuit may be disposed in pixels located in a specific row and a specific column in a pixel array, wherein an output terminal of the pixel array may be connected to an analog-to-digital convertor (ADC) array, and the feedback unit further includes a third switch, one terminal of which is connected to a ground terminal, and the other terminal of which may be connected to the one terminal of the first capacitor and the input terminal of the first inverter.
According to this implementation, the third switch may be turned on in response to the ADC array generating pixel output signals; a low level voltage may be applied to the input terminal of the first inverter; the first inverter may generate a high level voltage as an output and the second inverter may correspondingly generate a low level voltage as an output. That is, in response to an analog-to-digital convertor (ADC) array generating pixel array output signals, the two inverters in the feedback unit may be turned on. Thus, the imaging sensor circuit may save power consumption after the ADC array generates the pixel array output signal.
In a possible implementation manner of the first aspect, the reading unit may further include a photodetection element for temporarily storing charges converted from incident light, and a transfer gate for transferring the charges stored in the photodetection element to a floating diffusion (Floating Diffusion, FD) node in response to a transfer signal (TX).
Wherein the boost current may be generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, may include:
In response to the transfer signal (TX), the first switch and the second switch may be turned off so that the transfer gate can transfer charges stored in the photodetecting element to the FD node.
The first capacitance may be adjusted according to the voltage (V sig ) A current generated by a voltage difference with a threshold level of the first inverter propagates from the one terminal of the first capacitor to the input of the current mirror element.
The current mirror element may generate a current that is determined based on a current ratio of the current mirror element and a current propagated to the input of the current mirror element.
In a possible implementation manner of the first aspect, the reading unit may further include a select gate connected between the FD node and the output line.
Wherein a selection Signal (SEL) may be fed to the selection gate, which may enable the selection gate to select a row at a particular column in the pixel array as a particular row.
Wherein the current mirror element may be configured to: feeding back the current determined based on the current ratio of the current mirror element and a current propagated to the input terminal of the current mirror element to the output line, the current fed back to the output line can be used as a current for causing the parasitic capacitance to discharge the charge stored in the parasitic capacitance.
In a possible implementation manner of the first aspect, the reading unit may further include a reset gate for resetting a voltage level of the floating diffusion (Floating Diffusion, FD) node, and the reset gate may be connected between a supply voltage line and the FD node. According to the implementation, inAfter feeding the select gate with a select Signal (SEL) and before feeding the transfer gate with a transfer signal (TX), the reset gate is fed with a Reset Signal (RST) so that the FD node is pulled up to a supply voltage (V DD )。
According to the first aspect, due to cooperation among the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, a Direct Current (DC) component may not be fed back to the output line, so that the boost current may reduce the settling time of the imaging sensor circuit without increasing the fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor circuit.
In a second aspect, the present application may provide a method of driving an imaging sensor circuit using a driving circuit in a pixel array, wherein the imaging sensor circuit may include a reading unit and a feedback unit.
Wherein the reading unit may include a photodetection element for temporarily storing charges converted from incident light, a select gate, a transfer gate, an output line of a pixel, and a parasitic capacitance associated with the output line.
The feedback unit may include a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element.
Wherein the method may comprise the steps of:
a select Signal (SEL) is fed to the select gate, wherein the select Signal (SEL) enables the select gate to select a row at a particular column in the pixel array as a particular row.
A transfer signal (TX) is fed to the transfer gate, wherein the transfer signal (TX) enables the transfer gate to transfer charge stored in the photodetecting element to a floating diffusion (Floating Diffusion, FD) node.
And generating boost current through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch and the current mirror element, wherein the boost current is used for discharging the parasitic capacitor.
A current determined based on a current ratio of the current mirror element and a current propagated to an input terminal of the current mirror element is fed back to the output line, and the current fed back to the output line is used as a current for causing the parasitic capacitance to discharge the charge stored in the parasitic capacitance.
The method according to the second aspect of the application may be performed by an imaging sensor circuit according to an embodiment of the application. The imaging sensor circuit may include a feedback unit of a simple structure including two inverters, one current mirror, and three capacitors. The capacitance values of these three capacitors may be much smaller than those of the capacitors of the conventional art. Of the two inverters in the feedback unit, the input terminal of the inverter on the input side of the feedback unit is connected to the pixel output signal line through a capacitor. Accordingly, a feedback unit in the imaging sensor circuit may provide a pixel output signal line without a Direct Current (DC) component. According to the embodiment of the application, the method performed by using the imaging sensor circuit can ensure that the feedback current generated by the feedback unit does not increase the value of the fixed pattern noise (fixed pattern noise, FPN) due to the variation of the transistor for the source follower gate during manufacturing. In addition, since the capacitance values of the three capacitors can be much smaller than those of the capacitors in the conventional art, the imaging sensor circuit according to the embodiment of the present application can save power consumption as compared with the conventional art. Furthermore, the die size of the two inverters may also be much smaller than in the conventional art.
In a possible implementation manner of the second aspect, the input end of the first inverter may be connected to one terminal of the first capacitor, one terminal of the second capacitor and one terminal of the first switch, and the output end of the first inverter may be connected to the other terminal of the second capacitor, the other terminal of the first switch and the input end of the second inverter.
Wherein the input of the second inverter may be connected to one terminal of the third capacitor and one terminal of the second switch, and the output of the second inverter may be connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input of the current mirror element.
Wherein an output of the current mirror element may be connected to the output line and to the other terminal of the first capacitor.
In a possible implementation manner of the second aspect, the reading unit may further include a reset gate for resetting a voltage level of the floating diffusion (Floating Diffusion, FD) node, the reset gate may be connected between a supply voltage line and the FD node, wherein the method may further include:
After feeding the select Signal (SEL) to the select gate and before feeding the transfer signal (TX) to the transfer gate, a Reset Signal (RST) is fed to the reset gate so that the FD node is pulled up to a supply voltage (V DD )。
In a possible implementation manner of the second aspect, an output terminal of the pixel array may be connected to an analog-to-digital convertor (ADC) array, the feedback unit may further include a third switch, one terminal of the third switch may be connected to a ground terminal, and another terminal of the third switch may be connected to the one terminal of the first capacitor and the input terminal of the first inverter, and the method may further include:
the third switch is turned on in response to the ADC array generating pixel output signals.
A low level voltage is applied to the input of the first inverter.
And generating a high-level voltage as the output of the first inverter and correspondingly generating a low-level voltage as the output of the second inverter, so that the power consumption of the ADC array after generating pixel output signals is saved.
The two inverters in the feedback unit may be turned on in response to an analog-to-digital convertor (ADC) array generating a pixel array output signal. Thus, the method according to this implementation of the second aspect may save power consumption after the ADC array generates the pixel array output signal.
According to the second aspect, due to cooperation among the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, a Direct Current (DC) component may not be fed back to the output line, so that the boost current may reduce the settling time of the imaging sensor circuit without increasing the fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor circuit.
Drawings
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.
FIG. 1 shows a block diagram of an exemplary configuration of an imaging sensor circuit according to an embodiment of the present application;
FIG. 2 shows a block diagram of an exemplary configuration of a pixel array according to an embodiment of the application;
fig. 3 shows an exemplary configuration of a reading unit of an imaging sensor circuit according to an embodiment of the present application;
fig. 4 shows an example of a timing chart of output voltages at a plurality of nodes of a reading unit of an imaging sensor circuit according to an embodiment of the present application;
FIG. 5 shows a circuit diagram of an exemplary configuration of an imaging sensor circuit according to one embodiment of the application;
FIG. 6 illustrates an example of a timing diagram of output voltages at a plurality of nodes of an imaging sensor circuit according to one embodiment of the application;
FIG. 7 shows a circuit diagram of another exemplary configuration of an imaging sensor circuit in accordance with another embodiment of the application;
FIG. 8 illustrates an example of a timing diagram of output voltages at a plurality of nodes of an imaging sensor circuit according to another embodiment of the application;
fig. 9 shows a circuit diagram of an inverter element used in an imaging sensor circuit according to an embodiment of the present application;
fig. 10 shows a circuit diagram of an imaging sensor circuit in the conventional art;
fig. 11 shows a circuit diagram of an imaging sensor circuit in the conventional art.
In the following, like reference numerals refer to like or at least functionally equivalent features unless explicitly stated otherwise.
Detailed Description
In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific aspects in which embodiments of the application may be practiced. It is to be understood that embodiments of the application may be used in other aspects and may include structural or logical changes not depicted in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.
For example, it should be understood that the disclosure relating to the described method also applies equally to the corresponding device or system for performing the method, and vice versa. For example, if a particular apparatus is described based on one or more elements (e.g., functional elements), the corresponding method may include one step to perform the function of the one or more elements (e.g., one step to perform the function of the one or more elements, or multiple steps to perform the function of one or more elements, respectively, of the plurality of elements), even if the one or more elements are not explicitly described or shown in the figures. On the other hand, for example, if one or more specific method steps are described, the corresponding apparatus may include one or more units (e.g., functional units) to perform the described one or more method steps (e.g., one unit performs one or more steps, or a plurality of units performs one or more of the steps, respectively), even if the one or more units are not explicitly described or shown in the figures. Furthermore, it should be understood that features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless explicitly stated otherwise.
Fig. 1 shows a block diagram of an exemplary configuration of an imaging sensor circuit according to an embodiment of the present application. In fig. 1, the imaging sensor device may include a pixel array 1, an analog-to-digital convertor (ADC) array 2, a digital signal level transmission circuit 3, a comparison circuit 4, a counter 5, a row driver 6, and a ramp reference generator 7. The pixel array 1 may include a plurality of pixels arranged in a two-dimensional matrix form. Each of these pixels may convert incident light into an electrical signal, and the converted electrical signal may be output to the ADC 2 through a reading unit and a Voltage Output Line (VOL). Each ADC 2 can convert an analog signal into a digital signal by referring to the ramp voltage supplied by the ramp reference generator 7.
In the CMOS imaging sensor, the operation of the pixels can be controlled row by a pulse (for example, a reset pulse (reset signal) (RST), a transfer pulse (transfer signal) Tx, a row selection pulse (row selection Signal) (SEL)) supplied by a row driver serving as a circuit for generating a row control pulse. The configuration of the imaging sensor device may be various types of configurations, for example, a configuration in which amplification of pixel outputs and suppression of fixed pattern noise (fixed pattern noise, FPN) are arranged in parallel in columns, a configuration in which an AD conversion circuit is provided at the final stage, a configuration in which AD conversion is performed in parallel in columns, a configuration in which a column parallel circuit is provided above and below a pixel array, a system-on-chip type configuration (typically a sensor used in a cellular phone camera) in which AD converted digital data is output after processing a camera signal, or a configuration in which pixel outputs are output as analog signals without performing AD conversion (typically a sensor used in a digital single lens reflex camera).
Fig. 2 shows a block diagram of an exemplary configuration of a pixel array according to an embodiment of the present application. As shown in fig. 1 and 2, the digital signal level transmission circuit 3 sequentially selects one column from a predetermined number of columns disposed in the pixel array from left to right in the horizontal direction to determine a column to be scanned. More specifically, the digital signal horizontal transfer circuit 3 turns on a predetermined number of column selection switches in order from left to right in the horizontal direction, and then the row driver 6 turns on the predetermined number of column selection switches in the order from top to bottomThe next sequence sequentially selects the rows to be scanned in the selected columns. The row driver 6 feeds a select Signal (SEL) to the select gates M in the pixels arranged in the selected row 2 。
Fig. 3 shows an exemplary configuration of a reading unit of the imaging sensor circuit according to the embodiment of the present application. In fig. 3, a reading unit for reading pixel data (e.g., luminance data and chrominance data) may include a power supply line 1, a pixel output signal line 2 of a pixel, a photodetecting element D 1 Transmission grid M 3 Reset grid M 4 Select gate M 2 Source follower M 1 And a parasitic capacitance C associated with the pixel output signal line 2 1 . Photodetection element D 1 May be a Photodiode (PD). Photodetection element D 1 It is possible to detect incident light, convert the incident light into electric charges, and store the converted electric charges in potential wells inside thereof. Transmission gate M 3 A transfer signal Tx may be received from the row driver 6 and the stored charge may be transferred to a floating diffusion (Floating Diffusion, FD) node in response to the transfer signal Tx. Reset gate M 4 A Reset Signal (RST) may be received from the row driver 6, and the level of the FD node may be reset in response to the Reset Signal (RST). Select gate M 2 A row selection Signal (SEL) may be received from the row driver 6 and, in response to the row selection Signal (SEL), a row at a specific column in the pixel array 1 is selected as a specific row to be scanned by the reading unit. Source follower M 1 The gate voltage of the pixel output signal line 2 can be buffered. The current source may be a source follower M 1 Providing a bias current.
As described above, the CMOS imaging sensor is convenient in comparison with the CCD imaging sensor because the CMOS imaging sensor is easy to integrate peripheral CMOS circuits at the same time, and various types of image processing functions can be integrated into a single chip. However, the CMOS imaging sensor generates a larger fixed pattern noise (fixed pattern noise, FPN) and thermal noise than the CCD imaging sensor due to variations in the drive transistor elements. In particular, CMOS imaging sensors can generate fixed pattern noise (fixed pattern noise, FPN) due to variations in the threshold of MOSFETs used in the pixel cell circuits.
In a CMOS imaging sensor, at the beginning of an imaging period, the gate M is reset 4 Turned on by RST signal to turn on photodetector D 1 Charging to an initial voltage. The potential of the floating diffusion (Floating Diffusion, FD) node is higher than the power supply voltage (V) DD ) Low difference is reset gate M 4 Is set to a threshold value of (2). When the photoelectric detection element D 1 When irradiated by light, the photocurrent flows through the photodetection element D 1 And discharges charges, causing the potential of the floating diffusion (Floating Diffusion, FD) node to drop according to the light intensity. Source follower M 1 Receives the potential of the floating diffusion (Floating Diffusion, FD) node and provides a row select Signal (SEL) to select gate M 2 So that the image signal is transmitted to the pixel output signal line. The main problem of the read unit is that when the source follower M 1 When there is a threshold change, the threshold change affects the signal output, which is a factor causing FPN. Even source follower M 1 The transistors used in are integrated on the same single chip, source follower M 1 The threshold value of (2) is also inevitably changed due to variations occurring at the time of manufacture.
The fixed pattern noise (fixed pattern noise, FPN) may include fixed pattern noise (which occurs randomly in space, the noise amplitude does not fluctuate with time) generated by the characteristic variation of the transistors in the pixels, fixed pattern noise (which occurs randomly in space, the noise amplitude is proportional to the integration time) generated by the dark current variation of each pixel, and fixed pattern noise (which occurs in the form of vertical stripes, the noise amplitude does not fluctuate with time) caused by the variation of the signal processing circuit provided for each column.
The operation of the feedback unit is described below with reference to a timing chart. Fig. 4 shows an example of a timing chart of output voltages at a plurality of nodes of a reading unit of an imaging sensor circuit according to an embodiment of the present application. In fig. 4, at time t 1 At this point, a select Signal (SEL) is fed from the row driver 6 to the select gate M 2 . A select Signal (SEL) causes select gate M to 2 Can be selected in a pixel arrayThe row at a particular column is the particular row. At time t 2 At the point of selecting gate M 2 After feeding the selection Signal (SEL) and after feeding the transfer gate M 3 Before feeding the transmission signal (TX), the reset gate M is fed 4 A Reset Signal (RST) is fed so that the FD node is pulled up to a power supply voltage (V DD ). At time t 3 Feeding a transmission signal (TX) to a transmission gate M 3 . A transmission signal (TX) causes a transmission gate M 3 The charge stored in the photodetecting element can be transferred to the floating diffusion (Floating Diffusion, FD) node. In the embodiment of the present application, when the charge is transferred to the FD node, the potential at the FD node is lowered because the charge is considered to be an electron. The pixel output signal line 2 has a parasitic capacitance C of a specific value 1 . Therefore, its falling voltage slew rate is subject to the current source I 1 Is set to (I) bias ) Parasitic capacitance C 1 And a source follower M 1 Transconductance (g) m ) Is limited by the number of (a).
The total duration of the settling time of the pixel output signal line 2 may include two parts, one part being a large signal range and the other part being a small signal range. For a large signal range, the settling time (t settle ) Can be controlled by a bias current (I bias ) And parasitic capacitance C 1 The determination is made according to the following equation:
t settle ＝k×C 1 /I bias (1)
wherein t is settle Indicating the settling time of the pixel output signal line 2, I bias Representing the current source I 1 And k represents a constant. For the small signal range, the settling time (t settle ) G through a source follower transistor m And C 1 The determination is made according to the following equation:
t settle ＝C 1 /g m (2)
due to g m And 1/I bias Is proportional, so that the settling time (t settle ) Are proportional to each other. For example, bias current (I bias ) The greater the settling time (t settle ) The shorter. Thus, for large and small signal ranges, the settling time (t settle ) And power consumption are in a trade-off relationship. The invention can improve the settling time (t) without increasing the fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor circuit settle ) And power consumption.
As described above, the imaging sensor circuit according to the embodiment of the present application can reduce the settling time of the pixel source follower circuit output by feeding the boost current to the pixel output without increasing the fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor circuit. The increase in power consumption of the additional feedback circuit is smaller than that of the conventional art. These advantages result from the adaptation of the capacitively coupled simple circuit and its power down function.
Fig. 5 shows a circuit diagram of an exemplary configuration of an imaging sensor circuit according to an embodiment of the present application. In fig. 5, an imaging sensor circuit according to an embodiment of the present application may be disposed in pixels located at a specific row and a specific column in a pixel array. The imaging sensor circuit may include a reading unit for reading the pixel data and a feedback unit for feeding back the boosting current to the pixel output signal line. The reading unit may include a power supply line 1, a pixel output signal line 2 of the pixel, a photodetecting element D 1 Transmission grid M 3 Reset grid M 4 Select gate M 2 Source follower M 1 And a parasitic capacitance C associated with the pixel output signal line 2 1 . The feedback unit comprises a first capacitor C 2 A second capacitor C 3 Third capacitor C 4 A first inverter 5, a second inverter 6, a first switch 3, a second switch 4 and a current mirror element 7.
As shown in fig. 5, the input terminal of the first inverter 5 is connected to a first capacitor C 2 A second capacitor C 3 And one terminal of the first switch 3. The output of the first inverter 5 is connected to a second capacitor C 3 Another terminal of the first switch 3, another terminal of the second switch 6, and an input of the second inverterAnd (3) an end. The input of the second inverter 6 is connected to a third capacitor C 4 One terminal of the second switch 4, and an output of the first inverter 5. The output terminal of the second inverter 6 is connected to a third capacitor C 4 The other terminal of the second switch 4 and the input of the current mirror element 7. The output terminal of the current mirror element 7 is connected to the pixel output signal line 2 and the first capacitor C 2 Is provided.
The operation of the imaging sensor circuit according to one embodiment of the present application is described below with reference to timing charts. Fig. 6 shows an example of a timing diagram of output voltages at a plurality of nodes of an imaging sensor circuit according to one embodiment of the application. As shown in fig. 6, at time t 1 Where the row driver 6 in fig. 1 is directed to the select gate M 2 A feed select Signal (SEL). A select Signal (SEL) causes select gate M to 2 A row at a particular column in the pixel array can be selected as a particular row. At time t 2 At the point of selecting gate M 2 After feeding the selection Signal (SEL) and after feeding the transfer gate M 3 Before feeding the transmission signal (TX), the reset gate M is fed 4 A Reset Signal (RST) is fed such that the voltage level at the FD node is pulled up to a supply voltage (V DD ). As shown in fig. 6, since the voltage level at the FD node is pulled up to the power supply voltage (V DD ) The potential on the pixel output signal line 2 is pulled up to V reset 。
In FIG. 4, signal P switch May be when pulse P switch The pulse that turns on the first switch 3 and the second switch 4 when the voltage level of (c) is high. On the other hand, when pulse P switch When the voltage level of (2) is low, pulse P switch The first switch 3 and the second switch 4 are turned off. As described above, at time t 1 At this point, a row select Signal (SEL) may be fed to select gate M 2 So that the gate M is selected 2 Activated so that pixels located in a particular row in the pixel array can be ready to be scanned. In other words, select gate M 2 The photodetecting element D temporarily stored in the pixel can be allowed 1 The pixel data (e.g., luminance data and chrominance data) in (a) is ready to be read out. At time t 2 At this point, a Reset Signal (RST) may be fed to the reset gate M 4 So that the gate M is reset 4 Activated so that the voltage level at the FD node can be pulled up to the supply voltage (V DD ). The voltage level at the pixel output signal line 2 can be brought to be equal to the voltage level (V DD –V gs1 ) V of (2) reset 。V gs1 Is equal to the value of the source follower M 1 Is provided, the voltage difference between the gate terminal and the source terminal.
At the same time at time t 2 At pulse P switch May rise to a high level such that the first switch 3 and the second switch 4 are turned on. When the input terminals and the output terminals of the first inverter 5 and the second inverter 6 are short-circuited by the first switch 3 and the second switch 4 with the negative feedback effect, the output terminals of the first inverter 5 and the second inverter 6 can be stabilized near the threshold levels of the first inverter 5 and the second inverter 6. In other words, when the first switch 3 and the second switch 4 are turned on, the input terminals and the output terminals of the first inverter element 5 and the second inverter element 6 may be short-circuited, and the first inverter element 5 and the second inverter element 6 may function as voltage followers but not as inverting amplifier circuits. In addition, when the first switch 3 and the second switch 4 are turned on, the second capacitor C 3 And a third capacitor C 4 Can discharge without stored charge. A second capacitor C connected between the input and output terminals of the first and second inverter elements 5, 6 when the first and second switches 3, 4 are turned off 3 And a third capacitor C 4 The input current of the inverter can be outputted from the output terminal as a negative feedback capacitor. The threshold level of the inverter is denoted herein as V inv . First capacitor C 2 By two voltages V inv And V reset Charging is performed. It should be noted that the AC operation in the present application refers to only the first capacitor C 2 The current obtained.
At time t 3 At this point, a transmission signal (Tx) may be fed to the transmission gate M 3 So that the photodetection element D 1 Can be stored in the photodetection element D 1 Is transferred to the FD node. The voltage level of the pixel output signal line 2 canTo lower to a lower level (V sig ). At time t 3 Here, a feedback unit in the imaging sensor circuit may be used to: a part of the current on the pixel output signal line 2 is used as the input current of the feedback unit and passes through the first capacitor C 2 A second capacitor C 3 Third capacitor C 4 The first inverter 5, the second inverter 6, the first switch 3, the second switch 4, and the current mirror element 7 generate a boost current as a feedback current. More specifically, at time t 3 At this point, in response to the transmission signal (TX), the first switch 3 and the second switch 4 may be turned off such that the gate M is transmitted 3 Can be stored in the photodetection element D 1 Is transferred to the FD node. The first capacitor C can be 2 According to the voltage (V) on the pixel output signal line 2 sig ) And the threshold level (V of the first inverter 5 inv ) The current generated by the voltage difference between the capacitors is transmitted from the first capacitor C 2 To the input of the current mirror element 7. The current mirror element 7 may generate a current that is determined based on the current ratio of the current mirror element 7 and the current propagated to the input of the current mirror element 7.
For example, as shown in fig. 5 and 6, when the transmission signal (TX) enables the transmission gate M 3 Will be stored in the photodetection element D 1 When the charges in (a) are transferred to the FD node, a signal (P switch ) May drop to a lower level and may turn off the first switch 3 and the second switch 4. A second capacitor C connected between the input and output terminals of the first and second inverters 5 and 6 when the first and second switches 3 and 4 are turned off 3 And a third capacitor C 4 Can be used as a negative feedback capacitor, and can output the input current of the inverter from the output terminal. Due to the first capacitance C 2 The voltage level of one terminal of (2) can be reduced to a lower level, and the first capacitance C 2 The voltage level of the other terminal of (2) can be kept as V with feedback effect inv The charging current can be based on the voltage difference (V reset –V sig ) Through the first capacitor C 2 . Through the first capacitor C 2 The current of (c) is represented as I in FIG. 6 C1 . Flow through the firstA capacitor C 2 The current of (2) can also flow through the second capacitor C 3 And a third capacitor C 4 And may propagate to the input of the current mirror element 7. The current mirror element 7 may generate a current, the value of which is determined based on the current ratio of the current mirror element 7 and the input current of the current mirror element 7. The output current of the current mirror element 7 can be used as parasitic capacitance C 1 Is added to the discharge current. Therefore, the falling voltage slew rate can be increased, and the settling time of the pixel output can be reduced.
In an embodiment of the application, the current mirror element 7 may be used to: the current determined based on the current ratio of the current mirror element 7 and the current propagated to the input terminal of the current mirror element 7 are fed back to the pixel output signal line 2. The current fed back to the output line can be used as a feedback signal for the parasitic capacitance C 1 Releasing the storage in parasitic capacitance C 1 A current of the electric charges in the capacitor. The feedback current fed back to the pixel output signal line 2 can be fed back by the first capacitor C only 2 Is composed of the charging alternating current (alternating current, AC), and therefore, no Direct Current (DC) component is fed back to the pixel output signal line 2.
The following describes that the feedback unit in the imaging sensor circuit of the present application uses not only the second capacitor C 3 Also using a third capacitor C 4 To generate a cause of a feedback current fed back to the pixel output signal line 2. That is, since current imaging sensors can mostly process signals represented by negative charges, the stronger the incident light, the greater the amount of negative charges. Since negative charge is stored in the capacitor and output as a specific voltage, the polarity of the pixel output may become negative. Therefore, the imaging sensor according to the embodiment of the present application needs to use two inverters to make the polarity of the feedback current negative (sink the feedback current).
The reason why the feedback unit in the imaging sensor circuit of the present application does not feed back any Direct Current (DC) component of the feedback current to the pixel output signal line 2 is described below. That is, fixed pattern noise (fixed pattern noise, FPN) may be generated by the gate M 1 In which the gate is formed by a variation factor caused by a variation in the transistor used in the manufacturePole M 1 Can be used as a source follower. On the other hand, the current mirror ratio of the current mirror element 7 may be changed according to a change factor caused by a change in manufacturing. In addition, in addition to the change in the current mirror ratio or the like, the change in the output current of the current mirror element 7 may also be caused by the voltage dependence of the output voltage of the current mirror element 7. Since the voltage dependence itself can be quite large and the variation of the voltage dependence at the time of manufacture can also be quite large, the value of FPN can be large when feeding back the DC component of the output current of the current mirror element 7. Further, since the output current of the current mirror element 7 may significantly depend on the output voltage characteristics of the pixel, a change in the threshold value of the source follower transistor may affect the output current of the current mirror element 7. Therefore, when the DC component of the output current of the current mirror element 7 is fed back to the output pixel signal line 2, the value of FPN can be larger. Therefore, the feedback unit in the imaging sensor circuit according to the embodiment of the present application needs not to feedback any Direct Current (DC) component of the feedback current back to the pixel output signal line 2.
Therefore, according to the feedback unit in the imaging sensor circuit of the embodiment of the present application, due to cooperation among the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, and the second switch, a Direct Current (DC) component may not be fed back to the pixel output signal line 2, so that the boost current may reduce the settling time of the imaging sensor circuit without increasing the fixed pattern noise (fixed pattern noise, FPN) of the imaging sensor circuit.
In summary, according to a first aspect, the present application may provide an imaging sensor circuit provided in pixels located at a specific row and a specific column in a pixel array. The imaging sensor circuit may include a reading unit for reading data of a pixel, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line; and the feedback unit is used for feeding back the boost current to the output line, wherein the feedback unit comprises a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch and a current mirror element. In the imaging sensor circuit, a part of current on an output line is used as an input current of a feedback unit, a boosting current can be generated through a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch and a current mirror element, and the boosting current can be used for discharging parasitic capacitance.
The imaging sensor circuit according to the embodiment of the present application may include a feedback unit of a simple structure including two inverters, one current mirror, and three capacitors. The capacitance values of these three capacitors may be much smaller than those of the capacitors of the conventional art. Of the two inverters in the feedback unit, the input terminal of the inverter on the input side of the feedback unit is connected to the pixel output signal line through a capacitor. Accordingly, a feedback unit in the imaging sensor circuit may provide a pixel output signal line without a Direct Current (DC) component. The imaging sensor circuit according to the embodiment of the application can ensure that the feedback current generated by the feedback unit does not increase the value of fixed pattern noise (fixed pattern noise, FPN) due to the variation of the transistor for the source follower gate during manufacture. In addition, since the capacitance values of the three capacitors can be much smaller than those of the capacitors in the conventional art, the imaging sensor circuit according to the embodiment of the present application can save power consumption as compared with the conventional art. Furthermore, the die size of the two inverters may also be much smaller than in the conventional art.
Fig. 7 shows a circuit diagram of another exemplary configuration of an imaging sensor circuit according to another embodiment of the present application. The difference between fig. 7 and fig. 5 is whether the feedback unit in the imaging sensor circuit includes the third switch 8. As shown in fig. 1 to 3 and 7, the output of the pixel array 1 may be connected to an analog-to-digital convertor (ADC) array 2. The feedback unit may further comprise a third switch 8, one terminal of the third switch 8 may be connected to the ground terminal, and the other terminal of the third switch 8 may be connected to one terminal of the first capacitor and the input of the first inverter 5.
Fig. 8 shows an example of a timing chart of output voltages at a plurality of nodes of an imaging sensor circuit according to another embodiment of the present application. The operation of the imaging sensor circuit according to another embodiment of the present application will be described below. Time t in fig. 8 1 To time t 3 The operation performed is the same as time t in fig. 6 1 To time t 3 The operations performed are the same. Accordingly, details are not described herein. With respect to time t in FIG. 8 1 To time t 3 For details of the operation of (a), please refer to time t in fig. 6 1 To time t 3 Is described in detail below. As shown in fig. 8, at time t 4 The third switch 8 may be turned on in response to the ADC array generating the pixel output signal; a low level voltage may be applied to the input terminal of the first inverter 5; the first inverter 5 may generate a high level voltage as an output, and the second inverter 6 may correspondingly generate a low level voltage as an output, thereby saving power consumption after the ADC array generates the pixel output signal.
For example, at time t 4 Analog-to-digital conversion of the pixel array output is completed. The signal P can be generated after the signal from the ADC off And may turn on the third switch 8. Since the input level of the first inverter 5 may drop to a lower level when the switch 8 is turned on, the output level of the first inverter 5 may rise to a higher level and the output level of the second inverter 6 may correspondingly drop to a lower level. These operations may shut off the power supply currents of the first inverter 5 and the second inverter 6, because only NMOS or PMOS in the first inverter 5 and the second inverter 6 may be turned on when their input level is high or low. Fig. 8 shows an example of an inverter composed of NMOS and PMOS, wherein the inverter may include a power line 1, an input terminal 2, and an output terminal 3.
According to this design of another embodiment of the application, the imaging sensor circuit may save power consumption after the ADC array generates the output signal of the pixel array.
In a second aspect, the present application may provide a method of driving an imaging sensor circuit in pixels disposed at a specific row and a specific column in a pixel array by a driving circuit in the pixel array. The imaging sensor circuit for the method may include a reading unit and a feedback unit. The reading unit may include a photodetection element for temporarily storing charges converted from incident light, a select gate, a transfer gate, an output line of a pixel, and a parasitic capacitance associated with the output line. The feedback unit may include a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element. The method may comprise the steps of:
s1201: a select Signal (SEL) is fed to the select gate, wherein the select Signal (SEL) enables the select gate to select a row at a particular column in the pixel array as a particular row.
S1203: a transfer signal (TX) is fed to the transfer gate, wherein the transfer signal (TX) enables the transfer gate to transfer charge stored in the photodetecting element to a floating diffusion (Floating Diffusion, FD) node.
S1204: and taking a part of current on the output line as input current of the feedback unit, generating boost current through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch and the current mirror element, wherein the boost current is used for discharging the parasitic capacitor.
S1205: a current determined based on a current ratio of the current mirror element and a current propagated to an input terminal of the current mirror element is fed back to the output line, and the current fed back to the output line is used as a current for causing the parasitic capacitance to discharge the charge stored in the parasitic capacitance.
The method according to an embodiment of the present application may be performed by an imaging sensor circuit according to an embodiment of the present application. The imaging sensor circuit may include a feedback unit of a simple structure including two inverters, one current mirror, and three capacitors. The capacitance values of these three capacitors may be much smaller than those of the capacitors of the conventional art. Of the two inverters in the feedback unit, the input terminal of the inverter on the input side of the feedback unit is connected to the pixel output signal line through a capacitor. Accordingly, a feedback unit in the imaging sensor circuit may provide a pixel output signal line without a Direct Current (DC) component. According to the embodiment of the application, the method performed by using the imaging sensor circuit can ensure that the feedback current generated by the feedback unit does not increase the value of the fixed pattern noise (fixed pattern noise, FPN) due to the variation of the transistor for the source follower gate during manufacturing. In addition, since the capacitance values of the three capacitors can be much smaller than those of the capacitors in the conventional art, the imaging sensor circuit according to the embodiment of the present application can save power consumption as compared with the conventional art. Furthermore, the die size of the two inverters may also be much smaller than in the conventional art.
In one possible implementation according to an embodiment of the present application, the read unit in the imaging sensor circuit for the method may further include a reset gate for resetting a voltage level of the floating diffusion (Floating Diffusion, FD) node, the reset gate may be connected between a supply voltage line and the FD node. The method may further comprise:
s1202: after feeding the select Signal (SEL) to the select gate and before feeding the transfer signal (TX) to the transfer gate, a Reset Signal (RST) is fed to the reset gate so that the FD node is pulled up to a supply voltage (V DD )。
In one possible implementation according to an embodiment of the application, the output of the pixel array may be connected to an analog-to-digital convertor (ADC) array. The feedback unit in the imaging sensor circuit for the method may further comprise a third switch. One terminal of the third switch may be connected to the ground terminal, and the other terminal of the third switch may be connected to one terminal of the first capacitor and the input terminal of the first inverter. The method may further comprise the steps of:
s1206: the third switch is turned on in response to the ADC array generating pixel output signals.
S1207: a low level voltage is applied to the input of the first inverter.
S1208: and generating a high-level voltage as the output of the first inverter and correspondingly generating a low-level voltage as the output of the second inverter, so that the power consumption of the ADC array after generating pixel output signals is saved.
According to this design of another embodiment of the application, the imaging sensor circuit for the method may save power consumption after the ADC array generates the output signal of the pixel array.
For further details regarding embodiments of the method, reference may be made to the description above regarding the corresponding operation of the imaging sensor circuit. These details are not described in detail herein.
The embodiments and functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a computer-readable medium or transmitted over a communications medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium (e.g., a data storage medium), or any communication medium that facilitates transmission of a computer program from one place to another according to a communication protocol or the like. In this manner, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementing the techniques described herein. The computer program product may include a computer-readable medium.
By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source via a coaxial cable, fiber optic cable, twisted pair, and digital subscriber line (digital subscriber line, DSL), or infrared, radio, and microwave wireless technologies, then the coaxial cable, fiber optic cable, twisted pair, and DSL, or infrared, radio, and microwave wireless technologies are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but rather refer to non-transitory tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital versatile disc (digital versatile disc, DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application, and thus it is intended that the application cover the modifications and variations of this application provided they come within the scope of protection defined by the appended claims and their equivalents.

Claims (10)

1. An imaging sensor circuit, comprising:
a reading unit configured to read data of a pixel, wherein the reading unit includes an output line of the pixel and a parasitic capacitance associated with the output line;
a feedback unit for feeding back a boost current to the output line, wherein the feedback unit includes a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch, and a current mirror element;
wherein the boost current is generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, the boost current being used to discharge the parasitic capacitance.
2. The imaging sensor circuit of claim 1, wherein an input of the first inverter is connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch, and an output of the first inverter is connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input of the second inverter;
Wherein the input of the second inverter is connected to one terminal of the third capacitor and one terminal of the second switch, and the output of the second inverter is connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input of the current mirror element;
wherein an output of the current mirror element is connected to the output line and to the other terminal of the first capacitor.
3. The imaging sensor circuit of claim 2, wherein the imaging sensor circuit is disposed in pixels located in a particular row and a particular column in a pixel array, wherein an output of the pixel array is connected to an analog-to-digital convertor (ADC) array, the feedback unit further comprising a third switch having one terminal connected to a ground terminal and another terminal connected to the one terminal of the first capacitor and the input of the first inverter.
4. The imaging sensor circuit according to any one of claims 1 to 3, wherein the reading unit further comprises a photodetection element for temporarily storing charges converted from incident light, and a transfer gate for transferring the charges stored in the photodetection element to a floating diffusion (Floating Diffusion, FD) node in response to a transfer signal (TX);
Wherein the boost current is generated by the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, comprising:
turning off the first switch and the second switch in response to the transmission signal (TX) so that the transmission gate can transmit the charge stored in the photodetection element to the FD node;
the first capacitor is controlled according to the voltage (V sig ) A current generated by a voltage difference between a threshold level of the first inverter propagates from the one terminal of the first capacitor to the input of the current mirror element;
the current mirror element generates a current that is determined based on a current ratio of the current mirror element and a current propagated to the input of the current mirror element.
5. The imaging sensor circuit of claim 4, wherein the read unit further comprises a select gate connected between the FD node and the output line;
wherein a selection Signal (SEL) is fed to the selection gate, the selection Signal (SEL) enabling the selection gate to select a row at a particular column in the pixel array as a particular row;
Wherein the current mirror element is configured to: the current determined based on the current ratio of the current mirror element and the current propagated to the input terminal of the current mirror element is fed back to the output line, and the current fed back to the output line is used as a current for causing the parasitic capacitance to discharge the charge stored in the parasitic capacitance.
6. The imaging sensor circuit according to any one of claims 4 and 5, wherein the read unit further comprises a reset gate for resetting a voltage level of the floating diffusion (Floating Diffusion, FD) node, the reset gate being connected between a supply voltage line and the FD node.
7. A method of driving an imaging sensor circuit using a driving circuit in a pixel array, the imaging sensor circuit comprising a reading unit and a feedback unit;
wherein the reading unit includes a photodetection element for temporarily storing charges converted from incident light, a select gate, a transfer gate, an output line of a pixel, and a parasitic capacitance associated with the output line;
the feedback unit comprises a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a first switch, a second switch and a current mirror element;
Wherein the method comprises the steps of:
feeding a select Signal (SEL) to the select gate, wherein the select Signal (SEL) enables the select gate to select a row at a particular column in the pixel array as a particular row;
feeding a transfer signal (TX) to the transfer gate, wherein the transfer signal (TX) enables the transfer gate to transfer charge stored in the photodetecting element to a floating diffusion (Floating Diffusion, FD) node;
generating a boost current through the first capacitor, the second capacitor, the third capacitor, the first inverter, the second inverter, the first switch, the second switch, and the current mirror element, the boost current for discharging the parasitic capacitor;
a current determined based on a current ratio of the current mirror element and a current propagated to an input terminal of the current mirror element is fed back to the output line, and the current fed back to the output line is used as a current for causing the parasitic capacitance to discharge the charge stored in the parasitic capacitance.
8. The method of claim 7, wherein the input of the first inverter is connected to one terminal of the first capacitor, one terminal of the second capacitor, and one terminal of the first switch, and the output of the first inverter is connected to the other terminal of the second capacitor, the other terminal of the first switch, and the input of the second inverter;
Wherein the input of the second inverter is connected to one terminal of the third capacitor and one terminal of the second switch, and the output of the second inverter is connected to the other terminal of the third capacitor, the other terminal of the second switch, and the input of the current mirror element;
wherein an output of the current mirror element is connected to the output line and to the other terminal of the first capacitor.
9. The method according to any one of claims 7 and 8, wherein the read unit further comprises a reset gate for resetting a voltage level of the floating diffusion (Floating Diffusion, FD) node, the reset gate being connected between a supply voltage line and the FD node, the method further comprising:
after feeding the select Signal (SEL) to the select gate and before feeding the transfer signal (TX) to the transfer gate, a Reset Signal (RST) is fed to the reset gate so that the FD node is pulled up to a supply voltage (V DD )。
10. The method of claim 7, wherein an output of the pixel array is connected to an analog-to-digital convertor (ADC) array, the feedback unit further comprising a third switch having one terminal connected to a ground terminal and another terminal connected to the one terminal of the first capacitor and the input of the first inverter, the method further comprising:
Turning on the third switch in response to the ADC array generating pixel output signals;
applying a low level voltage to the input of the first inverter;
and generating a high-level voltage as the output of the first inverter and correspondingly generating a low-level voltage as the output of the second inverter, so that the power consumption of the ADC array after generating pixel output signals is saved.
CN202280025448.1A 2022-02-10 2022-02-10 High-speed low-power consumption pixel bias circuit Pending CN117223293A (en)

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