CN117221745A - Integrating capacitor multiplexing readout circuit and implementation and design method thereof - Google Patents

Abstract

The invention provides an integral capacitance multiplexing readout circuit and an implementation and design method thereof. The invention adopts the integrating capacitance multiplexing technology for improving the charge processing capability, in the integrating process, adjacent pixels can realize the mutual multiplexing of integrating capacitances, realize larger integrating capacitances in the limited pixel size area, at least improve the charge processing capability of a reading circuit to the original two times, and effectively improve the charge processing capability of the reading circuit, thereby effectively improving the sensitivity of the detector and providing an effective mode for realizing the high sensitivity of the long-wave detector.

Description

Integrating capacitor multiplexing readout circuit and implementation and design method thereof

Technical Field

The invention relates to the technical field of infrared detector readout circuits, in particular to an integrating capacitor multiplexing readout circuit and an implementation and design method thereof.

Background

The infrared detection technology is widely applied to the fields of industry, reconnaissance, exploration and the like, and the principle is mainly that an infrared detection system is used for detecting an infrared radiation optical signal emitted by an object, the infrared radiation optical signal is converted into voltage or current through integration, storage and amplification of the optical signal, and image information of a target and a background can be obtained through subsequent processing.

As the core of an infrared detection system, the performance of an infrared detector determines the quality of imaging to a large extent. According to the different detection wave bands, the infrared detectors are mainly divided into short wave, medium wave, long wave and very long wave detectors.

In recent years, a long-wave detector has become an important research direction in the field of detectors. Dark current of the long wave detector is at least an order of magnitude higher than that of the short wave and medium wave detectors, so that the readout circuit for the long wave detector needs more charge processing capability to improve signal-to-noise ratio and sensitivity. One of the most effective ways to increase the charge handling capability of a readout circuit is to increase the integration capacitance inside the pixel, which is limited by the size of the pixel. How to improve the charge handling capability in a limited pixel area becomes an important technical difficulty in the design of long-wave infrared focal plane readout circuits.

The common way to improve the charge processing capability is to use a stacked capacitor as an integrating capacitor, connect capacitors made of different layers of metals in parallel, and stack the capacitors in the same pixel space.

Disclosure of Invention

The invention provides an integrating capacitor multiplexing readout circuit, an implementation method and a design method thereof.

According to the integrated capacitance multiplexing readout circuit provided by the embodiment of the invention, the readout circuit is arranged corresponding to the pixel array, the readout circuit is provided with a control switch for controlling connection and disconnection of the integrated capacitance between adjacent pixels, and the readout circuit is provided with a snapshot integrated mode and an integrated capacitance multiplexing mode, and is provided with a first time sequence for controlling the snapshot integrated mode and a second time sequence for controlling the integrated capacitance multiplexing mode;

when the reading circuit is in the snapshot integration mode, the control switch is turned off, all pixels are controlled to be integrated simultaneously through the first time sequence, and all information of the pixel array is read out sequentially according to a row-column sequence after integration is completed, and all information of the pixel array is read out in one frame;

when the reading circuit is in the integral capacitance multiplexing mode, the control switch is communicated, the pixel array is at least divided into two parts, the pixels of each part are integrated and read in batches through the second time sequence control, when one part of the pixels are integrated, the rest of integral capacitance is occupied, so that the equivalent integral capacitance of the part of the pixels which are being integrated is increased, the information of the corresponding pixels is sequentially read out after the integration is finished, the information of one subframe is read out, and after the pixels of the rest parts are integrated and read out in batches, the information of the corresponding subframes forms complete frame information.

According to some embodiments of the invention, the integrating capacitance of each adjacent two rows of pixels has the control switch;

when the reading circuit is in the integral capacitance multiplexing mode, the control switch is communicated, the pixel array is divided into an odd row pixel and an even row pixel, when all the odd row pixels are integrated, the odd row pixels occupy the integral capacitance of the adjacent even row pixels, at the moment, the equivalent integral capacitance of all the odd row pixels can become twice in the snapshot integral mode, and after the integration of the odd row pixels is completed, the information of all the odd row pixels can be sequentially read out according to the sequence, so that the information reading of one subframe is completed; when the even line pixels integrate, the even line pixels occupy the integration capacitance of the odd line pixels, at this time, the equivalent integration capacitance of all the even line pixels will become twice in the snapshot integration mode, after the integration of the even line pixels is completed, the information of all the even line pixels is sequentially read out, the information of another subframe is completed, and the information of two subframes forms a complete frame information.

In some embodiments of the invention, the control word of the logic circuit controlling the read-out circuit to perform mode switching comprises:

INTERLACE, for controlling row selection signals, INTERLACE is 0 in the snapshot integration mode, and at this time, all row selection signals in the pixel array are valid in sequence; in the integral capacitance multiplexing mode, INTERLACE is 1, at this time, the circuit is divided into an odd line and an even line for integral reading, and when the odd line is read, the line selection signals of all the odd lines in the circuit are valid in sequence, and the line selection signals of all the even lines are invalid; when the even row part is read out, row selection signals of all even rows are valid in sequence, and row selection signals of all odd rows are invalid;

the POLAR is used for controlling an integral control signal, and in the snapshot integral mode, the POLAR is 1, the integral control signals of all pixels are valid, and all pixels in the pixel array are integrated at the same time; in the integrating capacitor multiplexing mode, the POLAR is 0, at this time, the integrating control signals of the pixels in the pixel array are valid in sequence according to the odd-even row integrating sequence, when the pixels in the odd row are integrated, the integrating control signals of the pixels in all the odd row are valid, and when the pixels in the even row are integrated, the integrating control signals of the pixels in all the even row are valid.

According to some embodiments of the invention, the timing signals of the first and second timings comprise: ENBIN, GPOL, RS, RST INT, GPOL_,

the ENBIN is used for controlling the integrating capacitor combining switch, the GPOL and the GPOL_are used for controlling whether integration is carried out or not, the RST_INT is a reset control signal, and the RS is a row selection signal.

In some embodiments of the present invention, when no integration capacitor multiplexing is performed, enable is forced to be invalid, the connection of the integration capacitors between each group of adjacent pixels is disconnected, GPOL of all pixel arrays is valid, rst_int is valid within a reset time, RS is valid sequentially in row order, a readout circuit works in a snapshot integration manner, and all information of the pixel arrays is read out in one frame;

when multiplexing the integration capacitor, the integration capacitor of each group of adjacent pixels is set as effective, the integration capacitor of each group of adjacent pixels is connected through a switch, the GPOL of only one pixel in each group of adjacent pixels is effective, the pixel GPOL_signal with the effective GPOL signal is ineffective, and the integration can be performed; the GPOL signal for the other pixel is inactive and the GPOL _ signal is active and the detector charge for the pixel is drained to ground.

According to some embodiments of the invention, the readout circuitry is for a long wave infrared detector.

A method for implementing a digital circuit for an integrating capacitance multiplexing readout circuit according to an embodiment of the present invention is a method for implementing a digital circuit employing an integrating capacitance multiplexing readout circuit as described above, the method including:

a10, writing all control words and address bits through a serial port, and outputting through a serial-parallel conversion module;

a20, designing a row address selector and a column address selector, wherein the row address selector and the column address selector convert the input maximum and minimum addresses into the maximum and minimum addresses required by the current mode under the control of a control word;

a30, designing a row counter and a column counter, generating a zero clearing signal when the row counter and the column counter reach preset values, and counting the next frame;

a40, designing a time sequence control module, generating a control signal of a read-out circuit, and generating a corresponding control signal according to a working mode set by a control word;

a50, designing a row control signal buffer to generate a control signal of a pixel level;

a60, designing a row decoder and a column decoder.

According to an embodiment of the present invention, a method for designing an integrating capacitance multiplexing readout circuit as described above includes:

s100, analyzing an analog circuit connection mode required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing the connection design of an analog circuit;

s200, analyzing time sequence control logic required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing digital time sequence design;

s300, simulation verification is carried out on the designed read-out circuit, and the effectiveness of the integration capacitance multiplexing technology is verified through simulation results.

The invention has the following beneficial effects:

the integration capacitance multiplexing technology for improving the charge processing capability is adopted, in the integration process, adjacent pixels can realize the mutual multiplexing of the integration capacitances, larger integration capacitances are realized in the limited pixel size area, the charge processing capability of a reading circuit is at least improved to be at least twice as high as the original charge processing capability, and the charge processing capability of the reading circuit is effectively improved, so that the sensitivity of the detector is effectively improved, and an effective mode is provided for realizing the high sensitivity of the long-wave detector.

Drawings

FIG. 1 is a schematic diagram of a pixel-level implementation of an integrating capacitance multiplexing readout circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating the operation timing of the readout circuit in the snapshot integration mode according to an embodiment of the present invention;

FIG. 3 is a schematic diagram showing the operation timing of the readout circuit in the integrating capacitor multiplexing mode according to the embodiment of the present invention;

fig. 4 is a schematic diagram of a digital circuit implementation of an integrating capacitor multiplexing readout circuit according to an embodiment of the present invention.

Detailed Description

In order to further describe the technical means and effects adopted by the present invention for achieving the intended purpose, the following detailed description of the present invention is given with reference to the accompanying drawings and preferred embodiments.

Aiming at the problem that the charge processing capacity of the long-wave detector is limited, the invention provides a readout circuit for multiplexing an integrating capacitor for improving the charge processing capacity, and an implementation and design method thereof, which can be used with a laminated capacitor. In the working process of the reading circuit, the mutual multiplexing of the integration capacitances of adjacent pixels of the array can be realized, so that the equivalent integration capacitance is at least doubled as that of a single pixel, and the charge processing capacity of the long-wave detector is effectively improved.

According to the integrated capacitance multiplexing readout circuit provided by the embodiment of the invention, the readout circuit is arranged corresponding to the pixel array, and the readout circuit is provided with a control switch for controlling connection and disconnection of the integrated capacitance between adjacent pixels. As used herein, the term "adjacent pixels" may refer to adjacent rows of pixels, for example, adjacent two, three or more rows of pixels.

The readout circuit has a snapshot integration mode and an integration capacitance multiplexing mode, and has a first timing to control the snapshot integration mode and a second timing to control the integration capacitance multiplexing mode.

When the reading circuit is in a snapshot integration mode, the control switch is turned off, all pixels are integrated simultaneously under the control of a first time sequence, and all information of the pixel array is read out sequentially according to a row-column sequence after integration is completed;

when the reading circuit is in an integrating capacitance multiplexing mode, the control switch is communicated, the pixel array is at least divided into two parts, the pixels of each part are integrated and read in batches through the second time sequence control, when one part of the pixels are integrated, the residual part of the integrating capacitance is occupied, so that the equivalent capacitance of the part of the pixels which are being integrated is increased, the information of the corresponding pixels is sequentially read out after the integration is finished, the information reading of one subframe is completed, the pixels of the other parts are integrated in batches in sequence, and the information of each corresponding subframe forms complete frame information after the reading.

According to the integral capacitance multiplexing readout circuit provided by the embodiment of the invention, an integral capacitance multiplexing technology for improving the charge processing capability is adopted, in the integral process, adjacent pixels can realize mutual multiplexing of integral capacitances, larger integral capacitances are realized in a limited pixel size area, and the charge processing capability of the readout circuit is improved to at least twice that of the original one, so that the sensitivity of the detector is effectively improved.

According to some embodiments of the present invention, the integration capacitors of the pixels of each two adjacent rows have control switches, such as enable shown in fig. 1 is the control switch.

When the reading circuit is in an integrating capacitance multiplexing mode, the control switch is communicated, and the pixel array is divided into an odd row of pixels and an even row of pixels. It should be noted that, as described above, in the present invention, "when the readout circuit is in the integrating capacitance multiplexing mode, the control switch is turned on, and the pixel array is divided into at least two parts". That is, in the integrating capacitance multiplexing mode, the pixel array may be divided into two parts, or may be divided into three or more parts, and the present invention is described as being divided into two parts in this embodiment:

when all the odd-line pixels are integrated, the odd-line pixels occupy the integration capacitance of the adjacent even-line pixels, at the moment, the equivalent integration capacitance of all the odd-line pixels is doubled in a snapshot integration mode, and after the integration of the odd-line pixels is completed, the information of all the odd-line pixels is sequentially read out to complete the information reading of one subframe; when the even line pixels integrate, the even line pixels occupy the integration capacitance of the odd line pixels, at this time, the equivalent integration capacitance of all the even line pixels will become twice in the snapshot integration mode, after the integration of the even line pixels is completed, the information of all the even line pixels is sequentially read out, the information of another subframe is completed, and the information of two subframes forms a complete frame information.

In some embodiments of the invention, the control word of the logic circuit controlling the read-out circuit to perform mode switching comprises:

INTERLACE, for controlling row select signals, INTERLACE is 0 in the snapshot integration mode, and all row select signals in the pixel array are valid in sequence at this time; in the integral capacitance multiplexing mode, INTERLACE is 1, at this time, the circuit is divided into an odd line and an even line for integral reading, and during integral reading of the odd line, the line selection signals of all the odd lines in the circuit are valid in sequence, and the line selection signals of all the even lines are invalid; when the even row part is read out, row selection signals of all even rows are sequentially valid, and row selection signals of all odd rows are invalid.

The POLAR is used for controlling an integral control signal, and in a snapshot integral mode, the POLAR is 1, the integral control signals of all pixels are valid, and all pixels in the pixel array are integrated at the same time; in the integrating capacitor multiplexing mode, the POLAR is 0, at this time, the integrating control signals of the pixels in the pixel array are valid in turn according to the odd-even line integrating sequence, and when the pixels in the odd line are integrated, the integrating control signals of the pixels in all the odd line are valid, and when the pixels in the even line are integrated, the integrating control signals of the pixels in all the even line are valid.

According to some embodiments of the invention, as shown in connection with fig. 1-3, the timing signals of the first timing and the second timing comprise: ENBIN, GPOL, RS, RST INT, GPOL_,

the ENBIN is used for controlling the integrating capacitor combining switch, the GPOL and the GPOL_are used for controlling whether integration is carried out or not, the RST_INT is a reset control signal, and the RS is a row selection signal.

In some embodiments of the present invention, when no capacitance multiplexing is performed, enable is forced to be invalid, the connection of integration capacitors between each group of adjacent pixels is disconnected, GPOL of all pixel arrays is valid, rst_int is valid within a reset time, RS is valid sequentially in row order, a readout circuit works in a snapshot integration manner, and all information of the pixel arrays is read out in one frame;

when multiplexing the integration capacitor, the integration capacitor of each group of adjacent pixels is set as effective, the integration capacitor of each group of adjacent pixels is connected through a switch, the GPOL of only one pixel in each group of adjacent pixels is effective, the pixel GPOL_signal with the effective GPOL signal is ineffective, and the integration can be performed; the GPOL signal for the other pixel is inactive and the GPOL _ signal is active and the detector charge for the pixel is drained to ground.

According to some embodiments of the invention, the readout circuitry is for a long wave infrared detector.

According to the implementation method of the digital circuit for the integral capacitance multiplexing readout circuit, the implementation method of the digital circuit adopting the integral capacitance multiplexing readout circuit comprises the following steps:

a10, writing all control words and address bits through a serial port, and outputting through a serial-parallel conversion module;

a20, designing a row address selector and a column address selector, wherein the row address selector and the column address selector convert the input maximum and minimum addresses into the maximum and minimum addresses required by the current mode under the control of a control word;

a30, designing a row counter and a column counter, generating a zero clearing signal when the row counter and the column counter reach preset values, and counting the next frame;

a40, designing a time sequence control module, generating a control signal of a read-out circuit, and generating a corresponding control signal according to a working mode set by a control word;

a50, designing a row control signal buffer to generate a control signal of a pixel level;

a60, designing a row decoder and a column decoder.

According to the design method of the integral capacitance multiplexing readout circuit, the method is used for designing the integral capacitance multiplexing readout circuit, and comprises the following steps:

s100, analyzing an analog circuit connection mode required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing the connection design of an analog circuit;

s200, analyzing time sequence control logic required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing digital time sequence design;

s300, simulation verification is carried out on the designed read-out circuit, and the effectiveness of the integration capacitance multiplexing technology is verified through simulation results.

The integrating capacitance multiplexing readout circuit and the implementation and design method thereof according to the present invention are described in detail below with reference to the accompanying drawings in a specific embodiment. It is to be understood that the following description is exemplary only and is not to be taken as limiting the invention in any way.

The integrating capacitor multiplexing circuit and the implementation method thereof of the embodiment mainly comprise two parts, namely, the design of a pixel level and the design of a time sequence control circuit, and can be directly applied to all readout circuits adopting a direct injection mode.

As shown in fig. 1, firstly, an array of N rows and M columns is divided into N/2×m groups according to two pixels of every two adjacent rows, each group is connected through a control switch, and secondly, a set of timing signals ENBIN, GPOL, RS, RST _int and gpol_are designed to realize different working modes of the pixels. The ENBIN signal is used for controlling the integrating capacitor combining switch, GPOL and GPOL_are used for controlling whether integration is carried out or not, RST_INT is a reset control signal, and RS is a row selection signal.

The operation mode of the timing signal control can be described as:

when the capacitor is not used for multiplexing, the reading circuit works in a snapshot integration mode, one frame can read all information of all arrays, enable is forced to be invalid, connection among each group of pixels is disconnected, GPOL of all rows is valid, RST is valid in reset time, RS is valid in sequence according to row sequence, the reading circuit works in a snapshot integration mode, and one frame can read all information of the arrays;

when the integration capacitance multiplexing is carried out, the enable is effective, each group of pixels are connected through a switch, only one pixel GPOL of each group of pixels is effective, the pixel GPOL_signal of the GPOL signal effective is invalid, the integration can be carried out, the GPOL signal of the other pixel is invalid, the pixel does not carry out the integration, the GPOL_signal is effective, the charge of the detector corresponding to the pixel is discharged to the ground, the interference to the pixel under the integration is prevented, at the moment, the equivalent integration capacitance of the other pixel is connected in parallel in the pixel under the integration, the equivalent integration capacitance of a reading circuit is doubled, the operation mode is that the integration reading is carried out according to the odd-even lines, one subframe reads out signals of all odd lines, the other subframe reads out signals of all even lines, and two subframes form a frame signal. The above is a pixel level design approach for integrating capacitance multiplexing.

The timing sequence of the readout circuit under different working modes is designed, firstly, the circuit working timing sequence under the snapshot integration mode is designed, as shown in fig. 2, all pixels in the array are integrated at the same time, and the readout of the nth frame data is carried out after the integration of the nth frame signal is finished.

And secondly, designing a circuit working time sequence in an integrating capacitor multiplexing mode, as shown in fig. 3, dividing the array into odd-even rows, integrating twice, integrating only all odd rows or all even rows in the array each time, and similarly, dividing the array into odd-even two parts for reading, wherein the part with the integrated part is read first, the integrated part of all the odd rows in the array is read as one subframe, the integrated part of all the even rows in the array is read as another subframe, and the data of the two subframes are combined into a complete frame.

Fig. 4 shows a digital circuit implementation of the integrating capacitance multiplexing circuit:

firstly, writing all control words and address bits through a serial port, and outputting the control words and the address bits to a subsequent circuit through a serial-parallel conversion module;

secondly, designing row and column address selectors, wherein the row and column address selectors convert the input maximum and minimum addresses into the maximum and minimum addresses required by the current mode under the control of control words;

then, designing a row counter and a column counter, wherein when the row counter and the column counter reach a certain value, a zero clearing signal is generated, and counting of the next frame is carried out;

then, a time sequence control module is designed, the module mainly generates control signals of the analog circuit, and corresponding control signals can be generated according to the working mode set by the control word;

then, designing a row control signal buffer, wherein the module is used for generating a control signal of a pixel level, the POLAR_O and the POLAR_E can control the integration mode of the pixel array, and when INTERLACE is invalid, namely the circuit works in a snapshot integration mode, the POLAR_O and the POLAR_E are forced to be valid, and the integration mode of the circuit is full array integration; when INTERLACE is active, when the circuit is operated in the integrating capacitor combining mode, POLAR_O and POLAR_E are alternately active in the sequence of subframes, when POLAR_O is active, all odd-row pixels are integrated, even-row pixels are not integrated, and when POLAR_E is active, all even-row pixels are integrated, and odd-row pixels are not integrated.

Finally, the row and column decoders are designed. Compared with the default mode, in the integrating capacitor merging mode, the column-level working mode is not changed, so that the column decoder does not need to be controlled by a control word, all generated row selection signals are sequentially valid when the column decoder is at INTERLACE and are alternately valid according to the sequence of subframes when the column decoder is at INTERLACE and is not at 0, at this time, row selection signals are alternately valid in an interlaced mode, row selection control signals of all odd rows in one subframe are sequentially valid, and row selection control signals of all even rows in one subframe are sequentially valid.

According to the integral capacitance multiplexing readout circuit provided by the invention, a complete frame of information is divided into two subframes in time sequence to carry out integral readout, when all odd lines of an array are integrated, even lines are not integrated, at the moment, all pixels of the odd lines in the array multiplex the integral capacitance of adjacent even lines, so that the integral capacitance of the odd lines is doubled as compared with the original integral capacitance of the even lines, after the integral readout of all the odd lines in the array is finished, all the even lines of pixels in the array can multiplex the integral capacitance of adjacent odd lines, after the integral readout of all the even lines in the array is finished, the complete frame of information can be obtained at an output end, all the pixels in the whole array multiplex the integral capacitance of the adjacent lines, the equivalent integral capacitance of the readout circuit is doubled as compared with the original integral capacitance, the charge processing capacity of the readout circuit is effectively improved, and an effective mode is provided for realizing the high sensitivity of a long wave detector.

The design method of the integrating capacitance multiplexing readout circuit for improving the charge processing capability comprises the following steps:

step A: integrating capacitance multiplexing technology is fused into an actual circuit, and two working modes of a reading circuit are realized on the basis, wherein one working mode is a traditional snapshot integrating mode, and the other working mode is an integrating capacitance multiplexing mode;

and (B) step (B): analyzing an analog circuit connection mode and a time sequence control logic which are required by realizing an integrating capacitance multiplexing function on the basis of a traditional snapshot integrating mode;

step C: the analog circuit connection design is completed, so that the analog circuit connection design can simultaneously support the snapshot integration mode and the implementation of the integration capacitance multiplexing technology.

Step D: and (3) completing digital time sequence design, designing a special time sequence of an integral capacitor multiplexing mode, and realizing an integral capacitor multiplexing function on the basis of a snapshot integral mode through time sequence control.

Step E: and carrying out simulation verification on the designed read-out circuit, and verifying the validity of the integrating capacitance multiplexing technology through a simulation result.

In the step A, the working modes of a reading circuit are divided into two modes, one mode is a traditional snapshot integration mode, all pixels in an array are integrated at the same time in the mode, all pixels after integration are sequentially read out according to a row-column sequence, and all information of the array can be read out in one frame;

the other is an integrating capacitance multiplexing mode, the implementation of the function applies the integrating capacitance multiplexing technology provided by the invention, the whole array is divided into two parts of odd lines and even lines in the mode, when all the pixels of the odd lines are integrated, the pixels of the even lines do not integrate, at the moment, the pixels of the odd lines occupy the integrating capacitance of all the pixels of the adjacent even lines, after the integration of the pixels of the odd lines is finished, the information of the pixels of the odd lines is sequentially read out to complete the information reading of one subframe, when the pixels of the even lines are integrated, the pixels of the odd lines do not integrate, at the moment, the pixels of the even lines occupy the integrating capacitance of the pixels of the even lines, after the integration of the pixels of the even lines is finished, the information of the pixels of the even lines is sequentially read out to complete the information reading of the other subframe, and the information of the two subframes form complete frame information.

In the step B, the difference between the snapshot integration mode and the integration capacitance multiplexing mode in the analog circuit connection is only a pixel level, the rest column levels, the output level and the bias circuit do not need to make any change, the time sequence control is greatly different, the integration capacitance multiplexing mode should ensure that the row selection signals of all odd rows are sequentially valid in all sub-frames of the odd row pixel integration, the row selection signals of even rows are invalid, the row selection signals of all even rows are sequentially valid in all sub-frames of the even row pixel integration, the row selection signals of odd rows are invalid, the readout time of each sub-frame is 1/2 of the whole frame, and in addition, the integration control signals of rows which do not perform integration are invalid, so that the even rows occupy the integration capacitance of adjacent rows in a time sharing manner is realized.

In the step C, analysis shows that in the circuit connection design, aiming at the realization of the multiplexing function of the integral capacitance, a control switch is needed to be added in the pixels so that the pixels can be connected to the pixels of the adjacent rows, when the multiplexing of the integral capacitance is carried out, the integral interlacing of the pixels is effective, the integral capacitance of the pixels which do not carry out the integral can be integrated into the pixels which are being integrated, and the equivalent integral capacitance of a reading circuit is increased; when the integration capacitor is not multiplexed, the control switch is turned off, and each pixel operates independently, and the integration readout is performed using the integration capacitor. The control word for controlling the switch to be closed and turned off is ENBIN, when ENBIN is high, the control switch is closed, the integration capacitors are combined, and when ENBIN is low, the control switch is opened, and the integration capacitors are not combined.

In addition, in step D, a logic circuit for realizing integration capacitance multiplexing is added to the digital circuit, and a INTERLACE, POLAR control word is introduced. INTERLACE is used for controlling row selection signals, INTERLACE is set to 0 when the circuit works in a snapshot integration mode, and all row selection signals are valid in sequence; when the circuit works in the integrating capacitor multiplexing mode, INTERLACE should be set to 1, and the circuit is divided into two subframes for integrating readout, wherein row selection signals of all odd rows in one subframe are sequentially valid, and row selection signals of all even rows are invalid; the row select signals for all even rows in another subframe are sequentially active and the row select signals for all odd rows are inactive. The POLAR is used for controlling the integral control signals, and when the circuit works in a snapshot integral mode, the integral control signals of all rows are valid, and the POLAR is set to be 1 at the moment; when the circuit works in the integrating capacitance multiplexing mode, POLAR should be set to 0, pixel integration control signals of all rows in the array are enabled in an interlacing mode, and rows which are not read out do not participate in integration.

Finally, in step E, simulation verification is carried out on the integrating capacitance multiplexing function of the reading circuit, a current source is added at the input end of the pixel level for exciting the analog photocurrent signal, and the simulation shows that under the condition of the same integrating time and current signal, the signal variation quantity in the integrating capacitance multiplexing mode is 1/2 of that in the snapshot integrating mode, which proves that the integrating capacitance in the integrating capacitance multiplexing mode becomes 2 times that in the snapshot integrating mode, and the effectiveness of the integrating capacitance multiplexing technology is verified.

In summary, according to the integrating capacitance multiplexing technology provided by the invention, the infrared focal plane readout circuits with two working modes are integrated on the same chip, and in the integrating capacitance multiplexing mode, the equivalent integrating capacitance of the readout circuit is enlarged to be twice as much as the original one, so that the charge processing capacity of the readout circuit is increased, and the signal-to-noise ratio and the sensitivity of the long wave detector are effectively improved. At the same time, the design method is simple to understand and easy to operate and implement.

While the invention has been described in connection with specific embodiments thereof, it is to be understood that these drawings are included in the spirit and scope of the invention, it is not to be limited thereto.

Claims (8)

1. An integrating capacitance multiplexing readout circuit, wherein the readout circuit is arranged corresponding to a pixel array, the readout circuit is provided with a control switch for controlling connection and disconnection of integrating capacitances between adjacent pixels, the readout circuit is provided with a snapshot integrating mode and an integrating capacitance multiplexing mode, and is provided with a first time sequence for controlling the snapshot integrating mode and a second time sequence for controlling the integrating capacitance multiplexing mode;

when the reading circuit is in the snapshot integration mode, the control switch is turned off, all pixels are controlled to be integrated simultaneously through the first time sequence, and all information of the pixel array is read out sequentially according to a row-column sequence after integration is completed, and all information of the pixel array is read out in one frame;

when the reading circuit is in the integral capacitance multiplexing mode, the control switch is communicated, the pixel array is at least divided into two parts, the pixels of each part are integrated and read in batches through the second time sequence control, when one part of the pixels are integrated, the rest of integral capacitance is occupied, so that the equivalent integral capacitance of the part of the pixels which are being integrated is increased, the information of the corresponding pixels is sequentially read out after the integration is finished, the information of one subframe is read out, and after the pixels of the rest parts are integrated and read out in batches, the information of the corresponding subframes forms complete frame information.

2. The integrating capacitance multiplexing readout circuit according to claim 1, wherein the integrating capacitances of the pixels of each adjacent two rows have the control switch;

when the reading circuit is in the integral capacitance multiplexing mode, the control switch is communicated, the pixel array is divided into an odd row pixel and an even row pixel, when all the odd row pixels are integrated, the odd row pixels occupy the integral capacitance of the adjacent even row pixels, at the moment, the equivalent integral capacitance of all the odd row pixels can become twice in the snapshot integral mode, and after the integration of the odd row pixels is completed, the information of all the odd row pixels can be sequentially read out according to the sequence, so that the information reading of one subframe is completed; when the even line pixels integrate, the even line pixels occupy the integration capacitance of the odd line pixels, at this time, the equivalent integration capacitance of all the even line pixels will become twice in the snapshot integration mode, after the integration of the even line pixels is completed, the information of all the even line pixels is sequentially read out, the information of another subframe is completed, and the information of two subframes forms a complete frame information.

3. The integrating capacitance multiplexing readout circuit of claim 1, wherein the control word of the logic circuit controlling the readout circuit to perform mode switching comprises:

INTERLACE, for controlling row select signals, INTERLACE is 0 in the snapshot integration mode, and at this time, all row select signals in the pixel array are valid; in the integration capacitance multiplexing mode, INTERLACE is 1, at this time, the circuit is divided into an odd line and an even line for integration reading, and during the integration reading of the odd line, the line selection signals of all the odd lines in the circuit are valid in sequence, and the line selection signals of all the even lines are invalid; when the even row part is read out, row selection signals of all even rows are valid in sequence, and row selection signals of all odd rows are invalid;

the POLAR is used for controlling an integral control signal, and in the snapshot integral mode, the POLAR is 1, the integral control signals of all pixels are valid, and all pixels in the pixel array are integrated at the same time; in the integrating capacitor multiplexing mode, the POLAR is 0, at this time, the integrating control signals of the pixels in the pixel array are valid in sequence according to the odd-even row integrating sequence, when the pixels in the odd row are integrated, the integrating control signals of the pixels in all the odd row are valid, and when the pixels in the even row are integrated, the integrating control signals of the pixels in all the even row are valid.

4. The integrating capacitance multiplexing readout circuit of claim 1, wherein the timing signals of the first timing and the second timing comprise: ENBIN, GPOL, RS, RST INT, GPOL_,

the ENBIN is used for controlling the integrating capacitor combining switch, the GPOL and the GPOL_are used for controlling whether integration is carried out or not, the RST_INT is a reset control signal, and the RS is a row selection signal.

5. The integrating capacitor multiplexing readout circuit according to claim 4, wherein when no integrating capacitor multiplexing is performed, enable is forced to be invalid, integrating capacitors between each group of adjacent pixels are disconnected, GPOL of all pixel arrays are valid, rst_int is valid within a reset time, RS is valid in sequence in a row order, the readout circuit operates in a snapshot integration manner, and all information of the pixel arrays is read out in one frame;

when multiplexing the integration capacitor, the integration capacitor of each group of adjacent pixels is set as effective, the integration capacitor of each group of adjacent pixels is connected through a switch, the GPOL of only one pixel in each group of adjacent pixels is effective, the pixel GPOL_signal with the effective GPOL signal is ineffective, and the integration can be performed; the GPOL signal for the other pixel is inactive and the GPOL _ signal is active and the detector charge for the pixel is drained to ground.

6. The integrating capacitance multiplexing readout circuit of any one of claims 1 to 5, wherein the readout circuit is for a long wave infrared detector.

7. A method for implementing a digital circuit for an integrating capacitance multiplexing readout circuit, the method for implementing a digital circuit employing an integrating capacitance multiplexing readout circuit according to any one of claims 1-6, the method comprising:

a10, writing all control words and address bits through a serial port, and outputting through a serial-parallel conversion module;

a20, designing a row address selector and a column address selector, wherein the row address selector and the column address selector convert the input maximum and minimum addresses into the maximum and minimum addresses required by the current mode under the control of a control word;

a30, designing a row counter and a column counter, generating a zero clearing signal when the row counter and the column counter reach preset values, and counting the next frame;

a40, designing a time sequence control module, generating a control signal of a read-out circuit, and generating a corresponding control signal according to a working mode set by a control word;

a50, designing a row control signal buffer to generate a control signal of a pixel level;

a60, designing a row decoder and a column decoder.

8. A method of designing an integrating capacitance multiplexing readout circuit, characterized in that the method is for designing an integrating capacitance multiplexing readout circuit according to any one of claims 1 to 6, the method comprising:

s100, analyzing an analog circuit connection mode required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing the connection design of an analog circuit;

s200, analyzing time sequence control logic required by a readout circuit for realizing an integrating capacitor multiplexing function on the basis of a snapshot integrating mode, and completing digital time sequence design;

s300, simulation verification is carried out on the designed read-out circuit, and the effectiveness of the integration capacitance multiplexing technology is verified through simulation results.