CN117221252A - Multi-physical interface control communication method and system of Ethernet and Ethernet chip - Google Patents
Multi-physical interface control communication method and system of Ethernet and Ethernet chip Download PDFInfo
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Abstract
The application discloses a method and a system for controlling communication by multiple physical interfaces of Ethernet and an Ethernet chip, wherein the method comprises the following steps: when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration; the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration. In the application, when a plurality of PHY chips send data to the Ethernet chip, the PHY chips send arbitration sequences to the arbitration bus, then the arbitration serial numbers returned by the arbitration bus are compared with the arbitration serial numbers sent by the PHY chips until the comparison results are consistent, and the PHY chips can send data to the Ethernet chip, so that the data sending sequences of the PHY chips can be sequenced successively, thereby realizing the communication between one Ethernet chip and the plurality of PHY chips, and reducing the cost.
Description
Technical Field
The present application relates to the field of ethernet technologies, and in particular, to a method and a system for controlling communication by using multiple physical interfaces of ethernet, and an ethernet chip.
Background
Ethernet is a computer network, and is also the most widely used network access technology in local area networks, and has its own advantages in terms of data transmission, and can access the internet to achieve a wider range of remote access control. The IEEE organization sets the technical standard of ethernet in the IEEE 802.3 standard, and a medium access control layer (Media Access Control, MAC) of the ethernet may communicate with a physical layer (PHY) through a medium independent interface, where a default medium independent interface is a medium independent interface (Media Independent Interface, MII) and a simplified reduced medium independent interface (Reduced Media Independent Interface, RMII), and a communication rate of the ethernet may reach 10/100Mbit/s.
Current ethernet MACs can support access to up to 32 PHY chips through a station management interface (Serial Management Interface, SMI), and an application can select one PHY from the 32 PHYs to transmit control data or receive status information, so that the MAC of one ethernet chip can only communicate with one PHY at a time. However, when the MAC of the ethernet chip and the communication of the plurality of PHY chips are involved, one PHY chip needs to be configured for each ethernet chip, so that the plurality of ethernet chips need to be used, which is costly.
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present application is to provide a method and a system for controlling communication with multiple physical interfaces of ethernet and an ethernet chip, so as to solve the problem of high cost caused by using multiple ethernet chips when the MAC of the existing ethernet chip communicates with multiple PHY chips.
The technical scheme of the application is as follows:
a multi-physical interface control communication method of an ethernet, comprising:
when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration;
the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration.
In a further arrangement of the present application, when the ethernet chip receives data transmitted by two or more PHY chips, the step of each PHY chip transmitting an arbitration sequence number to an arbitration bus to perform arbitration includes:
each PHY chip sends an arbitration serial number to an arbitration bus;
the PHY chip compares the transmitted arbitration serial number with the arbitration serial number returned by the arbitration bus, and when the comparison result is consistent, the PHY chip arbitrates out and transmits data to the Ethernet chip;
when the arbitration serial number sent by the PHY chip is inconsistent with the arbitration serial number returned by the arbitration bus, the control PHY chip continues to send the arbitration serial number to the arbitration bus until the comparison result is consistent.
In a further arrangement of the present application, the step of the ethernet chip querying the arbitration result of each PHY chip and receiving the data sent by the PHY chip that has been found by arbitration includes:
the Ethernet chip sends address requests to each PHY chip in a broadcast mode;
acquiring the address of a PHY chip which wins arbitration;
and receiving the data transmitted by the PHY chip which wins arbitration.
In a further arrangement of the present application, the step of each PHY chip sending an arbitration sequence number to an arbitration bus includes:
and when the PHY chip receives the data, caching the data and sending an arbitration serial number to an arbitration bus.
In a further arrangement of the application, the arbitration sequence number of each PHY chip is inconsistent.
The application further provides that the multi-physical interface control communication method of the Ethernet further comprises the following steps:
when the Ethernet chip communicates with one PHY chip, disconnecting the arbitration bus and acquiring the address of the PHY chip;
and receiving the data sent by the PHY chip.
The application further provides that the multi-physical interface control communication method of the Ethernet further comprises the following steps:
when the Ethernet chip sends data to the PHY chip, the address of the PHY chip to be accessed is acquired;
the ethernet chip sends data to the PHY chip according to the address of the PHY chip.
A multi-physical interface control communication system of an ethernet network, comprising: an Ethernet chip, a PHY chip, an arbitration bus, a medium independent interface bus and a station management interface bus; wherein,
the Ethernet chip is provided with a medium access control unit;
each PHY chip is connected through the arbitration bus;
the medium independent interface bus is connected between the medium access control unit and the PHY chip;
the station management interface bus is connected between the medium access control unit and the PHY chip;
the Ethernet chip sends data to the PHY chip through the medium independent interface bus and receives the data sent by the PHY chip;
the PHY chip is used for sending an arbitration serial number to the arbitration bus when receiving data, and arbitrating the sent arbitration serial number with an arbitration serial number returned by the arbitration bus;
the Ethernet chip is also used for inquiring the arbitration result of each PHY chip through the station management interface bus.
In a further arrangement of the application, the PHY chip includes: the system comprises a cache module and an arbitration module; wherein,
the buffer memory module is connected with the medium access control unit through the medium independent interface bus and is used for receiving data and buffering the data;
the arbitration module is connected with the medium access control unit through the station management interface bus, and is used for sending an arbitration serial number to the arbitration bus when the PHY chip receives data, comparing the sent arbitration serial number with the arbitration serial number returned by the arbitration bus, and feeding back the comparison result to the Ethernet chip when the Ethernet chip inquires the arbitration result of each PHY chip through the station management interface bus.
An ethernet chip comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is used for implementing the ethernet multi-physical interface control communication method when executed by the processor.
The application provides a method and a system for controlling and communicating a plurality of physical interfaces of Ethernet and an Ethernet chip, wherein the method for controlling and communicating the plurality of physical interfaces of the Ethernet comprises the following steps: when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration; the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration. In the application, when a plurality of PHY chips send data to the Ethernet chip, the PHY chips send arbitration sequences to the arbitration bus, then the arbitration serial numbers returned by the arbitration bus are compared with the arbitration serial numbers sent by the PHY chips until the comparison results are consistent, and the PHY chips can send data to the Ethernet chip, so that the data sending sequences of the PHY chips can be sequenced successively, thereby realizing the communication between one Ethernet chip and the plurality of PHY chips, and reducing the cost.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for controlling communication by multiple physical interfaces of an ethernet network according to the present application.
Fig. 2 is a flow chart of an ethernet chip transmitting data in one embodiment of the present application.
Fig. 3 is a flow chart of an ethernet chip receiving data in one embodiment of the present application.
Fig. 4 is a schematic diagram of a multi-physical interface control communication system of an ethernet in accordance with the present application.
Fig. 5 is a schematic diagram of one ethernet chip in communication with a single PHY chip in the present application.
The marks in the drawings are as follows: 100. an Ethernet chip; 110. a medium access control unit; 200. a PHY chip; 210. a cache module; 220. and an arbitration module.
Detailed Description
The application provides a method, a system and an Ethernet chip for controlling communication by multiple physical interfaces of Ethernet, which are used for making the purposes, technical schemes and effects of the application clearer and more definite, and the application is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description and claims, unless the context specifically defines the terms "a," "an," "the," and "the" include plural referents. If there is a description of "first", "second", etc. in an embodiment of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
Referring to fig. 1 to 3, the present application provides a preferred embodiment of a method for controlling communication with multiple physical interfaces of an ethernet.
The application provides a multi-physical interface control communication method of Ethernet, as shown in figure 1, comprising the following steps:
s100, when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration;
in this embodiment, after the PHY chip receives data, it starts to prepare to send data to the MAC of the ethernet chip, at this time, each PHY chip sends an arbitration sequence number to the arbitration bus, and at the same time, the arbitration bus also replies an arbitration sequence number, if the arbitration sequence number replied by the arbitration bus is the same as the arbitration sequence number sent by the PHY chip, it indicates that the arbitration is winning, and the PHY chip that is currently winning may send data to the MAC of the ethernet chip. If the PHY chip does not receive data, the PHY chip will not send an arbitration sequence number to the arbitration line.
S200, the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip with the winning arbitration.
In this embodiment, the ethernet chip queries the arbitration result of each PHY chip through the station management interface bus, and when it is queried that the arbitration result of one PHY chip is consistent, the data sent by the PHY chip that meets the arbitration result will be preferentially received until the data sending of all PHY chips is completed.
Therefore, in the application, when a plurality of PHY chips send data to the Ethernet chip, the PHY chips send arbitration sequences to the arbitration bus, then the arbitration serial numbers returned by the arbitration bus are compared with the arbitration serial numbers sent by the PHY chips, and when the comparison results are consistent, namely only when the arbitration is successful, the PHY chips send data to the Ethernet chip, so that the data sending sequences of the PHY chips can be sequenced successively, two or more PHY chips are prevented from sending data to the Ethernet chip at the same time, thereby realizing the communication between one Ethernet chip and the plurality of PHY chips, and reducing the cost.
In some embodiments, when the ethernet chip receives data transmitted by more than two PHY chips, the step of each PHY chip transmitting an arbitration sequence number to the arbitration bus for arbitration includes the sub-steps of:
s110, each PHY chip sends an arbitration serial number to an arbitration bus;
s120, the PHY chip compares the transmitted arbitration serial number with the arbitration serial number returned by the arbitration bus, and when the comparison result is consistent, the PHY chip arbitrates out and transmits data to the Ethernet chip;
and S130, when the arbitration serial number sent by the PHY chip is inconsistent with the arbitration serial number returned by the arbitration bus, the PHY chip continuously sends the arbitration serial number to the arbitration bus until the comparison result is consistent.
In this embodiment, the PHY chip compares the transmitted arbitration sequence number with the arbitration sequence number returned by the arbitration bus, if the comparison result is consistent, it indicates that the current PHY chip wins arbitration, if the arbitration sequence number returned by the arbitration bus is inconsistent with the arbitration sequence number transmitted by the PHY chip, it indicates that the arbitration fails, the PHY chip continues to transmit data to the arbitration bus, waits for an arbitration sequence number returned on the arbitration bus to compare, and does not transmit data to the ethernet chip until the arbitration is successful. It should be noted that, each PHY chip defines an arbitration sequence number, that is, the arbitration sequence numbers of each PHY chip are inconsistent, so when each PHY chip sends an arbitration sequence number to the arbitration bus and compares, only one PHY chip will always succeed at the same time, and a PHY chip with successful arbitration can send data to the ethernet chip.
In some embodiments, the step of each PHY chip sending an arbitration sequence number to an arbitration bus includes the sub-steps of:
and S111, caching the data when the PHY chip receives the data, and sending an arbitration serial number to an arbitration bus.
In this embodiment, when the PHY chip receives data and needs to send the data to the ethernet, the received data is first buffered, and the data is not sent to the ethernet chip until the PHY chip wins arbitration.
In some embodiments, the step of the ethernet chip querying the arbitration result of each PHY chip and receiving the data sent by the PHY chip that has been arbitrated out includes the sub-steps of:
s210, the Ethernet chip sends an address request to each PHY chip in a broadcast mode;
s220, acquiring an address of a PHY chip which wins arbitration;
s230, receiving data transmitted by the PHY chip which wins arbitration.
In this embodiment, the ethernet chip controls the PHY chip that needs to transmit data through the station management interface bus SMI. In the process of arbitration of the PHY chip, the Ethernet chip queries the arbitration result of the PHY chip, sends an address request to each PHY chip in a broadcast mode, acquires the address of the PHY chip with the arbitration success through the station management interface bus SMI after the arbitration success of one PHY chip is queried, and receives the data sent by the PHY chip through the medium independent interface bus MII.
In some embodiments, the method of multi-physical interface control communication of ethernet further comprises:
s300, disconnecting an arbitration bus and acquiring an address of a PHY chip when the Ethernet chip is communicated with the PHY chip;
s400, receiving data sent by the PHY chip.
In this embodiment, when only a single PHY chip is required to communicate with the ethernet chip, the PHY chip is not required to arbitrate with the arbitration bus, so that the arbitration bus can be disconnected, and the ethernet chip can directly receive the data sent by the PHY chip by acquiring the address of the PHY chip. Therefore, the application can realize the communication between the Ethernet chip and a plurality of PHY chips and simultaneously can also be compatible with the communication between the traditional single PHY chip and the Ethernet chip.
In some embodiments, the method of multi-physical interface control communication of ethernet further comprises:
s101, when an Ethernet chip sends data to a PHY chip, acquiring an address of the PHY chip to be accessed;
s102, the Ethernet chip sends data to the PHY chip according to the address of the PHY chip.
In this embodiment, the medium access control unit MAC of the ethernet chip is connected to the PHY chip by using a medium independent interface bus MII or a reduced medium independent interface bus RMII, so as to implement data transmission and reception. The medium access control unit MAC of the Ethernet chip is also connected with the PHY chip through the station management interface bus SMI, the Ethernet chip controls the PHY chip needing to transmit data through the station management interface bus, and after the Ethernet chip obtains the address of the PHY chip needing to transmit data, the Ethernet chip transmits data to each PHY chip through the medium independent interface bus or the simplified medium independent interface bus.
The communication principle between the Ethernet chip and the PHY chip is described below by taking the Ethernet chip as a singlechip MCU as an example. As shown in fig. 2 and fig. 3, the single chip microcomputer MCU transmits required data to the medium access control unit through the FIFO memory through the AHB interface, the medium access control unit accesses the PHY chip through the station management interface bus SMI, writes the PHY chip address and data, and the medium access control unit transmits the data to the PHY chip to be accessed through the medium independent interface bus MII or the reduced medium independent interface bus RMII, which is the data transmission process of the ethernet chip. After the PHY chip receives the data, the PHY chip prepares to send the data to the medium access control unit, stores the data in the buffer module, waits for the comparison result of the arbitration module, starts to continuously send an arbitration serial number to the arbitration bus, the arbitration bus returns an arbitration serial number, compares the returned arbitration serial number with the arbitration serial number sent by the PHY chip, if the comparison result is consistent, the arbitration is successful, otherwise, the arbitration is failed, the data received by the PHY chip is sent to the medium independent interface bus MII or the reduced medium independent interface bus RMII from the buffer module after the arbitration is successful, and is sent to the medium access control unit of the singlechip through the medium independent interface bus MII or the reduced medium independent interface bus to complete the data transmission of the PHY chip, namely the receiving process of the data of the Ethernet chip.
In some embodiments, as shown in fig. 4, the present application further provides a multi-physical interface control communication system of an ethernet, which includes: ethernet chip 100, PHY chip 200, arbitration bus AB, media independent interface bus MII, and station management interface bus SMI. Wherein the ethernet chip 100 has a medium access control unit 110; each PHY chip 200 is connected through the arbitration bus AB; the medium independent interface bus MII is connected between the medium access control unit 110 and the PHY chip 200; the station management interface bus SMI is connected between the medium access control unit 110 and the PHY chip 200; the ethernet chip 100 transmits data to the PHY chip 200 through the medium independent interface bus MII, and receives data transmitted by the PHY chip 200; the PHY chip 200 is configured to send an arbitration sequence number to the arbitration bus AB when receiving data, and arbitrate the sent arbitration sequence number with an arbitration sequence number returned by the arbitration bus AB; the ethernet chip 100 is further configured to query the arbitration result of each PHY chip 200 through the station management interface bus SMI.
In this embodiment, when the ethernet chip 100 communicates with the plurality of PHY chips 200, each PHY chip 200 is connected through the arbitration bus AB, each PHY chip 200 transmits an arbitration sequence number to the arbitration bus AB, and after arbitrating with the arbitration sequence number replied by the arbitration bus AB, only the PHY chip 200 that has been found out in the arbitration can transmit data to the ethernet chip 100, so as to avoid the preemption problem of arbitration priority when two or more PHY chips 200 transmit data to the ethernet chip 100 at the same time. The medium independent interface bus MMI is connected between the ethernet chip 100 and the PHY chip 200, and is used to implement data transmission (including transmission and reception) between the ethernet chip 100 and the PHY chip 200. The station management interface bus SMI is connected between the ethernet chip 100 and the PHY chip 200, and the ethernet chip 100 controls each PHY chip 200 through the station management interface bus SMI, for example, when transmitting data, the station management interface bus SMI may control the PHY chip 200 that needs to transmit data, obtain the address of the PHY chip 200 that needs to transmit data, and when receiving data, query each PHY chip 200, obtain the address of the PHY chip 200 that wins arbitration, so as to receive the data transmitted by the PHY chip 200 that wins arbitration.
In some embodiments, the ethernet chip 100 may be a single-chip microcomputer MCU.
In specific implementation, taking the MCU as an example, when the MCU sends data to the PHY chip 200, the MCU transmits the data to be sent to the mac unit 110 through the FIFO (First Input FirstOutput) buffer, and then the mac unit 110 accesses the address and data of the PHY chip 200 through the station management interface bus SMI, and then transmits the data to be sent to the PHY chip 200 to be accessed through the MII.
When a plurality of PHY chips 200 send data to the MCU, the PHY chips 200 send arbitration sequences to the arbitration bus AB, then the arbitration sequence numbers returned by the arbitration bus AB are compared with the arbitration sequence numbers sent by the PHY chips 200, when the comparison results are consistent, namely, only when the arbitration is successful, the PHY chips 200 send data to the MCU, so that the data sending sequences of the PHY chips 200 can be sequenced sequentially, two or more PHY chips 200 are prevented from sending data to the MCU at the same time, thereby realizing the communication between one Ethernet chip 100 and the plurality of PHY chips 200, and reducing the cost.
In some embodiments, as shown in fig. 5, in this embodiment, when only a single PHY chip is required to communicate with the ethernet chip 100, the PHY chip 200 is not required to arbitrate with the arbitration bus AB, so that the arbitration bus AB may be disconnected, and the ethernet chip 100 may directly receive the data sent by the PHY chip 200 by acquiring the address of the PHY chip 200. Therefore, the present application can realize communication between the ethernet chip 100 and the plurality of PHY chips 200, and simultaneously can also be compatible with the conventional communication between a single PHY chip and the ethernet chip.
In some embodiments, as shown in fig. 4, the PHY chip 200 includes: a cache module 210 and an arbitration module 220; wherein, the buffer module 210 is connected to the medium access control unit 110 through the medium independent interface bus MII, and is configured to receive and buffer data; the arbitration module 220 is connected to the medium access control unit 110 through the station management interface bus SMI, and is configured to send an arbitration sequence number to the arbitration bus AB when the PHY chip 200 receives data, compare the sent arbitration sequence number with an arbitration sequence number returned by the arbitration bus AB, and feed back a comparison result to the ethernet chip 100 when the ethernet chip 100 queries an arbitration result of each PHY chip 200 through the station management interface bus SMI.
In this embodiment, the buffer module 210 is mainly configured to buffer data received by the PHY chip 200, and when the PHY chip 200 receives data that needs to be sent to the ethernet chip 100, the data is first buffered in the buffer module 210. The arbitration module 220 defines an arbitration sequence number for the PHY chip 200, the PHY chip 200 always sends an arbitration sequence number to the arbitration bus AB after receiving data, the arbitration bus AB replies an arbitration sequence number, the arbitration module 220 compares the sent arbitration sequence number with the arbitration sequence number returned by the arbitration bus AB, if the comparison result is consistent, that is, the arbitration sequence number sent by the arbitration module 220 is consistent with the received arbitration sequence number, that is, the arbitration win is illustrated, the ethernet chip 100 can query the arbitration result of each PHY chip 200 through the station management interface bus SMI, send an address request to each PHY chip 200 in a broadcast mode, and the data buffered in the buffer module 210 of the arbitrated PHY chip 200 is sent to the ethernet chip 100. If the PHY chip 200 fails to arbitrate, the arbitration module 220 continues to send arbitration sequence numbers, waiting for the next arbitration sequence number to be returned on the arbitration bus for comparison until arbitration wins.
In some embodiments, the buffer module 210 may be a FIFO buffer, a Static Random-Access Memory (SRAM), a dynamic Random-Access Memory (DynamicRandom Access Memory, DRAM), etc., and the arbitration bus AB may be a CAN bus, an I2C bus, etc., and the arbitration module 220 may be a CAN bus arbitration module, an I2C bus arbitration module, etc.
In some embodiments, the present application also provides an ethernet chip comprising a memory and a processor, the memory having stored thereon a computer program for implementing the steps in the following method when executed by the processor:
s100, when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration;
s200, the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip with the winning arbitration.
In summary, the method, the system and the ethernet chip for controlling communication by using multiple physical interfaces of ethernet provided by the present application have the following beneficial effects:
when a plurality of PHY chips send data to an Ethernet chip, the PHY chips send arbitration sequences to an arbitration bus, then the arbitration sequence numbers returned by the arbitration bus are compared with the arbitration sequence numbers sent by the PHY chips until the comparison results are consistent, and the PHY chips send data to the Ethernet chip, so that the data sending sequences of the PHY chips can be sequenced successively, the communication between one Ethernet chip and the plurality of PHY chips is realized, the data of the plurality of PHY chips can be received and analyzed by adopting one Ethernet chip, the cost can be effectively reduced, and the communication efficiency is improved.
It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A method for controlling communication by multiple physical interfaces of an ethernet network, comprising:
when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration;
the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration.
2. The method of claim 1, wherein when the ethernet chip receives data transmitted from two or more PHY chips, each PHY chip transmits an arbitration sequence number to an arbitration bus to perform arbitration, comprising:
each PHY chip sends an arbitration serial number to an arbitration bus;
the PHY chip compares the transmitted arbitration serial number with the arbitration serial number returned by the arbitration bus, and when the comparison result is consistent, the PHY chip arbitrates out and transmits data to the Ethernet chip;
when the arbitration serial number sent by the PHY chip is inconsistent with the arbitration serial number returned by the arbitration bus, the PHY chip continues to send the arbitration serial number to the arbitration bus until the comparison result is consistent.
3. The method for ethernet multi-physical interface control communication according to claim 1, wherein the step of the ethernet chip querying the arbitration result of each PHY chip and receiving the data transmitted by the PHY chip that has winning arbitration comprises:
the Ethernet chip sends address requests to each PHY chip in a broadcast mode;
acquiring the address of a PHY chip which wins arbitration;
and receiving the data transmitted by the PHY chip which wins arbitration.
4. The method of claim 2, wherein the step of each PHY chip transmitting an arbitration sequence number to an arbitration bus comprises:
and when the PHY chip receives the data, caching the data and sending an arbitration serial number to an arbitration bus.
5. The method of claim 1, wherein the arbitration sequence number of each PHY chip is not identical.
6. The method of claim 1, further comprising:
when the Ethernet chip communicates with one PHY chip, disconnecting the arbitration bus and acquiring the address of the PHY chip;
and receiving the data sent by the PHY chip.
7. The method of claim 1, further comprising:
when the Ethernet chip sends data to the PHY chip, the address of the PHY chip to be accessed is acquired;
the ethernet chip sends data to the PHY chip according to the address of the PHY chip.
8. A multi-physical interface control communication system for an ethernet network, comprising: an Ethernet chip, a PHY chip, an arbitration bus, a medium independent interface bus and a station management interface bus; wherein,
the Ethernet chip is provided with a medium access control unit;
each PHY chip is connected through the arbitration bus;
the medium independent interface bus is connected between the medium access control unit and the PHY chip;
the station management interface bus is connected between the medium access control unit and the PHY chip;
the Ethernet chip sends data to the PHY chip through the medium independent interface bus and receives the data sent by the PHY chip;
the PHY chip is used for sending an arbitration serial number to the arbitration bus when receiving data, and arbitrating the sent arbitration serial number with an arbitration serial number returned by the arbitration bus;
the Ethernet chip is also used for inquiring the arbitration result of each PHY chip through the station management interface bus.
9. The ethernet multi-physical interface control communication system according to claim 8, wherein said PHY chip comprises: the system comprises a cache module and an arbitration module; wherein,
the buffer memory module is connected with the medium access control unit through the medium independent interface bus and is used for receiving data and buffering the data;
the arbitration module is connected with the medium access control unit through the station management interface bus, and is used for sending an arbitration serial number to the arbitration bus when the PHY chip receives data, comparing the sent arbitration serial number with the arbitration serial number returned by the arbitration bus, and feeding back the comparison result to the Ethernet chip when the Ethernet chip inquires the arbitration result of each PHY chip through the station management interface bus.
10. An ethernet chip comprising a memory and a processor, said memory having stored thereon a computer program which, when executed by said processor, is adapted to implement the ethernet multi-physical interface control communication method of any of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311254485.2A CN117221252A (en) | 2023-09-26 | 2023-09-26 | Multi-physical interface control communication method and system of Ethernet and Ethernet chip |
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| CN202311254485.2A CN117221252A (en) | 2023-09-26 | 2023-09-26 | Multi-physical interface control communication method and system of Ethernet and Ethernet chip |
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| US20040252641A1 (en) * | 2003-06-12 | 2004-12-16 | Bagchi Amit G. | Classifier for IEEE 802.11g receiver |
| CN101442563A (en) * | 2008-12-17 | 2009-05-27 | 杭州华三通信技术有限公司 | Data communication method and Ethernet equipment |
| CN109600457A (en) * | 2019-01-28 | 2019-04-09 | 伟乐视讯科技股份有限公司 | A kind of the PHY-MAC interface control unit and method of up to one mapping |
| CN116561150A (en) * | 2023-07-06 | 2023-08-08 | 苏州浪潮智能科技有限公司 | Cache updating method, device, equipment and readable storage medium |
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| US20040252641A1 (en) * | 2003-06-12 | 2004-12-16 | Bagchi Amit G. | Classifier for IEEE 802.11g receiver |
| CN101442563A (en) * | 2008-12-17 | 2009-05-27 | 杭州华三通信技术有限公司 | Data communication method and Ethernet equipment |
| CN109600457A (en) * | 2019-01-28 | 2019-04-09 | 伟乐视讯科技股份有限公司 | A kind of the PHY-MAC interface control unit and method of up to one mapping |
| CN116561150A (en) * | 2023-07-06 | 2023-08-08 | 苏州浪潮智能科技有限公司 | Cache updating method, device, equipment and readable storage medium |
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