CN117220815A - Clock adjustment method, device, equipment and medium - Google Patents
Clock adjustment method, device, equipment and medium Download PDFInfo
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Abstract
The application discloses a clock adjustment method, a device, equipment and a medium, comprising the following steps: receiving a synchronous message sent by a master clock device, and analyzing a time value which is required to be adjusted by the master clock device from the synchronous message to obtain a first time value; determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device; and determining a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency controller, and adjusting the clock frequency of the clock frequency controller to the new clock frequency. Therefore, the frequency offset and the time value offset can be comprehensively considered, the master clock device and the slave clock device are aligned in time correction, and meanwhile, the time value in the slave clock device is prevented from jumping, so that the normal operation of the slave clock device is ensured.
Description
Technical Field
The present application relates to the field of network communications technologies, and in particular, to a clock adjustment method, apparatus, device, and medium.
Background
TSN (i.e., time Sensitive Networking, time sensitive network) networks can provide deterministic performance for ethernet networks to meet the low latency, low jitter, high reliability, etc. requirements of transmission networks for industrial automation, internet of vehicles, etc. applications. Clock synchronization is a precondition for a TSN network to implement deterministic transmission, and many functions of the TSN network are based on clock synchronization.
At present, when the TSN network performs clock synchronization, when the slave clock device adjusts the time value, if there is a large offset between the value to be adjusted and the actual value of the slave clock, if the slave clock device directly adjusts the time value, the time value of the slave clock device will jump. The jump in time value may cause some functions in the slave clock device to not run (jump to the future) or some functions to run repeatedly (reverse time to the past), affecting the normal operation of the slave clock device.
Disclosure of Invention
Accordingly, the present application aims to provide a clock adjustment method, apparatus, device and medium, which can align the master clock device and the slave clock device in time, and avoid time value jump in the slave clock device, so as to ensure normal operation of the slave clock device. The specific scheme is as follows:
in a first aspect, the present application discloses a clock adjustment method, which is applied to a slave clock device in a TSN network, including:
receiving a synchronous message sent by a master clock device, and analyzing a time value which is required to be adjusted by the master clock device from the synchronous message to obtain a first time value;
determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device;
and determining a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency controller, and adjusting the clock frequency of the clock frequency controller to the new clock frequency.
Optionally, determining the frequency offset control factor based on the current actual time value of the frequency offset control factor and the first time value includes:
reading a second time value and a third time value; the second time value is a time value which is analyzed from the last synchronous message and is adjusted by the self, and the third time value is an actual time value of the self when the last synchronous message is received;
and determining a frequency offset control factor based on the current actual time value, the first time value, the second time value and the third time value.
Optionally, determining the frequency offset control factor based on the current actual time value, the first time value, the second time value and the third time value includes:
determining a difference between the first time value and the second time value to obtain a first difference;
determining a difference value between the current actual time value and the third time value to obtain a second difference value;
and determining the ratio between the first difference value and the second difference value to obtain a frequency offset control factor.
Optionally, determining the time offset control factor based on the current actual time value of the time offset control factor and the first time value includes:
determining the time value offset between the master clock device and the slave clock device based on the current actual time value and the first time value;
a time offset control factor is determined based on the time value offset.
Optionally, determining the time offset control factor based on the current actual time value of the time offset control factor and the first time value includes:
calculating a time offset control factor by using a preset formula; the preset formula is as follows:
wherein r is 2 Is a time offset control factor, t c For the first time value, t L T is the current actual time value of the self c -t L Is the time value offset between the master and slave clock devices.
Optionally, after analyzing the time value to be adjusted from the synchronization message to obtain the first time value, the method further includes:
and recording the first time value and the current actual time value of the first time value.
Optionally, before adjusting the clock frequency of the clock generator to the new clock frequency, the method further includes:
judging whether the current clock frequency of the clock is equal to the new clock frequency or not;
and triggering the step of adjusting the own clock frequency to the new clock frequency if the current clock frequency of the own clock frequency is not equal to the new clock frequency.
In a second aspect, the present application discloses a clock adjustment device, applied to a slave clock device in a TSN network, comprising:
the synchronous message receiving module is used for: receiving a synchronous message sent by a master clock device;
the synchronous message analysis module is used for analyzing the time value which is required to be adjusted from the synchronous message to obtain a first time value;
the control factor determining module is used for determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device;
the clock frequency determining module is used for determining a new clock frequency by utilizing the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency determining module;
and the clock frequency adjusting module is used for adjusting the clock frequency of the clock frequency adjusting module to the new clock frequency.
In a third aspect, the application discloses an electronic device comprising a processor and a memory; wherein,
the memory is used for storing a computer program;
the processor is configured to execute the computer program to implement the foregoing clock adjustment method.
In a fourth aspect, the present application discloses a computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the aforementioned clock adjustment method.
It can be seen that the present application is applied to a slave clock device in a TSN network, receives a synchronization packet sent by a master clock device, and analyzes a time value to which the slave clock device should adjust from the synchronization packet to obtain a first time value, then determines a frequency offset control factor based on a current actual time value of the slave clock device and the first time value, and a time offset control factor, where the frequency offset control factor reflects an offset condition of a clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects an offset condition of a time value between the master clock device and the slave clock device, and then determines a new clock frequency by using the frequency offset control factor, the time offset control factor, and the current clock frequency of the slave clock device, and adjusts the clock frequency of the slave clock device to the new clock frequency. That is, when clock synchronization is periodically performed between master clock devices and slave clock devices in the TSN network, the application comprehensively considers frequency offset and time value offset, and does not directly adjust the time value, but adjusts the clock frequency and the time value simultaneously by adjusting the clock frequency, so that the master clock device and the slave clock device can be aligned in time, and the time value in the slave clock device is prevented from jumping, thereby ensuring the normal operation of the slave clock device.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of TSN network clock synchronization according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the internal of a slave clock device according to an embodiment of the present application;
FIG. 3 is a flowchart of a clock adjustment method according to an embodiment of the present application;
FIG. 4 is a flowchart of a specific clock adjustment method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a clock adjustment device according to an embodiment of the present application;
fig. 6 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The TSN is originally derived from application requirements in the field of Audio and Video, and then the technology is called AVB (Ethernet Audio/Video Bridging), and can be used for better transmitting high-quality Audio and Video by means of the AVB according to requirements of an Audio and Video network such as higher bandwidth, maximum real-time performance and the like. The application requirement and the application range of the time deterministic Ethernet are enlarged, the time deterministic Ethernet is evolved into TSN, the TSN can provide deterministic performance for the Ethernet, and the time deterministic Ethernet is essentially a deterministic Ethernet expansion set so as to meet the requirements of low delay, low jitter, high reliability and the like of a transmission network in industrial automation, internet of vehicles and other applications. Clock synchronization is a precondition for a TSN network to achieve deterministic transmission, and many functions of the TSN network are based on clock synchronization, which uses the ieee802.1as protocol to provide clock synchronization functions for a domain in the network. The main contents of the ieee802.1as clock synchronization are: a plurality of domains are partitioned in the network, and each domain determines the master clock device by means of static configuration or election. The election master clock device adopts BMCA (Best Master Clock Algorithm, optimal master clock algorithm), and selects the optimal parameter according to the parameters of each clock device in the domain as the master clock device. After determining the master clock device by static configuration or election, other clock devices are slave clock devices, and the slave clock devices periodically and the master clock device perform timing to update the clock frequency and time value of the slave clock devices, so as to realize clock synchronization among network nodes, as shown in fig. 1, fig. 1 is a schematic diagram of TSN network clock synchronization provided by the application, including slave clock devices 1 to 4.
At present, when the slave clock device adjusts the time value, if there is a large offset between the value to be adjusted and the actual value of the slave clock, the time value of the slave clock device will jump, and the jump of the time value may cause some functions in the slave clock device not to operate (jump to the future) or some functions to repeatedly operate (reverse to the past), so as to affect the normal operation of the slave clock device, as shown in fig. 2, fig. 2 is an internal schematic diagram of the slave clock device provided in the embodiment of the application. Therefore, the application provides a clock adjustment scheme which is suitable for a scene that slave clock equipment in a TSN adjusts a local clock when the clocks are synchronous. The master clock device and the slave clock device can be aligned in time correction, and meanwhile, time value jump in the slave clock device is avoided, so that normal operation of the slave clock device is guaranteed.
The slave clock in the present application refers to a local clock in the slave clock device, and referring to fig. 2, for convenience of description, different expressions may be used.
Referring to fig. 3, an embodiment of the present application discloses a clock adjustment method applied to a slave clock device in a TSN network, including:
step S11: and receiving a synchronous message sent by the master clock device, and analyzing a time value which is required to be adjusted by the master clock device from the synchronous message to obtain a first time value.
The embodiment of the application can adopt IEEE802.1AS protocol to carry out clock synchronization, and the master clock device can obtain the path transmission delay between the slave clock device and the master clock device by sending the delay measurement message. The master clock device takes the sum of the path transmission delay and the clock value of the master clock device as the time value which the slave clock device should adjust to, and the time value which the slave clock device should adjust to is carried to the slave clock device through a synchronous message. The slave clock equipment receives the synchronous message sent by the master clock equipment, further analyzes the message to obtain a time value which is a first time value and is adjusted by the slave clock equipment, and then locally records the first time value and reads the current actual time value of the slave clock equipment. It can be understood that in the embodiment of the present application, the synchronization message sent by the master clock device is received periodically, that is, steps S11 to S13 are performed every period.
Step S12: determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device.
In the embodiment of the present application, the step of determining the frequency offset control factor may specifically include: reading a second time value and a third time value; the second time value is a time value which is analyzed from the last synchronous message and is adjusted by the self, and the third time value is an actual time value of the self when the last synchronous message is received; and determining a frequency offset control factor based on the current actual time value, the first time value, the second time value and the third time value. Wherein the second time value and the third time value may be read from the local record.
And, in a specific embodiment, a difference between the first time value and the second time value may be determined to obtain a first difference; determining a difference value between the current actual time value and the third time value to obtain a second difference value; and determining the ratio between the first difference value and the second difference value to obtain a frequency offset control factor. The formula used may be:
wherein r is 1 Is a frequency offset control factor, t c For the first time value, t' c For the second time value, t L Is the current actual time value of the self, t' L Is a third time value. It should be noted that the clock frequency is a characteristic of clock crystal, and the crystal oscillation speed is different, and the timing times are different. The ratio of the different clock frequencies can be calculated by the ratio of the durations.
In the embodiment of the application, the time value offset between the master clock device and the slave clock device can be determined based on the current actual time value and the first time value; a time offset control factor is determined based on the time value offset. In a specific embodiment, the time offset control factor may be calculated using a preset formula; the preset formula is as follows:
wherein r is 2 Is a time offset control factor, t c For the first time value, t L T is the current actual time value of the self c -t L Is the time value offset between the master and slave clock devices.
Step S13: and determining a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency controller, and adjusting the clock frequency of the clock frequency controller to the new clock frequency.
The embodiment of the application can obtain a new clock frequency by calculating the product of the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency. I.e. in combination with the local current actual clock frequency f L A new clock frequency f is calculated: f=f L ×r 1 ×r 2 。
Before adjusting the clock frequency of the clock to the new clock frequency, the embodiment of the application also judges whether the current clock frequency of the clock is equal to the new clock frequency; and triggering the step of adjusting the own clock frequency to the new clock frequency if the current clock frequency of the own clock frequency is not equal to the new clock frequency. If the current clock frequency of the self is equal to the new clock frequency, the step of adjusting the self clock frequency to the new clock frequency is not triggered,
it can be seen that the embodiment of the present application is applied to a slave clock device in a TSN network, receives a synchronization packet sent by a master clock device, and analyzes a time value to which the slave clock device should adjust from the synchronization packet to obtain a first time value, then determines a frequency offset control factor based on a current actual time value of the slave clock device and the first time value, and a time offset control factor, where the frequency offset control factor reflects an offset condition of a clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects an offset condition of a time value between the master clock device and the slave clock device, and then determines a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the slave clock device, and adjusts the clock frequency of the slave clock device to the new clock frequency. That is, when clock synchronization is periodically performed between master clock devices and slave clock devices in the TSN network, the embodiment of the application comprehensively considers frequency offset and time value offset, and does not directly adjust the time value, but adjusts the clock frequency and the time value simultaneously by adjusting the clock frequency, so that the master clock device and the slave clock device can be aligned in time correction, and jump of the time value in the slave clock device is avoided, thereby ensuring normal operation of the slave clock device.
Further, referring to fig. 4, fig. 4 is a flowchart of a specific clock adjustment method disclosed in an embodiment of the present application. Analyzing the synchronous message to obtain a time value to be adjusted, recording the time value in the local, calculating a frequency offset control factor and a time offset control factor, further calculating a local new clock frequency, and then adjusting the local clock frequency, wherein the method specifically comprises the following steps of:
at the beginning, clock synchronization is periodically carried out between master clock equipment and slave clock equipment in a TSN (time division multiple access) network according to IEEE802.1AS (institute of Electrical and electronics Engineers) protocol, and the master clock equipment sends a clock synchronization message to the slave clock equipment, wherein the clock synchronization message is carried in the synchronization messageWith time value t to which slave clock device should adjust c . After receiving the synchronous message from the clock, analyzing the message to obtain the time value t to be adjusted c And saves the value record locally. The actual time value of the slave clock is t L And storing the value record locally, the current actual clock frequency of the slave clock is f L . After the time value to be adjusted is analyzed from the clock, the frequency offset control factor r is calculated by combining the actual time value 1 The values of (2) are:
wherein t' c Is the time value t 'which is carried in the last clock synchronization message and is adjusted by the slave clock' L Is the actual time value of the slave clock device at the last clock synchronization. The numerator is the duration of the master clock device in the two-time synchronization interval, the denominator is the duration of the slave clock device in the two-time synchronization interval, and the ratio of the two is the ratio of the master clock frequency to the slave clock frequency, thus reflecting the deviation condition of the master clock frequency and the slave clock frequency.
Then, the slave clock device calculates a time offset control factor r according to the time value to be adjusted and the local actual time value 2 The values of (2) are:
calculating r from clock device 1 And r 2 After combining the values of the local current actual clock frequency f L Calculating a new clock frequency f having a value f=f L ×r 1 ×r 2 . After calculating the new clock frequency value, the slave clock device adjusts the value of its own clock frequency to the new clock frequency value.
Each time the clocks are synchronized, the above steps are performed. In this way, by calculating the frequency offset control factor and the time offset control factor in the slave clock device, the frequency offset and the time value offset are comprehensively considered, a new slave clock frequency is calculated, and the current actual frequency of the slave clock is adjusted to the new frequency, without adjusting the time value of the slave clock device. The slave clock equipment time value can be adjusted while the frequency of the slave clock equipment is adjusted, so that the time value of the slave clock equipment is prevented from jumping, and the normal operation of other functions of the slave clock equipment is ensured.
Further, in one embodiment, initially, the TSN network master-slave clock devices have a time value of 0. The master clock device and the slave clock device periodically perform clock synchronization according to the IEEE802.1AS protocol, and after the master clock device runs for a period of time, the master clock device sends a clock synchronization message to the slave clock, wherein the synchronization message carries a time value which the slave clock device should adjust to be 10. After receiving the synchronous message from the clock device, the synchronous message is analyzed to obtain the time value which is adjusted to be 10, and the value record is stored locally. The actual time value of the slave clock device read itself is 8, and the clock frequency is 0.8. That is, the slave clock device is delayed in time from the master clock device, and if the slave clock device directly adjusts the time value to 10, the time value jumps, the time value 9 is lost, and other functions that originally need to be executed at the time value 9 in the slave clock device are not executed. Therefore, the time value is not directly adjusted. The slave clock equipment calculates a frequency conversion factor r according to the analyzed time value to be adjusted and the local actual time value 1 Has a value r of 1 = (10-0)/(8-0) =1.25. Then, the slave clock device calculates a time offset control factor r according to the time value to be adjusted and the local actual time value 2 Has a value r of 2 =1+ (10-8)/10=1.2. Calculating r from clock device 1 And r 2 After the value of f, the new clock frequency f is calculated as f=0.8×1.25×1.2=1.2, in combination with the value of 0.8 of the local current actual clock frequency. After the slave clock device calculates the new clock frequency value, the slave clock device adjusts its own frequency value to the new clock frequency value of 1.2.
Along with the continuous operation of the TSN network, the second clock synchronization starts, the synchronization message reaches the slave clock equipment, and the time value to be adjusted by the slave clock equipment carried in the synchronization message is 20. In the second synchronization periodThe slave clock has a clock frequency of 1.2, and the time value increases faster than in the first synchronization period during the same time interval. When the slave clock device receives the second clock synchronization message, its own actual time value is 20. The slave clock device uses the same calculation mode to calculate r 1 Has a value r of 1 ＝(20-10)/(20-8)＝5/6，r 2 Has a value r of 2 =1+ (20-20)/20=1, then the new clock frequency f has a value of f=1.2× (5/6) ×1=1. When the clock synchronization message is received for the second time, after the new clock frequency value is calculated from the clock equipment, the clock frequency value is adjusted to be 1. The clock frequency and the time value between the slave clock device and the master clock device are kept strictly consistent, and the master clock and the slave clock are always in an aligned state when the clocks are synchronized every time later.
In another embodiment, the master clock device sends a clock synchronization message to the slave clock, where the synchronization message carries a time value 8 to which the slave clock device should adjust. The actual time value of itself is read from the clock device as 10 and the value record is kept locally, with a clock frequency of 1. That is, the slave clock device is advanced in time relative to the master clock device, and if the slave clock directly adjusts the time value to 8, the slave clock will reverse the time value, repeat the time values 8, 9 and 10, and the other functions originally required to be executed in the slave clock device at the time values 8, 9 and 10 will be repeatedly executed. Therefore, the time value is not directly adjusted. Calculating a frequency conversion factor r from a clock device 1 Time offset control factor r 2 The new clock frequency f has the values: r is (r) 1 ＝(8-0)/(10-0)＝0.8；r 2 ＝1+(8-10)/8＝1-0.25＝0.75；f＝1×0.8×0.75＝0.6；
And starting the second clock synchronization, wherein the synchronization message reaches the slave clock, and the time value to which the slave clock carried in the synchronization message is adjusted is 16. In the second synchronization period, the clock frequency of the slave clock device is 0.6, and the time value increases at a slower rate than in the first synchronization period during the same time interval. When the slave clock device receives the second clock synchronization message, its own actual time value is 16. Second calculation of frequency conversion from clock deviceFactor r 1 Time offset control factor r 2 The new clock frequency f has the values: r is (r) 1 ＝(16-8)/(16-10)＝4/3；r 2 ＝1+(16-16)/16＝1；f＝0.6×(4/3)×1＝0.8。
According to the scheme described in the embodiment, the frequency offset and the time value offset between the master clock and the slave clock are comprehensively considered, the time value is not directly adjusted, and the slave clock is enabled to quickly or slowly reach the state aligned with the master clock by adjusting the frequency speed of the slave clock, so that the consistency between the master clock and the slave clock in frequency and time value is realized, the master clock is the local clock of the master clock device, and the slave clock is the local clock of the slave clock device.
Referring to fig. 5, an embodiment of the present application discloses a clock adjustment device, which is applied to a slave clock device in a TSN network, and includes:
the synchronous message receiving module 11 is configured to: receiving a synchronous message sent by a master clock device;
the synchronous message parsing module 12 is configured to parse a time value to be adjusted from the synchronous message to obtain a first time value;
a control factor determining module 13, configured to determine a frequency offset control factor and a time offset control factor based on a current actual time value of the control module itself and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device;
a clock frequency determining module 14, configured to determine a new clock frequency by using the frequency offset control factor, the time offset control factor, and a current clock frequency of the clock frequency determining module;
the clock frequency adjusting module 15 is configured to adjust its own clock frequency to the new clock frequency.
It can be seen that the embodiment of the present application is applied to a slave clock device in a TSN network, receives a synchronization packet sent by a master clock device, and analyzes a time value to which the slave clock device should adjust from the synchronization packet to obtain a first time value, then determines a frequency offset control factor based on a current actual time value of the slave clock device and the first time value, and a time offset control factor, where the frequency offset control factor reflects an offset condition of a clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects an offset condition of a time value between the master clock device and the slave clock device, and then determines a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the slave clock device, and adjusts the clock frequency of the slave clock device to the new clock frequency. That is, when clock synchronization is periodically performed between master clock devices and slave clock devices in the TSN network, the embodiment of the application comprehensively considers frequency offset and time value offset, and does not directly adjust the time value, but adjusts the clock frequency and the time value simultaneously by adjusting the clock frequency, so that the master clock device and the slave clock device can be aligned in time correction, and jump of the time value in the slave clock device is avoided, thereby ensuring normal operation of the slave clock device.
The control factor determining module 13 specifically includes a frequency offset control factor determining sub-module and a time offset control factor determining sub-module, wherein,
the frequency offset control factor determining submodule specifically includes:
the time value reading unit is used for reading the second time value and the third time value; the second time value is a time value which is analyzed from the last synchronous message and is adjusted by the self, and the third time value is an actual time value of the self when the last synchronous message is received;
and the frequency offset control factor determining unit is used for determining a frequency offset control factor based on the current actual time value, the first time value, the second time value and the third time value.
Further, the frequency offset control factor determining unit is specifically configured to determine a difference between the first time value and the second time value to obtain a first difference; determining a difference value between the current actual time value and the third time value to obtain a second difference value; and determining the ratio between the first difference value and the second difference value to obtain a frequency offset control factor.
The time offset control factor determining submodule is specifically used for determining time value offset between the master clock device and the slave clock device based on the current actual time value and the first time value; a time offset control factor is determined based on the time value offset. In a specific embodiment, the time offset control factor is calculated by using a preset formula; the preset formula is as follows:
wherein r is 2 Is a time offset control factor, t c For the first time value, t L T is the current actual time value of the self c -t L Is the time value offset between the master and slave clock devices.
Further, the device also comprises a recording module for recording the first time value and the current actual time value of the device.
And, the apparatus further comprises:
the judging module is used for judging whether the current clock frequency of the judging module is equal to the new clock frequency; and triggering the step of adjusting the own clock frequency to the new clock frequency if the current clock frequency of the own clock frequency is not equal to the new clock frequency.
Referring to fig. 6, an embodiment of the present application discloses an electronic device 20 comprising a processor 21 and a memory 22; wherein the memory 22 is used for storing a computer program; the processor 21 is configured to execute the computer program and the clock adjustment method disclosed in the foregoing embodiments.
For the specific process of the clock adjustment method, reference may be made to the corresponding content disclosed in the foregoing embodiment, and no further description is given here.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk or an optical disk, and the storage mode may be transient storage or permanent storage.
In addition, the electronic device 20 further includes a power supply 23, a communication interface 24, an input-output interface 25, and a communication bus 26; wherein the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
Further, the embodiment of the application also discloses a computer readable storage medium for storing a computer program, wherein the computer program realizes the clock adjustment method disclosed in the previous embodiment when being executed by a processor.
For the specific process of the clock adjustment method, reference may be made to the corresponding content disclosed in the foregoing embodiment, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed description of a clock adjustment method, device, apparatus and medium provided by the present application applies specific examples to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A method of clock adjustment, for use with a slave clock device in a TSN network, comprising:
receiving a synchronous message sent by a master clock device, and analyzing a time value which is required to be adjusted by the master clock device from the synchronous message to obtain a first time value;
determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device;
and determining a new clock frequency by using the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency controller, and adjusting the clock frequency of the clock frequency controller to the new clock frequency.
2. The clock adjustment method according to claim 1, wherein determining a frequency offset control factor based on the first time value and a current actual time value thereof, comprises:
reading a second time value and a third time value; the second time value is a time value which is analyzed from the last synchronous message and is adjusted by the self, and the third time value is an actual time value of the self when the last synchronous message is received;
and determining a frequency offset control factor based on the current actual time value, the first time value, the second time value and the third time value.
3. The clock adjustment method according to claim 2, wherein determining a frequency offset control factor based on the own current actual time value, the first time value, the second time value, and the third time value, comprises:
determining a difference between the first time value and the second time value to obtain a first difference;
determining a difference value between the current actual time value and the third time value to obtain a second difference value;
and determining the ratio between the first difference value and the second difference value to obtain a frequency offset control factor.
4. The clock adjustment method according to claim 1, wherein determining a time offset control factor based on the first time value and a current actual time value thereof, comprises:
determining the time value offset between the master clock device and the slave clock device based on the current actual time value and the first time value;
a time offset control factor is determined based on the time value offset.
5. The clock adjustment method according to claim 4, wherein determining a time offset control factor based on the first time value and a current actual time value thereof, comprises:
calculating a time offset control factor by using a preset formula; the preset formula is as follows:
wherein r is 2 Is a time offset control factor, t c For the first time value, t L T is the current actual time value of the self c -t L Is the time value offset between the master and slave clock devices.
6. The clock adjustment method according to claim 1, further comprising, after analyzing a time value to be adjusted by itself from the synchronization message to obtain a first time value:
and recording the first time value and the current actual time value of the first time value.
7. The clock adjustment method according to any one of claims 1 to 6, characterized by further comprising, before adjusting the own clock frequency to the new clock frequency:
judging whether the current clock frequency of the clock is equal to the new clock frequency or not;
and triggering the step of adjusting the own clock frequency to the new clock frequency if the current clock frequency of the own clock frequency is not equal to the new clock frequency.
8. A clock adjustment apparatus for use with a slave clock device in a TSN network, comprising:
the synchronous message receiving module is used for: receiving a synchronous message sent by a master clock device;
the synchronous message analysis module is used for analyzing the time value which is required to be adjusted from the synchronous message to obtain a first time value;
the control factor determining module is used for determining a frequency offset control factor and a time offset control factor based on the current actual time value and the first time value; the frequency offset control factor reflects the offset condition of the clock frequency between the master clock device and the slave clock device, and the time offset control factor reflects the offset condition of the time value between the master clock device and the slave clock device;
the clock frequency determining module is used for determining a new clock frequency by utilizing the frequency offset control factor, the time offset control factor and the current clock frequency of the clock frequency determining module;
and the clock frequency adjusting module is used for adjusting the clock frequency of the clock frequency adjusting module to the new clock frequency.
9. An electronic device comprising a processor and a memory; wherein,
the memory is used for storing a computer program;
the processor is configured to execute the computer program to implement the clock adjustment method according to any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the clock adjustment method according to any one of claims 1 to 7.
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| CN202311310338.2A CN117220815A (en) | 2023-10-10 | 2023-10-10 | Clock adjustment method, device, equipment and medium |
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| CN202311310338.2A CN117220815A (en) | 2023-10-10 | 2023-10-10 | Clock adjustment method, device, equipment and medium |
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