CN117220814A - Clock device synchronization method, nonvolatile storage medium, and electronic device - Google Patents

Abstract

The application discloses a clock device synchronization method, a nonvolatile storage medium and an electronic device. Wherein the method comprises the following steps: under the condition that a first main Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches a first main BFD session state from a first state to a second state; the first clock device switches the master clock frequency state of the first clock device according to the first master BFD session state, and the packet sending frequency level of the first clock device is increased from the first level to the second level; and under the condition that the duration that the packet sending frequency grade of the first clock equipment continues to the second grade reaches the first preset duration, if the current clock frequency state is the initial state of the main clock frequency of the first clock equipment, reducing the packet sending frequency of the first clock equipment. The application solves the technical problem of untimely clock equipment synchronization caused by slow clock equipment link switching.

Description

Clock device synchronization method, nonvolatile storage medium, and electronic device

Technical Field

The present application relates to the field of network technology and security, and in particular, to a clock device synchronization method, a nonvolatile storage medium, and an electronic device.

Background

The clock synchronization method of the networking clock module mainly uses an accurate time protocol (Precision Time Protocol, PTP) and a synchronous Ethernet (Synchronous Ethernet, syncE) to cooperate, wherein frequency synchronization is a basis, and time synchronization is performed on the basis of the frequency synchronization, so that the networking ensures nanosecond high-precision clock synchronization under the phase synchronization of the frequency synchronization.

In the related time synchronization technology, by judging the quality grade of a synchronization status message (Synchronous Status Message, SSM) of an ethernet service multiplexing capability (Ethernet Service Multiplexing Capability, ESMC) message received by a clock device, when the SSM grade changes, a downstream device changes the clock source of the local device according to the SSM grade, so as to inform the downstream device of the local device to also make the clock source. In the above technology, the link switching of the clock device is slower, which results in the problems of untimely synchronization of the clock device and the like.

In view of the above problems, no effective solution has been proposed at present.

Disclosure of Invention

The embodiment of the application provides a clock equipment synchronization method, a nonvolatile storage medium and electronic equipment, which are used for at least solving the technical problem of untimely clock equipment synchronization caused by slow clock equipment link switching.

According to an aspect of an embodiment of the present application, there is provided a synchronization method of a clock device, including: under the condition that a first main Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches the state of the first main BFD session from a first state to a second state, and switches the session of the first clock device and the second clock device to a first standby BFD session; the method comprises the steps that a first clock device switches a main clock frequency state of the first clock device according to a first main BFD session state, the packet sending frequency level of the first clock device is improved to a second level from the first level, a first target message carrying the packet sending frequency level is sent to a second clock device, the packet sending frequency corresponding to the second level is larger than the packet sending frequency corresponding to the first level, a second frequency synchronization module corresponding to the second clock device is used for switching the main clock frequency state of the second clock device according to the first main BFD session state, and switching a standby clock frequency state of the second clock device according to the received first target message; and under the condition that the duration that the packet sending frequency grade of the first clock equipment continues to the second grade reaches the first preset duration, if the current clock frequency state is the initial state of the main clock frequency of the first clock equipment, reducing the packet sending frequency of the first clock equipment.

Optionally, the first clock device switches the active clock frequency state of the first clock device according to the first active BFD session state, including: and switching the main clock frequency state of the first clock device from a third state to a fourth state, wherein the third state is used for representing that the main clock frequency is an initial state, and the fourth state is used for representing that the main clock signal corresponding to the main clock frequency is a lost state.

Optionally, if the current clock frequency state is the third state, the packet sending frequency of the first clock device is kept at the first level under the condition that the duration of the packet sending frequency level of the first clock device lasting the first level reaches the second preset duration.

Optionally, under the condition that the first primary BFD session and the first standby BFD session of the first clock device are disconnected from the first primary BFD session and the first standby BFD session of the second clock device, the primary clock frequency state and the standby clock frequency state of the first clock device are switched, and the packet sending frequency level of the first clock device to the third clock device is promoted, where the first clock device is respectively in communication connection with the second clock device and the third clock device, the second clock device is in communication connection with the fourth clock device, the second clock device is configured to switch the primary clock frequency state and the standby clock frequency state of the second clock device according to the first primary BFD session state, respectively, and promote the packet sending frequency level of the second clock device to the fourth clock device, and the fourth clock device is configured to switch the clock frequency state of the fourth clock device according to the received second target packet sent by the second clock device, where the second target packet includes: the second clock device sends the packet frequency level to the fourth clock device, and the fourth clock device is further used for communicating with the third clock device according to the received third target message sent by the third clock device, and switching the clock frequency state of the fourth clock device.

Optionally, when the first primary BFD session and the first standby BFD session of the first clock device and the second clock device are both disconnected, switching the primary clock frequency status and the standby clock frequency status of the first clock device, and increasing the packet sending frequency level of the first clock device to the third clock device, including: and under the condition that the first main BFD session and the first standby BFD session of the first clock device and the second clock device are disconnected, switching the main clock frequency state of the first clock device from the third state to the fourth state, and increasing the packet sending frequency of the first clock device to the third clock device from the first level to the second level.

According to still another aspect of the embodiment of the present application, there is also provided a synchronization method of a clock device, including: under the condition that a second clock device is disconnected from a first main Bidirectional Forwarding Detection (BFD) session of a first clock device, the state of the first main BFD session is switched from a first state to a second state, and the session of the second clock device and the first clock device is switched to a first standby BFD session; the second clock device switches the master clock frequency state of the second clock device according to the first master BFD session state and switches the standby clock frequency state of the second clock device according to the received first target message, wherein the first frequency synchronization module corresponding to the first clock device is used for switching the master clock frequency state of the first clock device according to the first master BFD session state, increasing the packet sending frequency of the first clock device from the first level to the second level, and sending the first target message carrying the packet sending frequency level to the second clock device.

Optionally, the second clock device switches the master clock frequency status of the second clock device according to the first master BFD session status, and switches the standby clock frequency status of the second clock device according to the received first target message, including: switching the master clock frequency state of the second clock device from the fifth state to the third state; the standby clock frequency state of the second clock device is switched from the third state to the sixth state.

Optionally, under the condition that the second clock device is disconnected from both the first primary BFD session and the first standby BFD session of the first clock device, the second clock device switches the primary clock frequency state and the standby clock frequency state of the second clock device according to the first primary BFD session state, and promotes a packet sending frequency level of the second clock device to the fourth clock device, where the second clock device is communicatively connected with the first clock device and the fourth clock device, the fourth clock device is configured to switch the clock frequency state of the fourth clock device according to the received second target message sent by the second clock device, and the second target message includes: the second clock device sends a packet to the fourth clock device, and the fourth clock device is further configured to communicate with the third clock device according to the received third target packet sent by the third clock device, and switch the clock frequency state of the fourth clock device.

Optionally, the second clock device switches the primary clock frequency state and the standby clock frequency state of the second clock device according to the first primary BFD session state, and promotes a packet sending frequency level from the second clock device to the fourth clock device, including: switching the master clock frequency state of the second clock device from the sixth state to the fourth state; switching the standby clock frequency state of the second clock device from the fifth state to the fourth state; the frequency of the packet sent from the second clock device to the fourth clock device is increased from the first level to the second level.

According to still another aspect of the embodiments of the present application, there is also provided a nonvolatile storage medium, the storage medium including a stored program, wherein the program controls a device in which the storage medium is located to execute the above method of synchronizing a clock device when running.

According to still another aspect of the embodiment of the present application, there is also provided an electronic device including: the device comprises a memory and a processor, wherein the processor is used for running a program stored in the memory, and the program runs to execute the synchronization method of the clock device.

In the embodiment of the application, when a first primary Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches the state of the first primary BFD session from a first state to a second state, and switches the session of the first clock device and the second clock device to a first standby BFD session; the method comprises the steps that a first clock device switches a main clock frequency state of the first clock device according to a first main BFD session state, the packet sending frequency level of the first clock device is improved to a second level from the first level, a first target message carrying the packet sending frequency level is sent to a second clock device, the packet sending frequency corresponding to the second level is larger than the packet sending frequency corresponding to the first level, a second frequency synchronization module corresponding to the second clock device is used for switching the main clock frequency state of the second clock device according to the first main BFD session state, and switching a standby clock frequency state of the second clock device according to the received first target message; under the condition that the duration of the continuous second level of the packet sending frequency level of the first clock device reaches the first preset duration, if the current clock frequency state is the initial state of the main clock frequency of the first clock device, the packet sending frequency of the first clock device is reduced, and the packet sending frequency of the clock device corresponding to the frequency synchronization module is adjusted according to the state of the BFD session, so that the purpose of quickly sensing the abnormal link is achieved, the technical effect of timely synchronization of the clock device is achieved, and the technical problem of untimely synchronization of the clock device caused by slow link switching of the clock device is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic diagram of a master-slave clock device switch according to the related art;

FIG. 2 is a flow chart of a method of synchronizing clock devices according to an embodiment of the application;

FIG. 3 is a flow chart of another method of synchronizing clock devices according to an embodiment of the application;

FIG. 4 is a schematic diagram of a method of synchronizing clock devices according to an embodiment of the application;

fig. 5 is a block diagram of a hardware configuration of a computer terminal (or electronic device) of a synchronization method of a clock device according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of switching between a master clock device and a slave clock device according to the related art, as shown in fig. 1, in the case that the main link AB1 is broken, the clock device B cannot switch to the AB2 link in time, so that the clock precision is greatly dithered, and in addition, the clock device D is affected by the clock device B, which also has the problem of poor synchronization precision. Under the condition that both the main link AB1 and the standby link AB2 are broken, the clock equipment D still recovers the clock from the clock equipment B, so that the lock is lost, and the clock synchronization of the whole network is further affected. Namely, the technology only judges the SSM quality grade of the ESMC message received by the clock equipment, when the SSM grade changes, the downstream equipment changes the clock source selection of the local equipment according to the SSM grade, and further informs the downstream equipment of the local equipment to also make the clock source selection and the clock free keeping action. This technique has the following problems:

1. The local equipment cannot efficiently and timely sense the failure of the link of the local equipment:

(1) Under the condition that the local terminal equipment is a main and standby link, the main and standby clock switching cannot be timely made at the local terminal equipment, and the downstream equipment cannot realize the non-perception local terminal link switching;

(2) Under the condition that the local end equipment is a single link, the downstream equipment cannot be informed that the local end clock is unavailable in time, and the quality grade of the local end clock cannot be output to the downstream equipment in time.

ESMC protocol specifies that the packet-sending frequency of ESMC messages is one per second, and downstream devices cannot timely sense the change of SSM clock quality level.

In order to solve the above problems, related solutions are provided in the embodiments of the present application, and are described in detail below.

According to an embodiment of the present application, there is provided a method embodiment of a synchronization method of a clock device, it should be noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in an order different from that herein.

Fig. 2 is a flowchart of a method for synchronizing clock devices according to an embodiment of the present application, as shown in fig. 2, the method including the steps of:

In step S202, when the first primary bidirectional forwarding detection BFD session of the first clock device and the second clock device is disconnected, the first clock device switches the first primary BFD session state from the first state to the second state, and switches the session of the first clock device and the second clock device to the first standby BFD session.

In the event that the first primary BFD session of the first clock device and the second clock device is disconnected, the first clock device converts the first primary BFD session state from the first state UP to the second state DOWN, and switches the session of the first clock device and the second clock device to the first backup BFD session.

Bidirectional forwarding detection (Bidirectional Forwarding Detection, BFD) is a network protocol that detects the availability of network paths and quickly discovers faults. BFD may be applied in a variety of network environments including ethernet, IP, and multiprotocol label switching networks, among others. In BFD, bidirectional forwarding detection establishes a BFD session between two network devices. The BFD session includes a sender and a receiver. The sending end sends BFD messages at a certain time interval, and the receiving end is responsible for monitoring the receiving condition of the messages. If the receiving end does not receive the BFD message within a prescribed time, the path is considered to be faulty, and relevant network equipment is notified.

A bidirectional forwarding detection session is a session for detecting bidirectional forwarding problems in a network. I.e. the process of data in the network from a source address to a destination address and then back from the destination address to the source address. The bidirectional forwarding detection session verifies whether the network has bidirectional forwarding problems by sending specific test packets. These test packets typically contain an identifier to enable identification upon return. The sender sends the test packet to the destination address and waits to receive the returned packet. If a returned data packet is received and contains the same identifier as the transmitted test data packet, it indicates that there is no bidirectional forwarding problem in the network. If no returned data packet is received or the identifier in the returned data packet does not match the transmitted test data packet, a bidirectional forwarding problem exists in the network.

In step S204, the first clock device switches the primary clock frequency state of the first clock device according to the primary BFD session state, increases the packet sending frequency level of the first clock device from the first level to the second level, and sends the first target packet carrying the packet sending frequency level to the second clock device, where the packet sending frequency corresponding to the second level is greater than the packet sending frequency corresponding to the first level, and the second frequency synchronization module corresponding to the second clock device is configured to switch the primary clock frequency state of the second clock device according to the primary BFD session state, and switch the standby clock frequency state of the second clock device according to the received first target packet.

According to some alternative embodiments of the present application, the first frequency synchronization module switches the primary clock frequency status of the first clock device from the third status INIT to the fourth status LOSS according to the received first primary BFD session status, and the ESMC protocol perceives that the primary clock frequency status of the first clock device is switched from INIT to LOSS, thereby increasing the packet sending frequency of the first clock device from the first level to the second level, and sending the first target message carrying the packet sending frequency level (the second level) to the second clock device.

The frequency synchronization module of a clock device is a module for synchronizing clock frequencies of different devices. In data transmission or collaboration between multiple devices, it is important to ensure that the clock frequencies of the devices are consistent to avoid data transmission errors or dyssynchrony. It should be noted that, in this embodiment, the frequency synchronization module uses the ESMC protocol to perform frequency synchronization, and the ESMC protocol broadcasts or multicasts time synchronization information in the network, so that devices in the network can perform clock frequency synchronization according to the received time information. The frequency synchronization module receives the time information in the device and then adjusts the clock frequency of the device based on the received time information to keep it synchronized with other devices. The frequency synchronization module typically includes an implementation of a clock synchronization protocol and hardware coupled to the device master clock. Which may receive time information over a network and then pass the adjusted clock frequency to the master clock of the device to achieve frequency synchronization.

In this embodiment, the packet sending of the clock device is based on the ESMC protocol, and the three levels of ESMC packet sending frequency are respectively: MID (first level), HIGH (second level), and LOW (third level), wherein LOW corresponds to ESMC protocol standard rate: 1PPS; the standard rate of ESMC protocol corresponding to MID is: 16PPS, wherein the grade holding time is 3min; the standard rate of ESMC protocol corresponding to HIGH is: 32PPS, class hold time 5min.

The ESMC protocol is a multiplexing protocol for ethernet that can transmit different ethernet services (e.g., data, voice, video, etc.) over the same ethernet link, thereby improving bandwidth utilization and network efficiency. The ESMC protocol implements multiplexing by adding ESMC headers in Ethernet frames that contain source and destination service identifiers for distinguishing between different Ethernet services.

The second frequency synchronization module corresponding to the second clock device switches the main clock frequency state of the second clock device from the fifth state PASSIVE to the third state INIT according to the received first main BFD session state, and switches the standby clock frequency state of the second clock device from the third state INIT to the sixth state LOCK according to the packet sending frequency level (second level) in the received first target packet.

Step S206, if the duration of the second level of the packet sending frequency level of the first clock device reaches the first preset duration, the packet sending frequency of the first clock device is reduced if the current clock frequency state is the initial state of the primary clock frequency of the first clock device.

In some optional embodiments of the present application, when the duration that the packet sending frequency of the first clock device continues to last the second level HIGH reaches 5min, if the current clock frequency state is the initial state of the main clock frequency state of the first clock device, that is, the INIT state, the packet sending frequency of the first clock device is reduced, that is, the packet sending frequency level of the first clock device is reduced from the second level HIGH to the first level MID.

Further, in the case that the packet sending frequency level of the first clock device continues for the duration of the first level HIGH for 3min, if the current clock frequency state is INIT, the packet sending frequency of the first clock device is kept at the first level MID.

According to the steps, the purpose of quickly sensing the abnormal link is achieved by adjusting the packet sending frequency of the clock equipment corresponding to the frequency synchronization module according to the state of the BFD session, so that the technical effect of timely synchronizing the clock equipment is achieved.

According to some alternative embodiments of the present application, the first clock device switches the active clock frequency state of the first clock device according to the first active BFD session state, by: and switching the main clock frequency state of the first clock device from a third state to a fourth state, wherein the third state is used for representing that the main clock frequency is an initial state, and the fourth state is used for representing that the main clock signal corresponding to the main clock frequency is a lost state.

And the first frequency synchronization module corresponding to the first clock equipment switches the main clock frequency state of the first clock equipment from the third state INIT to the fourth state LOSS according to the first main BFD session state.

In some alternative embodiments of the present application, when the first primary BFD session and the first standby BFD session of the first clock device and the second clock device are both disconnected, the primary clock frequency state and the standby clock frequency state of the first clock device are switched, and the packet sending frequency level of the first clock device to the third clock device is promoted, where the first clock device is communicatively connected to the second clock device and the third clock device, respectively, the second clock device is communicatively connected to the fourth clock device, and the second clock device is configured to switch the primary clock frequency state and the standby clock frequency state of the second clock device according to the primary BFD session state, respectively, and promote the packet sending frequency level of the second clock device to the fourth clock device, and the fourth clock device is configured to switch the clock frequency state of the fourth clock device according to the received second target packet sent by the second clock device, where the second target packet includes: the second clock device sends the packet frequency level to the fourth clock device, and the fourth clock device is further used for communicating with the third clock device according to the received third target message sent by the third clock device, and switching the clock frequency state of the fourth clock device.

Under the condition that the first main BFD session and the first standby BFD session of the first clock device and the second clock device are disconnected, the main clock frequency state and the standby clock frequency state of the first clock device are switched, and the packet sending frequency level of the first clock device to the third clock device is improved, specifically: and under the condition that the first main BFD session and the first standby BFD session of the first clock device and the second clock device are disconnected, switching the main clock frequency state of the first clock device from the third state to the fourth state, and increasing the packet sending frequency of the first clock device to the third clock device from the first level to the second level.

In this embodiment, the first clock device is connected to the second clock device and the third clock device, the second clock device is connected to the fourth clock device, and the third clock device is connected to the fourth clock device.

In the case that the first primary BFD session and the first standby BFD session of the first clock device and the second clock device are both disconnected, the first frequency synchronization module switches the primary clock frequency state of the first clock device from the third state INIT to the fourth state LOSS, and increases the packet sending frequency of the first clock device from the first level MID to the second level HIGH.

The second frequency synchronization module switches the main clock frequency state of the second clock device from a sixth state LOCK to a fourth state LOSS according to the received first main BFD session state, switches the standby clock frequency state of the second clock device from a fifth state PASSIVE to the fourth state LOSS, and improves the packet sending frequency of the second clock device to the fourth clock device from the first level MID to the second level HIGH.

Further, the fourth clock device switches the clock frequency state of the fourth clock device from the sixth state LOCK to the third state INIT according to the received second target message carrying the frequency level sent by the second clock device; and the fourth clock device communicates with the third clock device according to the received third target message sent by the third clock device, and switches the clock frequency states of the fourth clock device and the third clock device from the fifth state PASSIVE to the sixth state LOCK.

The second clock device is in a LOSS state due to the double-link fault, and the packet sending frequency is kept at a HIGH level all the time, and waits for the processing of an administrator.

Fig. 3 is a flowchart of another method of synchronizing clock devices according to an embodiment of the present application, as shown in fig. 3, the method comprising the steps of:

In step S302, when the second clock device is disconnected from the first active bidirectional forwarding detection BFD session of the first clock device, the first active BFD session state is switched from the first state to the second state, and the session of the second clock device with the first clock device is switched to the first standby BFD session.

Step S304, the second clock device switches the primary clock frequency state of the second clock device according to the first primary BFD session state, and switches the standby clock frequency state of the second clock device according to the received first target message, wherein the first frequency synchronization module corresponding to the first clock device is used for switching the primary clock frequency state of the first clock device according to the first primary BFD session state, increasing the packet sending frequency of the first clock device from the first level to the second level, and sending the first target message carrying the packet sending frequency level to the second clock device.

According to some optional embodiments of the present application, the second clock device switches the primary clock frequency state of the second clock device according to the first primary BFD session state, and switches the standby clock frequency state of the second clock device according to the received first target packet, which may be implemented by: switching the master clock frequency state of the second clock device from the fifth state to the third state; the standby clock frequency state of the second clock device is switched from the third state to the sixth state.

According to other alternative embodiments of the present application, in a case where the second clock device is disconnected from both the first active BFD session and the first standby BFD session of the first clock device, the second clock device switches the active clock frequency state and the standby clock frequency state of the second clock device according to the first active BFD session state, and promotes a packet sending frequency level of the second clock device to the fourth clock device, where the second clock device is communicatively connected to the first clock device and the fourth clock device, and the fourth clock device is configured to switch the clock frequency state of the fourth clock device according to a received second target packet sent by the second clock device, where the second target packet includes: the second clock device sends a packet to the fourth clock device, and the fourth clock device is further configured to communicate with the third clock device according to the received third target packet sent by the third clock device, and switch the clock frequency state of the fourth clock device.

In some optional embodiments of the present application, the second clock device switches the active clock frequency state and the standby clock frequency state of the second clock device according to the first active BFD session state, and promotes the packet sending frequency level of the second clock device to the fourth clock device, specifically: switching the master clock frequency state of the second clock device from the sixth state to the fourth state; switching the standby clock frequency state of the second clock device from the fifth state to the fourth state; the frequency of the packet sent from the second clock device to the fourth clock device is increased from the first level to the second level.

Fig. 4 is a schematic diagram of a synchronization method of a clock device according to an embodiment of the present application, as shown in fig. 4:

in the event that the first primary BFD session of the first clock device and the second clock device is disconnected, the first clock device converts the first primary BFD session state from the first state UP to the second state DOWN, and switches the session of the first clock device and the second clock device to the first backup BFD session.

The first frequency synchronization module switches the main clock frequency state of the first clock device from the third state INIT to the fourth state LOSS according to the received first main BFD session state, and promotes the packet sending frequency of the first clock device from the first level MID to the second level HIGH, and sends a first target message carrying the packet sending frequency level (the second level) to the second clock device.

The second frequency synchronization module corresponding to the second clock device switches the main clock frequency state of the second clock device from the fifth state PASSIVE to the third state INIT according to the received first main BFD session state, and switches the standby clock frequency state of the second clock device from the third state INIT to the sixth state LOCK according to the packet sending frequency level (second level) in the received first target packet.

Furthermore, in case the first primary BFD session and the first standby BFD session of the first clock device and the second clock device are both disconnected, the first frequency synchronization module switches the primary clock frequency state of the first clock device from the third state INIT to the fourth state LOSS, and increases the packet sending frequency of the first clock device from the first level MID to the second level HIGH.

The second frequency synchronization module switches the main clock frequency state of the second clock device from a sixth state LOCK to a fourth state LOSS according to the received first main BFD session state, switches the standby clock frequency state of the second clock device from a fifth state PASSIVE to the fourth state LOSS, and improves the packet sending frequency of the second clock device to the fourth clock device from the first level MID to the second level HIGH.

The fourth clock device switches the clock frequency state of the fourth clock device from a sixth state LOCK to a third state INIT according to the received second target message carrying the frequency level sent by the second clock device; and the fourth clock device communicates with the third clock device according to the received third target message sent by the third clock device, and switches the clock frequency states of the fourth clock device and the third clock device from the fifth state PASSIVE to the sixth state LOCK. The second clock device is in a LOSS state due to the double-link fault, and the packet sending frequency is kept at a HIGH level all the time, and waits for the processing of an administrator.

Through the steps, the change of the network topology can be perceived quickly, and the stability of the networking clock synchronization function is improved. And dynamically adjusting the packet sending frequency to reduce the load of the central processing unit.

Fig. 5 shows a block diagram of a hardware structure of a computer terminal (or mobile device) for implementing a synchronization method of a clock device. As shown in fig. 5, the computer terminal 50 (or mobile device) may include one or more processors 502 (shown in the figures as 502a, 502b, … …,502 n) (the processor 502 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, etc. processing means), a memory 504 for storing data, and a transmission module 506 for communication functions. In addition, the method may further include: a display, an input/output interface (I/O interface), a Universal Serial BUS (USB) port (which may be included as one of the ports of the BUS), a network interface, a power supply, and/or a camera. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 5 is merely illustrative and is not intended to limit the configuration of the electronic device described above. For example, the computer terminal 50 may also include more or fewer components than shown in FIG. 5, or have a different configuration than shown in FIG. 5.

It should be noted that the one or more processors 502 and/or other data processing circuits described above may be referred to herein generally as "data processing circuits. The data processing circuit may be embodied in whole or in part in software, hardware, firmware, or any other combination. Furthermore, the data processing circuitry may be a single stand-alone processing module, or incorporated, in whole or in part, into any of the other elements in the computer terminal 50 (or mobile device). As referred to in embodiments of the application, the data processing circuit acts as a processor control (e.g., selection of the path of the variable resistor termination connected to the interface).

The memory 504 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the synchronization method of the clock device in the embodiment of the present application, and the processor 502 executes the software programs and modules stored in the memory 504, thereby performing various functional applications and data processing, that is, implementing the synchronization method of the clock device described above. Memory 504 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 504 may further comprise memory located remotely from the processor 502, which may be connected to the computer terminal 50 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission module 506 is used to receive or transmit data via a network. The specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 50. In one example, the transmission module 506 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission module 506 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.

The display may be, for example, a touch screen type Liquid Crystal Display (LCD) that may enable a user to interact with a user interface of the computer terminal 50 (or mobile device).

It should be noted here that, in some alternative embodiments, the computer device (or the electronic device) shown in fig. 5 may include hardware elements (including circuits), software elements (including computer code stored on a computer readable medium), or a combination of both hardware elements and software elements. It should be noted that fig. 5 is only one example of a specific example, and is intended to illustrate the types of components that may be present in the computer device (or electronic device) described above.

It should be noted that, the electronic device shown in fig. 5 is used for executing the synchronization method of the clock device shown in fig. 2, so the explanation of the execution method of the command is also applicable to the electronic device, and will not be repeated here.

The embodiment of the application also provides a nonvolatile storage medium, which comprises a stored program, wherein the program controls the equipment where the storage medium is located to execute the above clock equipment synchronization method when running.

The nonvolatile storage medium executes a program of the following functions: under the condition that a first main Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches the state of the first main BFD session from a first state to a second state, and switches the session of the first clock device and the second clock device to a first standby BFD session; the method comprises the steps that a first clock device switches a main clock frequency state of the first clock device according to a first main BFD session state, the packet sending frequency level of the first clock device is improved to a second level from the first level, a first target message carrying the packet sending frequency level is sent to a second clock device, the packet sending frequency corresponding to the second level is larger than the packet sending frequency corresponding to the first level, a second frequency synchronization module corresponding to the second clock device is used for switching the main clock frequency state of the second clock device according to the first main BFD session state, and switching a standby clock frequency state of the second clock device according to the received first target message; and under the condition that the duration that the packet sending frequency grade of the first clock equipment continues to the second grade reaches the first preset duration, if the current clock frequency state is the initial state of the main clock frequency of the first clock equipment, reducing the packet sending frequency of the first clock equipment.

The embodiment of the application also provides electronic equipment, which comprises: the device comprises a memory and a processor, wherein the processor is used for running a program stored in the memory, and the program runs to execute the synchronization method of the clock device.

The processor is configured to execute a program that performs the following functions: under the condition that a first main Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches the state of the first main BFD session from a first state to a second state, and switches the session of the first clock device and the second clock device to a first standby BFD session; the method comprises the steps that a first clock device switches a main clock frequency state of the first clock device according to a first main BFD session state, the packet sending frequency level of the first clock device is improved to a second level from the first level, a first target message carrying the packet sending frequency level is sent to a second clock device, the packet sending frequency corresponding to the second level is larger than the packet sending frequency corresponding to the first level, a second frequency synchronization module corresponding to the second clock device is used for switching the main clock frequency state of the second clock device according to the first main BFD session state, and switching a standby clock frequency state of the second clock device according to the received first target message; and under the condition that the duration that the packet sending frequency grade of the first clock equipment continues to the second grade reaches the first preset duration, if the current clock frequency state is the initial state of the main clock frequency of the first clock equipment, reducing the packet sending frequency of the first clock equipment.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed technology may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the related art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (11)

1. A method of synchronizing clock devices, comprising:

under the condition that a first main Bidirectional Forwarding Detection (BFD) session of a first clock device and a second clock device is disconnected, the first clock device switches a first main BFD session state from a first state to a second state and switches a session of the first clock device and the second clock device to a first standby BFD session;

the first clock device switches the master clock frequency state of the first clock device according to the first master BFD session state, the packet sending frequency level of the first clock device is increased from a first level to a second level, and a first target message carrying the packet sending frequency level is sent to a second clock device, wherein the packet sending frequency corresponding to the second level is greater than the packet sending frequency corresponding to the first level, and a second frequency synchronization module corresponding to the second clock device is used for switching the master clock frequency state of the second clock device according to the first master BFD session state and switching the standby clock frequency state of the second clock device according to the received first target message;

And if the current clock frequency state is the initial state of the primary clock frequency of the first clock device, reducing the packet sending frequency of the first clock device under the condition that the duration of the packet sending frequency level of the first clock device, which is continuous with the second level, reaches the first preset duration.

2. The method of claim 1, wherein the first clock device switching the master clock frequency state of the first clock device according to the first master BFD session state, comprising:

and switching the state of the main clock frequency of the first clock device from a third state to a fourth state, wherein the third state is used for representing that the main clock frequency is an initial state, and the fourth state is used for representing that the main clock signal corresponding to the main clock frequency is a lost state.

3. The method according to claim 2, wherein the method further comprises:

and if the current clock frequency state is the third state under the condition that the duration of the first clock equipment package frequency grade lasting the first grade reaches the second preset duration, the package frequency of the first clock equipment is kept at the first grade.

4. The method according to claim 1, wherein the method further comprises:

when the first clock device is disconnected from the first active BFD session and the first standby BFD session of the second clock device, the active clock frequency state and the standby clock frequency state of the first clock device are switched, and the packet sending frequency level of the first clock device to the third clock device is promoted, where the first clock device is communicatively connected with the second clock device and the third clock device, the second clock device is communicatively connected with the fourth clock device, and the second clock device is configured to switch the active clock frequency state and the standby clock frequency state of the second clock device according to the first active BFD session state, and promote the packet sending frequency level of the second clock device to the fourth clock device, and the fourth clock device is configured to switch the clock frequency state of the fourth clock device according to the received second target packet sent by the second clock device, where the second target packet includes: the second clock device is used for transmitting a packet frequency grade to the fourth clock device, and the fourth clock device is also used for communicating with the third clock device according to the received third target message sent by the third clock device and switching the clock frequency state of the fourth clock device.

5. The method of claim 4, wherein switching the primary and backup clock frequency states of the first clock device and increasing the level of packet sending frequency of the first clock device to a third clock device if the first primary BFD session and the first backup BFD session of the first clock device are both disconnected from the second clock device, comprises:

and under the condition that the first clock device is disconnected from the first main BFD session and the first standby BFD session of the second clock device, switching the main clock frequency state of the first clock device from a third state to a fourth state, and increasing the packet sending frequency of the first clock device to the third clock device from the first level to the second level.

6. A method of synchronizing clock devices, comprising:

under the condition that a second clock device is disconnected from a first main Bidirectional Forwarding Detection (BFD) session of a first clock device, the state of the first main BFD session is switched from a first state to a second state, and the session of the second clock device and the first clock device is switched to a first standby BFD session;

The second clock device switches the primary clock frequency state of the second clock device according to the first primary BFD session state, and switches the standby clock frequency state of the second clock device according to the received first target message, wherein the first frequency synchronization module corresponding to the first clock device is configured to switch the primary clock frequency state of the first clock device according to the first primary BFD session state, raise the packet sending frequency of the first clock device from a first level to a second level, and send the first target message carrying the packet sending frequency level to the second clock device.

7. The method of claim 6, wherein the second clock device switching the active clock frequency state of the second clock device according to the first active BFD session state and switching the standby clock frequency state of the second clock device according to the received first target message, comprising:

switching a master clock frequency state of the second clock device from a fifth state to a third state;

and switching the standby clock frequency state of the second clock device from the third state to a sixth state.

8. The method of claim 6, wherein the method further comprises:

under the condition that the second clock device is disconnected from both the first main BFD session and the first standby BFD session of the first clock device, the second clock device switches the main clock frequency state and the standby clock frequency state of the second clock device according to the first main BFD session state, and promotes the packet sending frequency level of the second clock device to the fourth clock device, wherein the second clock device is in communication connection with the first clock device and the fourth clock device, the fourth clock device is used for switching the clock frequency state of the fourth clock device according to the received second target message sent by the second clock device, and the second target message comprises: the second clock device is further configured to communicate with the third clock device according to the received third target packet sent by the third clock device, and switch the clock frequency state of the fourth clock device.

9. The method of claim 6, wherein the second clock device switches the active clock frequency state and the standby clock frequency state of the second clock device according to the first active BFD session state, respectively, and promotes a packet sending frequency level of the second clock device to a fourth clock device, comprising:

Switching a master clock frequency state of the second clock device from a sixth state to a fourth state;

switching the standby clock frequency state of the second clock device from a fifth state to the fourth state;

and increasing the frequency of the packets sent by the second clock device to the fourth clock device from the first level to the second level.

10. A non-volatile storage medium, characterized in that the non-volatile storage medium comprises a stored program, wherein the device in which the non-volatile storage medium is controlled to perform the synchronization method of the clock device according to any one of claims 1 to 9 when the program is run.

11. An electronic device, comprising: a memory and a processor for running a program stored in the memory, wherein the program runs to perform the method of synchronizing clock devices according to any of claims 1 to 9.