CN117220650A - Pre-punching processing circuit with de-emphasis function - Google Patents
Pre-punching processing circuit with de-emphasis function Download PDFInfo
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- 238000004080 punching Methods 0.000 title claims abstract description 67
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 35
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Abstract
The application provides a pre-punching processing circuit with a de-emphasis function, which belongs to the technical field of high-speed interconnection, and comprises: a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit; the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal; the combined processing sub-circuit is used for generating a target signal subjected to pre-punching and de-emphasis processing based on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal, can simultaneously perform pre-punching processing and de-emphasis processing on the data signal, can simultaneously adjust the amplitude difference between the high frequency component and other low frequency components contained in the first bit and the last bit of repeated data in the data signal, and further effectively compensates the high frequency loss caused by a channel on the basis of reducing the complexity of the circuit.
Description
Technical Field
The application relates to the technical field of high-speed interconnection, in particular to a pre-punching processing circuit with a de-emphasis function.
Background
The continuous development of electronic technology drives the data transmission speed to be gradually increased, for example, the transmission speed of PCIE has been developed from 2.5GT/s of the first generation to 64GT/s of the sixth generation, but the continuous development of electronic technology also brings challenges: the signal needs to be transmitted in a channel, and the channel has a low-pass frequency domain characteristic, so that the loss of the low-frequency component of the signal is small, and the loss of the high-frequency component is large. Thus, the normal signal, when transmitted through the channel, results in a signal having a higher amplitude for the low frequency component than the high frequency component. For the receiver, the large difference between the amplitudes of the high-frequency component and the low-frequency component of the signal can cause difficulty in correctly receiving the data signal by the receiving end.
In order to solve the problem of attenuation of the high frequency components of the transmitted signal by the channel, the prior art generally employs pre-emphasis or de-emphasis techniques to perform channel compensation on the signal.
For the voltage signals for transmitting binary data of 0 and 1, the high-frequency components of the signals are more before and after the data are overturned; the rest is more signal low frequency components. The preshot (presboost) technique increases the amplitude of the high frequency component of the signal portion by increasing the amplitude of the last bit of the repeated data of the signal (i.e., the last bit before the data flip occurs). However, this method has the disadvantage that: under normal conditions, the voltage swing of data is close to the power supply voltage, and the amplitude of the high-frequency component is increased by using pre-flushing on the basis, so that the amplitude exceeds the amplitude of the power supply voltage, and the difficulty is high. And the pre-flushing can only singly compensate the amplitude of the last bit of the repeated data, the compensation effect is limited, and if the compensation effect is improved by combining other technologies, the circuit structure is complicated. For example, CN1081048A discloses a circuit combining pre-flush and overshoot, but the circuit uses modules such as threshold control, jump detection, maximum selector, minimum detector, switch, bias, delay circuit, and the like, and uses devices such as inductors which are inconvenient to integrate, and has a complex structure, and can greatly increase the area and cost for the integrated circuit.
The de-emphasis technique uses the first bit of the repeated data (i.e., the first bit after the data is flipped) as the target bit, and increases the amplitude difference between the high-frequency component and the low-frequency component of the signal portion by reducing the amplitude of the non-target bit in the repeated data, but cannot adjust the amplitude difference between the last bit and the low-frequency bit of the repeated data that also contains the high-frequency component. Therefore, although the method can improve the amplitude difference of the high-frequency and low-frequency components of the signal caused by the channel, the effect is not ideal.
Disclosure of Invention
The application provides a pre-flushing processing circuit with a de-emphasis function, which is used for effectively compensating high-frequency loss of a channel on a data signal on the basis of reducing the complexity of the circuit.
The application provides a pre-punching processing circuit with a de-emphasis function, which comprises:
a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit;
the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal;
the joint processing sub-circuit is used for generating a target signal subjected to pre-punching and de-emphasis processing based on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal.
According to the pre-punching processing circuit with the de-emphasis function, the pre-punching driving signal is obtained by performing first time delay operation on an input original data signal, the main driving signal is obtained by performing first time delay operation and reverse phase operation on the pre-punching driving signal, and the de-emphasis driving signal is obtained by performing second time delay operation on the pre-punching driving signal;
the delay amount corresponding to the first delay operation is one data bit, and the delay amount corresponding to the second delay operation is two data bits.
According to the pre-punching processing circuit with the de-emphasis function provided by the application, the target signal subjected to pre-punching and de-emphasis processing is generated based on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal, and the pre-punching processing circuit specifically comprises:
respectively carrying out opposite-phase operation on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal to obtain a corresponding pre-punching output signal, a main output signal and a de-emphasis output signal;
and inputting the pre-punching output signal, the main output signal and the de-emphasis output signal into a preset resistor network to obtain a target signal subjected to pre-punching and de-emphasis processing.
According to the pre-punching processing circuit with the de-emphasis function, the driving signal generation sub-circuit comprises a pre-punching driving signal generation unit, a main driving signal generation unit and a de-emphasis driving signal generation unit, wherein the main driving signal generation unit and the de-emphasis driving signal generation unit are respectively connected with the pre-punching driving signal generation unit;
the pre-punching driving signal generation unit is used for performing first time delay operation on an input original data signal to generate a pre-punching driving signal;
the main driving signal generating unit is used for performing first delay operation and inversion operation on an input pre-flushing driving signal to generate a main driving signal;
the de-emphasis driving signal generating unit is used for performing a second time delay operation on the input pre-punching driving signal to generate a de-emphasis driving signal.
According to the pre-punching processing circuit with the de-emphasis function, the pre-punching driving signal generating unit comprises a first D trigger, the main driving signal generating unit comprises a second D trigger and an inverter which are connected in series, and the de-emphasis driving signal generating unit comprises a third D trigger and a fourth D trigger which are connected in series;
the data output end of the first D trigger is connected with the data input ends of the second D trigger and the third D trigger respectively, the data output end of the second D trigger is connected with the input end of the inverter, and the data output end of the third D trigger is connected with the data input end of the fourth D trigger.
According to the pre-punching processing circuit with the de-emphasis function, the data input end of the first D trigger is used for inputting an original data signal, and the data output end of the first D trigger is used for outputting a pre-punching driving signal; the data input end of the second D trigger is used for inputting a pre-flushing driving signal, and the output end of the phase inverter is used for outputting a main driving signal; the data input end of the third D trigger is used for inputting a pre-flushing driving signal, and the data output end of the fourth D trigger is used for outputting a emphasis driving signal.
According to the pre-flushing processing circuit with the de-emphasis function, the triggering modes of the first D trigger to the fourth D trigger are all rising edge triggering, the clock input ends of the first D trigger to the fourth D trigger are all input with target clock signals, and the period of the target clock signals is the time of one data bit.
According to the pre-flushing processing circuit with the de-emphasis function, the combined processing sub-circuit comprises a driving unit and a resistor network connected with the driving unit;
the driving unit comprises a first driving subunit, a second driving subunit and a third driving subunit;
the first driving subunit is used for carrying out reverse phase operation on the pre-punching driving signal to obtain a corresponding pre-punching output signal;
the second driving subunit is used for performing reverse phase operation on the main driving signal to obtain a corresponding main output signal;
and the third driving subunit is used for carrying out inverting operation on the de-emphasis driving signal to obtain a corresponding de-emphasis output signal.
According to the pre-punching processing circuit with the de-emphasis function, the resistor network comprises a first resistor, a second resistor and a third resistor;
the first end of the first resistor is connected with the output end of the first driving subunit, the first end of the second resistor is connected with the output end of the second driving subunit, and the first end of the third resistor is connected with the output end of the third driving subunit; the second ends of the first to third resistors are connected to each other to form a target signal output end.
According to the pre-flushing processing circuit with the de-emphasis function, the first driving subunit, the second driving subunit and the third driving subunit respectively comprise a P-type MOS tube unit and an N-type MOS tube unit;
the drain electrode of the P-type MOS tube unit is connected with a power supply, the source electrode of the P-type MOS tube unit is connected with the drain electrode of the N-type MOS tube unit to serve as an output end, the grid electrode of the P-type MOS tube unit is connected with the grid electrode of the N-type MOS tube unit to serve as an input end, and the source electrode of the N-type MOS tube unit is grounded.
The application provides a pre-punching processing circuit with a de-emphasis function, which comprises: a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit; the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal; the combined processing sub-circuit is used for generating a target signal subjected to pre-flushing and de-emphasis processing based on the pre-flushing driving signal, the main driving signal and the de-emphasis driving signal, can perform pre-flushing processing on the data signal, provides an amplification space for the last bit of the repeated data to be adjusted in the pre-flushing process by reducing the amplitude of the repeated data, simultaneously combines the de-emphasis processing, reduces the amplitude of other bits after the first bit in the repeated data, can simultaneously adjust the amplitude difference between the high-frequency component and other low-frequency components contained in the first and last bits of the repeated data in the data signal, and further effectively compensates the high-frequency loss caused by a channel on the data signal on the basis of reducing the circuit complexity.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a pre-flush processing circuit with de-emphasis function according to the present application;
FIG. 2 is a schematic diagram of the connection of the components of the driving signal generating sub-circuit provided by the present application;
FIG. 3 is a schematic diagram of signal timing corresponding to the driving signal generating sub-circuit according to the present application;
FIG. 4 is a schematic diagram of the connection of the components of the joint processing sub-circuit provided by the present application;
FIG. 5 is a schematic diagram of signal timing corresponding to the joint processing sub-circuit according to the present application;
FIG. 6 is an exploded view of the generation of a target signal provided by the present application;
FIG. 7 is a second schematic diagram of signal timing corresponding to the joint processing sub-circuit according to the present application;
FIG. 8 is a timing diagram of the target signal before and after improvement according to the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 is a schematic structural diagram of a pre-punching processing circuit with a de-emphasis function according to the present application, as shown in fig. 1, the circuit includes:
a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit;
the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal;
the joint processing sub-circuit is used for generating a target signal subjected to pre-punching and de-emphasis processing based on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal.
Specifically, for a driving signal generating sub-circuit, the pre-punching driving signal is obtained by performing a first time delay operation on an input original data signal, the main driving signal is obtained by performing a first time delay operation and an inversion operation on the pre-punching driving signal, and the de-emphasis driving signal is obtained by performing a second time delay operation on the pre-punching driving signal;
the delay amount corresponding to the first delay operation is one data bit, and the delay amount corresponding to the second delay operation is two data bits.
More specifically, the driving signal generating sub-circuit comprises a pre-flushing driving signal generating unit, a main driving signal generating unit and a de-emphasis driving signal generating unit, wherein the main driving signal generating unit and the de-emphasis driving signal generating unit are respectively connected with the pre-flushing driving signal generating unit;
the pre-punching driving signal generation unit is used for performing first time delay operation on an input original data signal to generate a pre-punching driving signal;
the main driving signal generating unit is used for performing first delay operation and inversion operation on an input pre-flushing driving signal to generate a main driving signal;
the de-emphasis driving signal generating unit is used for performing a second time delay operation on the input pre-punching driving signal to generate a de-emphasis driving signal.
Fig. 2 is a schematic diagram of connection relation between components of a driving signal generating sub-circuit provided by the present application, as shown in fig. 2, the pre-punching driving signal generating unit includes a first D flip-flop (i.e., D1 in fig. 2), the main driving signal generating unit includes a second D flip-flop (i.e., D2 in fig. 2) and an inverter (i.e., INV in fig. 2) connected in series, and the de-emphasis driving signal generating unit includes a third D flip-flop (i.e., D3 in fig. 2) and a fourth D flip-flop (i.e., D4 in fig. 2) connected in series;
the data output end (i.e., Q pin in fig. 2, the latter and the like) of the first D flip-flop is connected with the data input ends (i.e., D pin in fig. 2, the latter and the like) of the second D flip-flop and the third D flip-flop respectively, the data output end of the second D flip-flop is connected with the input end of the inverter, and the data output end of the third D flip-flop is connected with the data input end of the fourth D flip-flop.
As will be appreciated based thereon, the data input of the first D flip-flop is used for inputting the original data signal (i.e., S in fig. 2), and the data output of the first D flip-flop is used for outputting the pre-flush driving signal (i.e., s_a in fig. 2); the data input end of the second D trigger is used for inputting a pre-flushing driving signal, and the output end of the inverter is used for outputting a main driving signal (namely S_B in FIG. 2); the data input end of the third D flip-flop is used for inputting the pre-flush driving signal, and the data output end of the fourth D flip-flop is used for outputting the emphasis driving signal (i.e. s_c in fig. 2). The signal output by the delay operation of the second D flip-flop is denoted as s_bb.
It should be noted that the triggering manners of the first to fourth D flip-flops are rising edge triggering, and the clock input terminals (i.e., the CK pin in fig. 2) of the first to fourth D flip-flops each input a target clock signal (i.e., the CLK in fig. 2), and the period of the target clock signal is one data bit time. It can be understood that the internal structures of the first to fourth D flip-flops may be the same or different, and only the delay operation needs to be implemented, which is not particularly limited in the embodiment of the present application.
It is further understood that the main driving signal generating unit may also directly use the second D flip-flop output s_b having the inverse output function, which is not particularly limited in the embodiment of the present application. In the case where the main driving signal generating unit directly uses the second D flip-flop having the inverted output function, the principle and effect thereof are the same as those in the case where the aforementioned main driving signal generating unit includes the second D flip-flop and the inverter, and therefore the principle and effect will be described later with emphasis on the case where the main driving signal generating unit includes the second D flip-flop and the inverter.
By combining the working principles of the D trigger and the inverter, the following phase relationship can be ensured by the pre-flushing driving signal, the main driving signal and the de-emphasis driving signal obtained by the driving signal generating sub-circuit: the pre-flush drive signal lags the original data signal by one data bit, the main drive signal is an inverted signal of s_bb, and s_bb lags the pre-flush drive signal by one data bit, and the de-emphasis drive signal lags the s_bb by one data bit. Fig. 3 is a schematic diagram of signal timing corresponding to the driving signal generating sub-circuit according to the present application, wherein the abscissa represents time and the ordinate represents voltage value (the same is true for the following fig. 5, 7-8). The phase relation of the signals corresponding to the driving signal generating sub-circuit is shown in fig. 3, and the pre-punching driving signal, the main driving signal and the de-emphasis driving signal obtained based on the driving signal generating sub-circuit can be input into the combined processing sub-circuit to realize pre-punching and de-emphasis processing of the signals to obtain the target signal.
Specifically, the generating, based on the pre-flush driving signal, the main driving signal and the de-emphasis driving signal, a target signal subjected to pre-flush and de-emphasis processing specifically includes:
respectively carrying out opposite-phase operation on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal to obtain a corresponding pre-punching output signal, a main output signal and a de-emphasis output signal;
and inputting the pre-punching output signal, the main output signal and the de-emphasis output signal into a preset resistor network to obtain a target signal subjected to pre-punching and de-emphasis processing.
Based on this, the joint processing sub-circuit comprises a driving unit and a resistor network connected with the driving unit;
the driving unit comprises a first driving subunit, a second driving subunit and a third driving subunit;
the first driving subunit is used for carrying out reverse phase operation on the pre-punching driving signal to obtain a corresponding pre-punching output signal;
the second driving subunit is used for performing reverse phase operation on the main driving signal to obtain a corresponding main output signal;
and the third driving subunit is used for carrying out inverting operation on the de-emphasis driving signal to obtain a corresponding de-emphasis output signal.
FIG. 4 is a schematic diagram of the connection relationship between the components of the combined processing sub-circuit provided by the application, as shown in FIG. 4, the first to third driving sub-units each include a P-type MOS tube unit and an N-type MOS tube unit;
the drain electrode of the P-type MOS tube unit is connected with a power supply, the source electrode of the P-type MOS tube unit is connected with the drain electrode of the N-type MOS tube unit to serve as an output end, the grid electrode of the P-type MOS tube unit is connected with the grid electrode of the N-type MOS tube unit to serve as an input end, and the source electrode of the N-type MOS tube unit is grounded.
As will be appreciated from this, the input of the first drive subunit is used for inputting the pre-flush drive signal, the output is used for outputting the pre-flush output signal (i.e. out_a in fig. 4), the input of the second drive subunit is used for inputting the main drive signal, the output is used for outputting the main output signal (i.e. out_b in fig. 4), and the input of the third drive subunit is used for inputting the de-emphasis drive signal, and the output is used for outputting the de-emphasis output signal (i.e. out_c in fig. 4). It should be noted that the P-type MOS transistor unit may include only one P-type MOS transistor (in the case illustrated in fig. 4), or may be combined by a plurality of P-type MOS transistors, where the drain, the source, and the gate of the P-type MOS transistor unit respectively correspond to the drain, the source, and the gate of each P-type MOS transistor when the P-type MOS transistor unit is combined by a plurality of P-type MOS transistors; the N-type MOS transistor units are similar to the P-type MOS transistor units in composition, and are not described herein. It will be appreciated that other functional units, such as an enabling unit, may be included in the first to third driving sub-units, and embodiments of the present application are not limited in this regard.
Fig. 5 is a schematic diagram of signal timing corresponding to the joint processing sub-circuit according to the present application, which corresponds to waveforms of the pre-flush output signal, the main output signal and the de-emphasis output signal.
As can be further seen from fig. 4, the resistor network includes a first resistor (i.e., r_a in fig. 4), a second resistor (i.e., r_b in fig. 4), and a third resistor (i.e., r_c in fig. 4);
the first end of the first resistor is connected with the output end of the first driving subunit, the first end of the second resistor is connected with the output end of the second driving subunit, and the first end of the third resistor is connected with the output end of the third driving subunit; the second terminals of the first to third resistors are connected to each other to form a target signal output terminal (i.e., the OUT pin in fig. 4).
As can be seen from fig. 4, when the target signal (denoted as out_all) output from the OUT terminal is out_ A, OUT _ B, OUT _c, the voltage values on the OUT pins are superimposed. Fig. 6 is an exploded view of the generation process of the target signal provided by the present application, as shown in fig. 6, out_all=out1+out2+out3. It will be appreciated that during actual operation, since r_ A, R _ B, R _c is connected via a resistive star, the voltages (i.e., out_ A, OUT _b and out_c) will interact with each other such that there is some error between the theoretical and actual values, but the error is within an acceptable range. FIG. 7 is a second schematic diagram of signal timing corresponding to the joint processing sub-circuit according to the present application, which corresponds to the waveform of the target signal. Based on the foregoing, since s_b is the main driving signal, which is delayed and inverted from the S signal, and the second driving subunit also has an inverting function, out_b is the main output signal driven by s_b, which is in phase with the S signal. Both s_a and s_c are delayed by the S signal, and both the first and third drive subunits have an inverting function, so out_a is used as the pre-flush output signal driven by s_a and out_c is used as the de-emphasis output signal driven by s_c, both being inverted from the S signal.
Based on this, the last bit in the repeated data of out_b is in phase with out_a, and the superposition of the last bit and out_a attenuates the amplitude of the bit in the repeated data of out_b, which is not in phase with out_a, and increases the amplitude of the bit in phase. As shown in fig. 7, A, C, D, F is attenuated and B, E is amplified as the last bit of the repeated data. The first bit in the repeated data of the OUT_B is in phase with the OUT_C, and the first bit and the OUT_C are overlapped, so that the amplitude of the bit which is OUT of phase with the OUT_C in the repeated data of the OUT_B can be attenuated, and the amplitude of the bit which is in phase is increased. As shown in fig. 7, A, B, D, E is attenuated and C, F is amplified as the first bit of the repeated data. In the non-repeated data of OUT_B, OUT_ B, OUT _ A, OUT _C are in phase, and are not attenuated but only amplified. As shown in fig. 7, G, H will be amplified. Therefore, the resistances with proper resistance values are respectively connected in series in the OUT_A, the OUT_B and the OUT_C, and the target signal OUT_all after the pre-punching and de-emphasis processing can be obtained. The voltage value of A, D is mainly controlled by adjusting the resistance value of r_b, the voltage value of B, E is mainly controlled by adjusting the resistance value of r_a, the voltage value of C, F is mainly controlled by adjusting the resistance value of r_c, G, H is not repeated data, and neither pre-punching nor de-emphasis will attenuate the voltage at the point.
In the embodiment of the present application, a capacitor is preferably connected between the OUT terminal and ground, and fig. 8 is a schematic diagram showing the timing comparison of the target signal before and after the improvement (i.e. the capacitance increase) provided in the present application, and as shown in fig. 8, the capacitance increase can make the waveform of the output target signal smoother.
In summary, through the pre-flushing processing circuit with the de-emphasis function in the embodiment of the application, even if the voltage swing of the data is close to the power supply voltage, the purpose of increasing the amplitude difference between the first bit and the last bit of the repeated data and the middle bit can be well realized, so that the amplitude of the low-frequency component of the signal is lower than that of the high-frequency component, and the problem that the channel has larger loss on the high frequency can be effectively solved. Meanwhile, the circuit is simple in structure and easy to integrate, and can effectively compensate high-frequency loss of a channel on a data signal on the basis of reducing circuit complexity. It can be appreciated that the pre-flush processing circuit with the de-emphasis function according to the embodiment of the present application may be applied to a data transmitting end to meet the requirement of equalizing the output signal voltage of the transmitter by different specifications (e.g., PCIE 4.0).
The circuit provided by the embodiment of the application comprises the following components: a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit; the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal; the combined processing sub-circuit is used for generating a target signal subjected to pre-flushing and de-emphasis processing based on the pre-flushing driving signal, the main driving signal and the de-emphasis driving signal, can perform pre-flushing processing on the data signal, provides an amplification space for the last bit of the repeated data to be adjusted in the pre-flushing process by reducing the amplitude of the repeated data, simultaneously combines the de-emphasis processing, reduces the amplitude of other bits after the first bit in the repeated data, can simultaneously adjust the amplitude difference between the high-frequency component and other low-frequency components contained in the first and last bits of the repeated data in the data signal, and further effectively compensates the high-frequency loss caused by a channel on the data signal on the basis of reducing the circuit complexity.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A pre-flush processing circuit with de-emphasis function, the circuit comprising:
a drive signal generation sub-circuit and a joint processing sub-circuit connected to the drive signal generation sub-circuit;
the driving signal generation sub-circuit is used for generating a pre-flushing driving signal, a main driving signal and a de-emphasis driving signal based on an input original data signal;
the joint processing sub-circuit is used for generating a target signal subjected to pre-punching and de-emphasis processing based on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal.
2. The pre-emphasis processing circuit of claim 1, wherein the pre-emphasis driving signal is obtained by performing a first delay operation on an input original data signal, the main driving signal is obtained by performing a first delay operation and an inversion operation on the pre-emphasis driving signal, and the de-emphasis driving signal is obtained by performing a second delay operation on the pre-emphasis driving signal;
the delay amount corresponding to the first delay operation is one data bit, and the delay amount corresponding to the second delay operation is two data bits.
3. The pre-emphasis processing circuit with de-emphasis function of claim 1, wherein the generating the pre-emphasis and de-emphasis processed target signal based on the pre-emphasis driving signal, the main driving signal and the de-emphasis driving signal specifically comprises:
respectively carrying out opposite-phase operation on the pre-punching driving signal, the main driving signal and the de-emphasis driving signal to obtain a corresponding pre-punching output signal, a main output signal and a de-emphasis output signal;
and inputting the pre-punching output signal, the main output signal and the de-emphasis output signal into a preset resistor network to obtain a target signal subjected to pre-punching and de-emphasis processing.
4. The pre-flush processing circuit with a de-emphasis function according to claim 2, wherein the drive signal generation sub-circuit includes a pre-flush drive signal generation unit, a main drive signal generation unit, and a de-emphasis drive signal generation unit, the main drive signal generation unit and the de-emphasis drive signal generation unit being connected to the pre-flush drive signal generation unit, respectively;
the pre-punching driving signal generation unit is used for performing first time delay operation on an input original data signal to generate a pre-punching driving signal;
the main driving signal generating unit is used for performing first delay operation and inversion operation on an input pre-flushing driving signal to generate a main driving signal;
the de-emphasis driving signal generating unit is used for performing a second time delay operation on the input pre-punching driving signal to generate a de-emphasis driving signal.
5. The pre-flush processing circuit with a de-emphasis function according to claim 4, wherein the pre-flush driving signal generating unit includes a first D flip-flop, the main driving signal generating unit includes a second D flip-flop and an inverter connected in series, and the de-emphasis driving signal generating unit includes a third D flip-flop and a fourth D flip-flop connected in series;
the data output end of the first D trigger is connected with the data input ends of the second D trigger and the third D trigger respectively, the data output end of the second D trigger is connected with the input end of the inverter, and the data output end of the third D trigger is connected with the data input end of the fourth D trigger.
6. The pre-flush processing circuit with de-emphasis function according to claim 5, wherein a data input terminal of the first D flip-flop is used for inputting an original data signal, and a data output terminal of the first D flip-flop is used for outputting a pre-flush driving signal; the data input end of the second D trigger is used for inputting a pre-flushing driving signal, and the output end of the phase inverter is used for outputting a main driving signal; the data input end of the third D trigger is used for inputting a pre-flushing driving signal, and the data output end of the fourth D trigger is used for outputting a emphasis driving signal.
7. The pre-flush processing circuit with de-emphasis function as claimed in claim 6, wherein the first to fourth D flip-flops are all triggered by rising edges, and the clock input terminals of the first to fourth D flip-flops are all input with a target clock signal, and the period of the target clock signal is one data bit time.
8. A pre-flush processing circuit with a de-emphasis function according to claim 3, wherein the joint processing sub-circuit comprises a driving unit and a resistor network connected to the driving unit;
the driving unit comprises a first driving subunit, a second driving subunit and a third driving subunit;
the first driving subunit is used for carrying out reverse phase operation on the pre-punching driving signal to obtain a corresponding pre-punching output signal;
the second driving subunit is used for performing reverse phase operation on the main driving signal to obtain a corresponding main output signal;
and the third driving subunit is used for carrying out inverting operation on the de-emphasis driving signal to obtain a corresponding de-emphasis output signal.
9. The pre-flush processing circuit with de-emphasis function of claim 8, wherein said resistor network comprises a first resistor, a second resistor, and a third resistor;
the first end of the first resistor is connected with the output end of the first driving subunit, the first end of the second resistor is connected with the output end of the second driving subunit, and the first end of the third resistor is connected with the output end of the third driving subunit; the second ends of the first to third resistors are connected to each other to form a target signal output end.
10. The pre-flush processing circuit with a de-emphasis function according to claim 8, wherein the first to third driving subunits each comprise a P-type MOS transistor unit and an N-type MOS transistor unit;
the drain electrode of the P-type MOS tube unit is connected with a power supply, the source electrode of the P-type MOS tube unit is connected with the drain electrode of the N-type MOS tube unit to serve as an output end, the grid electrode of the P-type MOS tube unit is connected with the grid electrode of the N-type MOS tube unit to serve as an input end, and the source electrode of the N-type MOS tube unit is grounded.
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| CN202311484438.7A CN117220650A (en) | 2023-11-07 | 2023-11-07 | Pre-punching processing circuit with de-emphasis function |
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| CN202311484438.7A CN117220650A (en) | 2023-11-07 | 2023-11-07 | Pre-punching processing circuit with de-emphasis function |
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