CN117219641A - Image sensor and forming method thereof - Google Patents
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- CN117219641A CN117219641A CN202210620846.XA CN202210620846A CN117219641A CN 117219641 A CN117219641 A CN 117219641A CN 202210620846 A CN202210620846 A CN 202210620846A CN 117219641 A CN117219641 A CN 117219641A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000004408 titanium dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
The application provides a forming method of an image sensor and the image sensor, wherein the image sensor comprises a plurality of pixel units and isolation structures positioned among the pixel units, and the forming method of the isolation structures comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base; forming a plurality of deep trenches, wherein the deep trenches extend from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer; forming a second epitaxial layer on the side wall of the deep trench to reduce the size of an opening of the deep trench; filling a plurality of deep trenches to form a plurality of isolation structures. According to the application, the epitaxial layer is formed on the side wall of the deep trench, so that the size of an opening of the deep trench is reduced, and a narrow trench isolation structure with a high depth-to-width ratio is realized, so that enough space is reserved for the pixel unit, and the full-well capacity of the pixel unit is improved.
Description
Technical Field
The present application relates to the field of image sensors, and in particular, to a method for forming an image sensor and an image sensor.
Background
The CMOS image sensor (CMOS image sensor, CIS) is a photoelectric conversion device widely applied in the field of image acquisition, and has the industrial advantages of high integration level, process compatibility, low manufacturing cost and the like. In the past, CMOS image sensors have been developed toward the continuous miniaturization of pixel cell sizes and the continuous improvement of integration levels.
Photodiodes (PDs) are the most important electrical structures in a pixel cell. In order to develop small-size and high-performance pixel units, various performance problems such as full well capacity, white point, crosstalk, photosensitivity and the like in the PD need to be solved, and therefore the pixel unit size needs to be expanded in the depth direction, and meanwhile, the isolation size needs to be relatively small.
In general, a P-type region is formed around a photodiode by ion implantation to serve as isolation between pixel cells. However, the ion implantation depth is limited, and a required isolation depth between pixel units cannot be satisfied, thereby affecting the image sensor performance.
Disclosure of Invention
The application aims to provide a forming method of an image sensor and the image sensor, which are used for obtaining an isolation structure meeting depth requirements and improving the performance of the image sensor.
In view of the foregoing, the present application provides a method for forming an image sensor, the image sensor including a plurality of pixel units and an isolation structure between the pixel units, wherein the method for forming the isolation structure includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base;
forming a plurality of deep trenches, wherein the deep trenches extend from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer;
forming a second epitaxial layer on the side wall of the deep trench to reduce the size of an opening of the deep trench;
filling a plurality of deep trenches to form a plurality of isolation structures.
Optionally, the method further comprises: before filling the deep trench, forming a first dielectric layer on the side wall and the bottom surface of the deep trench to pin the side wall and the bottom surface of the deep trench.
Optionally, the material of the first dielectric layer is a high-K dielectric material.
Optionally, the thickness of the first dielectric layer is 5-100 a nm a.
Optionally, a second dielectric layer is further provided between the semiconductor substrate and the first epitaxial layer to serve as an etching stop layer when forming the deep trench.
Optionally, the method of forming the plurality of deep trenches comprises:
forming a patterned dielectric layer on the surface of the first epitaxial layer;
etching the first epitaxial layer by adopting an etching process and taking the patterned dielectric layer as a mask;
and forming a plurality of deep trenches in the first epitaxial layer by taking the second dielectric layer as an etching stop layer.
Optionally, the material of the second dielectric layer is one or a combination of more than one of silicon oxide, silicon nitride and silicon oxynitride.
Optionally, a third epitaxial layer is further included between the second dielectric layer and the semiconductor substrate, and the third epitaxial layer has a doping concentration gradient, and the doping concentration gradually decreases layer by layer in a direction away from the semiconductor substrate so as to serve as an etching buffer layer for thinning the semiconductor substrate.
Optionally, the material used to fill the deep trenches is polysilicon or silicon oxide.
Optionally, the method further comprises the step of forming a photodiode between the isolation structures before or after forming the isolation structures.
The application also provides an image sensor, which comprises a plurality of pixel units and a plurality of isolation structures positioned among the pixel units, wherein the isolation structures comprise:
the deep trench is positioned in the semiconductor substrate, the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base, and the deep trench extends from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer; the method comprises the steps of carrying out a first treatment on the surface of the
The second epitaxial layer is formed on the side wall of the deep groove;
and the filling layer is filled in the deep groove to form an isolation structure.
Optionally, a first dielectric layer is further included between the second epitaxial layer and the filling layer to pin the deep trench sidewalls and bottom surface.
Optionally, the thickness of the first dielectric layer is 5-100 a nm a.
Optionally, the material of the first dielectric layer is a high-K dielectric material.
Optionally, a second dielectric layer is further provided between the semiconductor substrate and the first epitaxial layer to serve as an etching stop layer when forming the deep trench.
Optionally, a third epitaxial layer is further included between the second dielectric layer and the semiconductor substrate, and the third epitaxial layer has a doping concentration gradient, and the doping concentration gradually decreases layer by layer in a direction away from the semiconductor substrate so as to serve as an etching buffer layer for thinning the semiconductor substrate.
Optionally, the material of the filling layer is polysilicon or silicon oxide.
The image sensor and the forming method thereof provided by the application have the following beneficial effects:
forming a second epitaxial layer on the side wall of the deep trench to reduce the opening size of the deep trench, form a deep trench with a smaller opening, facilitate the subsequent formation of a narrower isolation structure, increase the area of the photo-sensing area and improve the full-well capacity of the image sensor with the deep trench isolation structure;
a second dielectric layer is arranged on the semiconductor substrate and is used as an etching stop layer for forming a deep groove, so that an isolation structure with a specific depth is easy to realize;
pinning is carried out on the side wall and the bottom surface of the deep groove by adopting the first dielectric layer, so that dark current or white spot phenomenon caused by surface defects of the deep groove is reduced;
and a third epitaxial layer with doping concentration gradient is arranged in the semiconductor substrate and is used as an etching buffer layer for thinning the semiconductor substrate, so that the thinning of the semiconductor substrate is facilitated.
Drawings
Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIG. 1 is a flow chart showing a method of forming an image sensor according to the present application;
fig. 2 is a schematic structural diagram of a semiconductor substrate according to the present application;
fig. 3 is a schematic structural view of a semiconductor substrate according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of forming a patterned dielectric layer on a surface of a first epitaxial layer according to the present application;
fig. 5 is a schematic structural diagram of the etching process for etching the first epitaxial layer by using the patterned dielectric layer as a mask;
FIG. 6 is a schematic diagram showing a structure of forming a plurality of deep trenches according to the present application;
FIG. 7 is a schematic diagram showing a structure of forming a second epitaxial layer on the sidewall of the deep trench according to the present application;
FIG. 8 is a schematic diagram illustrating a structure of forming a first dielectric layer according to the present application;
fig. 9 is a schematic structural diagram of an image sensor according to the present application.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. The present application may be embodied in many other forms than those herein described, and those skilled in the art will readily appreciate that the present application may be similarly embodied without departing from the spirit or essential characteristics thereof, and therefore the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, which are only examples for convenience of illustration, and should not be construed as limiting the scope of the application.
The trench isolation structure in the CMOS image sensor is used for isolating light and charges between pixels in the CMOS image sensor so as to reduce crosstalk between pixels, and the deeper the trench is, the better the diffusion of electrons or light into adjacent pixels under the isolation trench is inhibited.
In the manufacturing process of the deep trench isolation structure in the prior art, due to the limitation of the etching process, the narrow deep trench is difficult to achieve, so that the deep trench is wider, and finally the photosensitive pixel unit is smaller, and the full-well capacity is small.
The application provides a forming method of an image sensor and the image sensor.
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings.
The application provides a forming method of an image sensor, the image sensor includes a plurality of pixel units and isolation structures between the pixel units, please refer to fig. 1, the forming method of the isolation structures of the image sensor includes:
s1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base;
s2: forming a plurality of deep trenches, wherein the deep trenches extend from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer;
s3: forming a second epitaxial layer on the side wall of the deep trench to reduce the size of an opening of the deep trench;
s4: filling a plurality of deep trenches to form a plurality of isolation structures.
Specifically, a method for forming the image sensor will be described in detail with reference to fig. 2 to 9.
Referring to fig. 2, step S1 is performed to provide a semiconductor substrate 11, wherein the semiconductor substrate 11 includes a semiconductor base 111 and a first epitaxial layer 112 on a surface of the semiconductor base.
Specifically, the semiconductor substrate 111 may be a silicon substrate, or may also be a germanium, silicon carbide, gallium arsenide, or indium phosphide substrate, or may also be an insulator-surface silicon substrate, or an insulator-surface germanium substrate, or the like. The semiconductor substrate 111 may also be a doped semiconductor substrate, and in this embodiment, the doping type of the semiconductor substrate is P-type.
Specifically, in the present embodiment, the doping type of the first epitaxial layer 112 is the same as that of the semiconductor substrate 111, and the doping type of the first epitaxial layer is P-type.
Preferably, in this embodiment, a second dielectric layer 113 is further disposed between the semiconductor substrate 111 and the first epitaxial layer 112, so as to serve as an etching stop layer when forming the deep trench, so as to control the depth of the trench.
Specifically, the second dielectric layer 113 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, or other materials with different etching ratios with single crystal silicon, so that when the deep trench is formed by using the etching process, the second dielectric layer 113 is used as an etching stop layer.
In another embodiment, referring to fig. 3, the semiconductor substrate 11 'further includes a third epitaxial layer 114' between the second dielectric layer 113 'and the semiconductor substrate 111', wherein the third epitaxial layer 114 'has a doping concentration gradient, and the doping concentration gradually decreases toward a direction away from the semiconductor substrate 111'. The third epitaxial layer 114' has a doping concentration gradient and can be used as an etching buffer layer for thinning the semiconductor substrate. For example, the preparation process of the back-illuminated image sensor comprises a thinning process of the back surface of the semiconductor substrate, and the semiconductor substrate is internally provided with a third epitaxial layer with a doping concentration gradient, so that the third epitaxial layer can be used as an etching buffer layer when the semiconductor substrate is thinned by adopting a wet etching process, thereby being beneficial to controlling the thinning depth of the semiconductor substrate.
Referring to fig. 4 to 6, step S2 is performed to form a plurality of deep trenches 12, wherein the deep trenches 12 extend from the upper surface 1121 to the lower surface 1122 of the first epitaxial layer.
Specifically, the method of forming the plurality of deep trenches 12 includes:
forming a patterned dielectric layer 13 on the surface of the first epitaxial layer 112, please refer to fig. 4;
etching the first epitaxial layer 112 by using the patterned dielectric layer 13 as a mask in an etching process, please refer to fig. 5;
with the second dielectric layer 113 as an etching stop layer, the patterned dielectric layer 13 is removed to form a plurality of deep trenches 12, and referring to fig. 6, the width of the deep trenches 12 is w1.
Referring to fig. 7, step S3 is performed to form a second epitaxial layer 15 on the sidewall of the first trench 12 to reduce the opening size of the first trench 12.
In the present application, a deep trench 12 is formed penetrating from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer. The deep trench is wider due to the limitation of the depth-to-width ratio in the trench manufacturing process, so that the light sensing area is occupied, the area of the light sensing area is relatively reduced, and the full-well capacity (full well capacity, FWC) is reduced. According to the application, the second epitaxial layer 14 is formed on the side wall of the deep trench 12, and the deep trench 12 is filled in the width direction, so that the width of the deep trench is reduced to w2, the area of the photo sensing region is ensured, and the full-well capacity of the image sensor with deep trench isolation is ensured.
Referring to fig. 8 to 9, step S4 is performed to fill a plurality of deep trenches to form a plurality of isolation structures.
Preferably, referring to fig. 8, before filling the deep trench 12, a first dielectric layer 15 is formed to cover the sidewalls and bottom of the deep trench to pin the sidewalls and bottom of the trench. And the first dielectric layer 15 is adopted to pin the surface of the deep groove, so that the defect electrons are reduced to enter the photodiode region, and the white point or dark current phenomenon of the image sensor is improved.
The material of the first dielectric layer 14 may be a high-K dielectric material, for example: silicon dioxide, silicon nitride, silicon oxynitride, titanium dioxide, aluminum oxide, or the like, or combinations thereof. The thickness of the first dielectric layer is preferably 5-100 a nm a. Of course, the setting may be performed according to actual needs, and is not limited herein.
Alternatively, in the present embodiment, the material of the filling layer 16 filling the deep trench 12 may be polysilicon or silicon oxide. The polysilicon or silicon oxide material in the deep trenches can achieve isolation between pixel cells to prevent optical or electrical cross-talk between pixel cells.
The method for forming an image sensor further comprises the step of forming a photodiode (not shown) in a pixel unit between the isolation structures before or after forming the isolation structures. Of course, other process steps for forming the pixel unit, including floating diffusion region, reset transistor, transfer transistor, etc., are also included, and the forming process is well known to those skilled in the art and will not be described herein.
The application also provides an image sensor, which comprises a plurality of pixel units and an isolation structure positioned among the pixel units, referring to fig. 9, the isolation structure comprises:
a deep trench 12 located in the semiconductor substrate 11, the semiconductor substrate 11 including a semiconductor base 111 and a first epitaxial layer 112 located on a surface of the semiconductor base 111, the deep trench 12 extending from a first epitaxial layer upper surface 1121 to a first epitaxial layer lower surface 1122;
a second epitaxial layer 14 formed on the sidewall of the deep trench 12;
and the filling layer 16 is filled in the deep trench 12 to form an isolation structure.
Preferably, there is also a first dielectric layer 15 between the fill layer 16 and the first epitaxial layer 112 to pin the deep trench sidewalls and bottom.
Preferably, between the semiconductor substrate 111 and the first epitaxial layer 112, there is also a second dielectric layer 113 to act as an etch stop layer when forming the trench.
The thickness of the first dielectric layer 15 is 5-100 a nm a. The material of the first dielectric layer 15 may be a high-K dielectric material, for example: silicon dioxide, silicon nitride, silicon oxynitride, titanium dioxide, aluminum oxide, or the like, or combinations thereof. The material of the filler layer 16 is polysilicon or silicon oxide.
Referring to fig. 3, a third epitaxial layer 114' is further included between the second dielectric layer 113' and the semiconductor substrate 111', wherein the third epitaxial layer 114' has a doping concentration gradient, and the doping concentration gradually decreases from layer to layer in a direction away from the semiconductor substrate 111 '.
For the principles, specific implementations and advantages of the image sensor, please refer to the foregoing description and the related descriptions of the forming method of the image sensor shown in fig. 1 to 9, which are not repeated herein.
It should be noted that the method for forming an image sensor and the image sensor provided by the present application can be applied to a front-illuminated image sensor or a back-illuminated image sensor, and are not limited herein.
In summary, the application provides a method for forming an image sensor and an image sensor, which are characterized in that an epitaxial layer is formed on the side wall of a deep trench to reduce the size of an opening of the deep trench, so that enough space is reserved for a pixel unit, and the full-well capacity of the pixel unit is improved; the second dielectric layer is adopted as a stop layer for deep trench etching, so that the depth of the deep trench is easy to control; providing a first dielectric layer, realizing pinning effect on the side wall and the bottom surface of the groove, and reducing white spot phenomenon of the image sensor; the deep grooves are filled with polysilicon or silicon oxide, so that effective isolation among pixel units is realized, optical crosstalk and electrical crosstalk among the pixel units are reduced, and the performance of the image sensor is improved.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (17)
1. A method for forming an image sensor, the image sensor comprising a plurality of pixel units and an isolation structure between the pixel units, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base;
forming a plurality of deep trenches, wherein the deep trenches extend from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer;
forming a second epitaxial layer on the side wall of the deep trench to reduce the size of an opening of the deep trench;
filling a plurality of deep trenches to form a plurality of isolation structures.
2. The method of forming an image sensor of claim 1, further comprising: before filling the deep trench, forming a first dielectric layer on the side wall and the bottom surface of the deep trench to pin the side wall and the bottom surface of the deep trench.
3. The method of claim 2, wherein the material of the first dielectric layer is a high-K dielectric material.
4. The method of forming an image sensor of claim 2 wherein the first dielectric layer has a thickness of 5-100 a nm a.
5. The method of claim 1, further comprising a second dielectric layer between the semiconductor substrate and the first epitaxial layer to act as an etch stop layer in forming the deep trench.
6. The method of forming an image sensor of claim 5, wherein the method of forming a plurality of deep trenches comprises:
forming a patterned dielectric layer on the surface of the first epitaxial layer;
etching the first epitaxial layer by adopting an etching process and taking the patterned dielectric layer as a mask;
and forming a plurality of deep trenches in the first epitaxial layer by taking the second dielectric layer as an etching stop layer.
7. The method of claim 5, wherein the second dielectric layer is formed of one or more of silicon oxide, silicon nitride, and silicon oxynitride.
8. The method of claim 5, further comprising a third epitaxial layer between the second dielectric layer and the semiconductor substrate, the third epitaxial layer having a doping concentration gradient, the doping concentration decreasing layer by layer away from the semiconductor substrate to act as an etch buffer for thinning the semiconductor substrate.
9. The method of claim 1, wherein the material used to fill the deep trenches is polysilicon or silicon oxide.
10. The method of forming an image sensor of claim 1, further comprising the step of forming a photodiode between the isolation structures before or after forming the isolation structures.
11. An image sensor comprising a plurality of pixel cells and a plurality of isolation structures between the pixel cells, the isolation structures comprising:
the deep trench is positioned in the semiconductor substrate, the semiconductor substrate comprises a semiconductor base and a first epitaxial layer positioned on the surface of the semiconductor base, and the deep trench extends from the upper surface of the first epitaxial layer to the lower surface of the first epitaxial layer;
the second epitaxial layer is formed on the side wall of the deep groove;
and the filling layer is filled in the deep groove to form an isolation structure.
12. The image sensor of claim 11, further comprising a first dielectric layer between the second epitaxial layer and the fill layer to pin the deep trench sidewalls and bottom surface.
13. The image sensor of claim 12, wherein the first dielectric layer has a thickness of 5-100 a nm a.
14. The image sensor of claim 12, wherein the material of the first dielectric layer is a high-K dielectric material.
15. The image sensor of claim 11, further comprising a second dielectric layer between the semiconductor substrate and the first epitaxial layer to act as an etch stop layer when forming the deep trench.
16. The image sensor of claim 15, further comprising a third epitaxial layer between the second dielectric layer and the semiconductor substrate, the third epitaxial layer having a doping concentration gradient that decreases layer by layer in a direction away from the semiconductor substrate to act as an etch buffer for thinning of the semiconductor substrate.
17. The image sensor of claim 11, wherein the material of the filler layer is polysilicon or silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210620846.XA CN117219641A (en) | 2022-06-02 | 2022-06-02 | Image sensor and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210620846.XA CN117219641A (en) | 2022-06-02 | 2022-06-02 | Image sensor and forming method thereof |
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| CN117219641A true CN117219641A (en) | 2023-12-12 |
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