CN117219622A

CN117219622A - Capacitor and device comprising same and preparation method thereof

Info

Publication number: CN117219622A
Application number: CN202310682672.4A
Authority: CN
Inventors: 金亨俊; 朴报恩; 庞桢一; 金载兴; 李周浩
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-06-10
Filing date: 2023-06-09
Publication date: 2023-12-12

Abstract

The application relates to a capacitor and a device comprising the same, and a method for manufacturing the same. The capacitor may include a first thin film electrode layer; a second thin film electrode layer; and a dielectric layer between the first thin film electrode layer and the second thin film electrode layer. The first thin film electrode layer and the second thin film electrode layer may include conductive perovskite type crystal structures. The dielectric layer may include a metal oxide having a dielectric perovskite crystal structure. The dielectric layer may be an epitaxial layer. The metal oxide may include a first element in a cuboctahedral site, a second element in an octahedral site, and a third element in an octahedral site. The third element may have a lower valence than the second element, and the third element may be a dopant.

Description

Capacitor and device comprising same and preparation method thereof

Cross reference to related applications

The present application is based on and claims priority from korean patent application No. 10-2022-007106 filed in the korean intellectual property office at 10/6/2022 and korean patent application No.10-2022-0163246 filed in 11/2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to capacitors, devices (apparatuses) including the same, and methods of making the same.

Background

Semiconductor devices (equipment), such as memories and transistors, are used in a variety of household and industrial equipment. According to the increasingly higher performance of household and industrial equipment, semiconductor devices are becoming highly integrated and miniaturized.

As semiconductor devices become highly integrated and miniaturized, the size of the semiconductor devices is reduced.

For example, since the capacitance of the capacitor decreases and the leakage current may increase as the size of the capacitor decreases, various methods have been proposed to solve the problem.

The capacitance of the capacitor may be maintained, for example, by modifying the structure of the capacitor, by increasing the electrode area of the capacitor, or by reducing the dielectric thickness, or by improving the capacitor manufacturing process.

Disclosure of Invention

However, there are limitations in maintaining the capacitance of the capacitor by structural modification such as increasing the electrode surface of the capacitor or reducing the dielectric material thickness, or by improving the manufacturing process.

For high capacitance of the capacitor, a ternary oxide dielectric material may be used. Typical ternary oxide dielectrics are perovskite crystal structure materials that are ternary oxides containing divalent cations and tetravalent cations, where the composition ratio of divalent cations, tetravalent cations, and oxygen is 1:1:3. Examples of the ternary oxide dielectric material include, for example, srTiO ₃ 、CaTiO ₃ 、BaTiO ₃ 、SrHfO ₃ 、SrZrO ₃ And PbTiO ₃ Is a material of (3). The ternary oxide dielectric material is not limited to the foregoing materials, and ternary oxides containing other cations may be used as the dielectric material.

As the film thickness decreases, the ternary oxide dielectric material experiences a sharp decrease in permittivity. Further, since the ternary oxide dielectric material has a small band gap of about 3eV to about 4eV, leakage current between the electrode and the dielectric material may be large.

Therefore, it is important to suppress the decrease in permittivity due to the decrease in thickness of the dielectric thin film, and the leakage current between the control electrode and the dielectric material.

In order to suppress the decrease in permittivity due to the decrease in thickness of the dielectric thin film, a polycrystalline dielectric material thin film having an increased grain size may be considered. The polycrystalline dielectric material film having increased grain size may be prepared by: dopants are implanted into the amorphous dielectric material film and phase change is induced by heat treatment. The thin film of polycrystalline dielectric material with increased grain size may cause problems such as formation of a low-k dielectric layer at the electrode-dielectric material interface and limited polarization orientation (polarization alignment). Thus, the polycrystalline dielectric material film with increased grain size is formed Or less, is limited in controlling the permittivity.

Thus, there is a need for a new type of capacitor as follows: by having a novel structure compared with a conventional capacitor, it is possible to suppress a decrease in permittivity due to a decrease in thickness of a dielectric material film, and to control leakage current between an electrode and a dielectric material.

A capacitor is provided, which includes a dielectric material and an electrode, having a novel structure, thereby suppressing a decrease in permittivity due to a decrease in thickness of the dielectric material and controlling leakage current.

A device comprising the capacitor is provided.

Methods of making the capacitors are provided.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to an example embodiment, a capacitor may include: a first thin film electrode layer; a second thin film electrode layer; and a dielectric layer between the first thin film electrode layer and the second thin film electrode layer. The first thin film electrode layer and the second thin film electrode layer may each have a conductive perovskite crystal structure. The dielectric layer may include a metal oxide having a dielectric perovskite crystal structure, and the dielectric layer may be an epitaxial layer. The metal oxide may include a first element in a cuboctahedral site (cubococtahedral), a second element in an octahedral site, and a third element in an octahedral site. The third element may have a lower valence than the second element. The third element may be a dopant.

According to example embodiments, the device may include the above capacitor.

According to example embodiments, a method of preparing a capacitor may include: forming a dielectric layer on one side of the first thin film electrode layer by epitaxial growth; and forming a second thin film electrode layer on the dielectric layer to thereby provide the capacitor. The capacitor may include the dielectric layer between the first thin film electrode layer and the second thin film electrode layer. The first thin film electrode layer and the second thin film electrode layer may have conductive perovskite type crystal structures. The dielectric layer may include a metal oxide having a dielectric perovskite crystal structure. The metal oxide may include a first element in a cuboctahedral site, a second element in an octahedral site, and a third element in an octahedral site. The third element may have a lower valence than the second element. The third element may be a dopant.

Drawings

The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings in which:

fig. 1 is a cross-sectional view of a capacitor prepared in example 1;

FIG. 2 is a graph showing the permittivity as a function of dielectric layer thickness of the capacitors prepared in examples 1-6 and comparative examples 1-3;

FIG. 3 is a graph showing leakage current as a function of dielectric layer thickness for the capacitors prepared in examples 1-6 and comparative examples 1-3;

FIG. 4 is an XRD spectrum of the surface of a STO substrate/undoped BST dielectric layer stack and a STO substrate/Y-doped BST dielectric layer stack prepared at 700 ℃;

FIG. 5 is a rocking curve of the surface of a STO substrate/Y-doped BST dielectric layer stack prepared at 700 ℃;

FIG. 6 is an XRD pattern for the surface of STO substrate/undoped BST dielectric layer stack and STO substrate/Y-doped BST dielectric layer stack prepared at 500 ℃;

FIG. 7 is an XRD pattern for the surface of STO substrate/undoped BST dielectric layer stack and STO substrate/Y-doped BST dielectric layer stack prepared at 300 ℃;

8A-8G are schematic diagrams of a capacitor according to an embodiment;

fig. 9 is a circuit diagram schematically showing a circuit configuration and operation of an electronic device employing a capacitor according to an embodiment;

FIG. 10 is a schematic diagram showing an electronic device according to one embodiment;

fig. 11 is a schematic diagram showing an electronic device according to another embodiment;

Fig. 12 is a plan view of an electronic device according to another embodiment;

fig. 13 is a cross-sectional view illustrating an electronic device according to another embodiment;

FIG. 14 is a cross-sectional view of an electronic device according to another embodiment;

FIG. 15 is a schematic diagram schematically illustrating a device architecture applicable to a device according to one embodiment; and

fig. 16 is a schematic diagram schematically showing a device architecture applicable to a device according to another embodiment.

Detailed Description

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiment may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below to illustrate aspects by referring only to the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The expression "at least one of the elements" for example, modifies the entire list of elements when before or after the list of elements without modifying individual elements of the list. For example, "A, B, and at least one of C" and similar language (e.g., "at least one of C selected from A, B," and C ") may be interpreted as a alone, B alone, C alone, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

When the term "about" or "substantially" is used in this specification with respect to a numerical value, it is intended that the relevant numerical value includes manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value. Furthermore, when the terms "substantially" and "essentially" are used in relation to a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather that the tolerance for the shape is within the scope of the present disclosure. Furthermore, whether or not a value or shape is modified to be "about" or "substantially," it will be understood that such value or shape should be interpreted to include manufacturing or operating tolerances (e.g., ±10%) around the stated value or shape. When a range is recited, the range includes all values therebetween, e.g., 0.1% increments.

The embodiments of the inventive concepts described below are susceptible of numerous variations and many embodiments, specific embodiments being shown in the drawings and described in detail in the written description. However, the inventive concepts should not be construed as being limited to the particular embodiments set forth herein. Rather, these embodiments are to be construed as encompassing all modifications, equivalents, or alternatives falling within the scope of the inventive concept.

The terminology used hereinafter is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise. As used herein, the terms "comprises" or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements (components), compositions, materials, or combinations thereof, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements (components), compositions, materials, or groups thereof. As used herein, "/" may be interpreted as "and" or as "or" depending on the context.

In the drawings, the thickness of layers and regions may be exaggerated for clarity and convenience of description. Like numbers refer to like elements throughout. When an element such as a layer, film, region, or plate is referred to as being "over" or "on" another element, it can be directly over the other element or still be there between. It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. In the present specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description thereof is omitted.

Hereinafter, a capacitor, a device including the same, and a method of manufacturing the capacitor according to example embodiments will be described in more detail.

A capacitor according to an embodiment may include: a first thin film electrode layer; a second thin film electrode layer; and a dielectric layer disposed between the first thin film electrode layer and the second thin film electrode layer, wherein the first thin film electrode layer and the second thin film electrode layer may include a conductive perovskite-type crystal structure, the dielectric layer may include a metal oxide having a dielectric perovskite-type crystal structure, the dielectric layer may be an epitaxial layer, and the metal oxide may include a first element disposed in a cubo-octahedral site, a second element disposed in an octahedral site, and a third element disposed in an octahedral site, wherein a valence of the third element may be lower than a valence of the second element, and the third element may be a dopant.

The first thin film electrode layer, the second thin film electrode layer, and the dielectric layer may have a perovskite crystal structure. Between the first thin film electrode layer and the second thin film electrode layer having a perovskite-type crystal structure, a dielectric layer having a well-defined orientation (well-defined orientation), that is, a dielectric layer having a perovskite-type crystal structure may be disposed. For example, the dielectric layer may include a metal oxide having a perovskite-type crystal structure with high crystallinity. For example, the dielectric layer may comprise a metal oxide having a single crystal or a crystallinity close thereto. Since the first thin film electrode layer, the second thin film electrode layer, and the dielectric layer all have the same perovskite-type crystal structure, formation of a low-k dielectric layer at an electrode layer-dielectric layer interface can be suppressed. Since polarization orientation within the dielectric layer can be improved due to the dielectric layer having high crystallinity, as a result, permittivity of the dielectric layer can be improved. The first thin film electrode layer, the second thin film electrode layer, and the dielectric layer may each be, for example, a single crystal having a perovskite crystal structure.

Since the metal oxide includes an octahedral site and the third element having a lower valence than that of the second element is located in the octahedral site, lattice expansion can be induced in the octahedral site, and as a result, compressive strain in the lattice structure can be induced. Since the lattice structure located at the electrode layer-dielectric layer interface contains compressive strain induced without degradation, the interfacial permittivity between the electrode layer and the dielectric layer can be increased. As the thickness of the dielectric layer decreases, the influence of the interfacial permittivity between the dielectric layer and the electrode layer, in addition to the bulk permittivity of the dielectric material (dielectric material), among the total permittivity of the dielectric layer increases. Accordingly, in a capacitor having a dielectric layer having an increased interface permittivity, a decrease in permittivity of the capacitor due to a decrease in thickness of the dielectric layer can be effectively suppressed.

The second element may have a valence of, for example, 4 or more. The valence of the second element may be 4, 5, or 6. The third element may have a valence of, for example, 3 or less. The valence of the third element may be, for example, 3, 2, or 1. Since the third element has a lower valence than the second element, lattice expansion in the octahedral site can be induced more effectively.

For example, the third element may be a metal or metalloid element of groups 1 to 16 of the periodic table. The third element may be, for example, at least one element selected from Y, mg, ni, fe, mn, co, al, cr, bi, and Ga. Since the third element includes the aforementioned metal or metalloid element, lattice expansion in the octahedral site can be induced more effectively. The third element may have one or more valence states. For example, mn may have variable valences such as 2, 3, etc.

The ionic radius of the third element may be, for example, greater than the ionic radius of the second element. Since the ionic radius of the third element is larger than that of the second element, lattice expansion in the octahedral site can be induced more effectively. As the ionic radius of the third element increases, the lattice expansion in the octahedral site may increase. For example, the cation of the third element may have an ionic radius greater than the ionic radius of the cation of the second element. The difference between the ionic radius of the third element and the ionic radius of the second element may be, for example, 1pm or more, 5pm or more, or 10pm or more. The difference between the ionic radius of the third element and the ionic radius of the second element may be, for example, from about 1pm to about 50pm, from about 5pm to about 50pm, or from about 10pm to about 50pm.

The metal oxide may be, for example, a ternary metal oxide. The ternary metal oxide may include a first element, a second element, and oxygen. At least one of the first element and the second element in the ternary metal oxide may be further substituted with another element. The substituted ternary metal oxide may further include, for example, a third element that replaces a portion of the second element, and optionally a fourth element that replaces a portion of the first element.

The lattice of the metal oxide may have, for example, a compressive strain along the c-axis. Since the metal oxide includes an octahedral site, and a third element having an ionic radius larger than that of the second element is substituted in the octahedral site, for example, the crystal lattice of the metal oxide may have, for example, compressive strain along a vertical c-axis direction (i.e., a direction coming out of the electrode layer-dielectric layer interface). Polarization can be induced more effectively due to deformation of the lattice along the c-axis, thereby improving permittivity.

The metal oxide may include a lattice, and the lattice includes an a-axis lattice constant, a b-axis lattice constant, and a c-axis lattice constant, wherein the c-axis lattice constant may be greater than, for example, at least one of the a-axis lattice constant and the b-axis lattice constant.

The c-axis lattice constant may be, for example Or->Since the c-axis lattice constant has a size in the foregoing range, a decrease in permittivity due to a decrease in volume of a capacitor including a dielectric layer can be more effectively suppressed. The c-axis lattice constant can be measured, for example, by XRD patterns.

The third element may be included in the metal oxide in an amount of, for example, about 0.1 atom% to about 9 atom%, about 0.1 atom% to about 7 atom%, about 0.5 atom% to about 5 atom%, about 0.5 atom% to about 3 atom%, about 1.0 atom% to about 2 atom%, or about 1.5 atom% to about 2 atom%, relative to the sum of the second element and the third element. Since the content of the third element in the metal oxide is within the foregoing range, a decrease in permittivity due to a decrease in volume of a capacitor including a dielectric layer can be more effectively suppressed. The content of the third element may be measured, for example, by XPS.

The dielectric layer may include, for example, a metal oxide represented by formula 1:

1 (1)

A1 _1-a D1 _a B1 _1-b C1 _b O _3-δ

In the formula (1) of the present invention,

0.ltoreq.a <1,0.001< b <0.09, and 0.ltoreq.delta.ltoreq.0.5,

a1 and D1 may each be an element having a valence of 2,

b1 can be an element having a valence of 4, and

C1 may be an element having a valence of 1, an element having a valence of 2, or an element having a valence of 3.

In formula 1, C1 may be, for example, at least one element selected from Y, mg, ni, fe, mn, co, al, cr, bi, and Ga.

In formula 1, for example, 0.1.ltoreq.a.ltoreq. 0.9,0.2.ltoreq.a.ltoreq.0.8, or 0.3.ltoreq.a.ltoreq.0.7.

The dielectric layer may include, for example, a metal oxide represented by the following formula 2:

2, 2

Ba _1-a Sr _a Ti _1-b C2 _b O _3-δ

In the formula (2) of the present invention,

0.ltoreq.a <1,0.001< b <0.08 and 0.ltoreq.delta.ltoreq.0.5, and C2 may be at least one element selected from Y, mg, ni, fe, mn, co, al, cr, bi, and Ga.

In formula 2, for example, 0.1.ltoreq.a.ltoreq. 0.9,0.2.ltoreq.a.ltoreq.0.8, or 0.3.ltoreq.a.ltoreq.0.7.

On the XRD spectrum of the dielectric layer, rocking curves can be measured by theta scanning, for example, between the X-ray source and the sample surface. The rocking curve may, for example, have a first peak for the (200) plane at a diffraction angle of θ=22.5° ±0.5°, and the half-width (FWHM) of the first peak may be 0.1 ° or less, 0.08 ° or less, or 0.06 ° or less. Since the FWHM of the first peak of the dielectric layer is 0.1 ° or less, the dielectric layer may have a high crystallinity. The dielectric layer may have a crystalline structure such as single crystal or the like. The dielectric layer may have a crystal structure different from a polycrystalline crystal structure and an amorphous structure.

The capacitor may include a dielectric layer and the capacitor is formed on the dielectric layerHas a first relative permittivity (εr 1), and +.>Has a second relative permittivity (er 2), wherein the ratio (er 2/er 1) of the second relative permittivity (er 2) to the first relative permittivity (er 0r 1) may be, for example, 0.20 or more, 0.25 or more, or 0.30 or more. For example, the ratio (εr2/εr1) of the second relative permittivity (εr2) to the first relative permittivity (εr1) may be, for example, 0.20-1.0, 0.25-0.90, or 0.30-0.80. Since the capacitor has such a ratio (er 2/er 1) of the second relative permittivity to the first relative permittivity, a decrease in permittivity of the capacitor due to a decrease in volume can be effectively suppressed. The capacitor may comprise a dielectric layer and in +.> Or->May have a relative permittivity of 100 or greater, 150 or greater, 200 or greater, 250 or greater, 300 or greater, 350 or greater, or 400 or greater. The dielectric layerThe permittivity of (C) can be measured at room temperature (25 ℃) at 1kHz-1 MHz. The capacitor may include a dielectric layer and is formed on Or->The leakage current of the capacitor may be, for example, 1×10 ^-5 A/cm ² Or smaller, 5×10 ^-6 A/cm ² Or smaller, 1×10 ^-6 A/cm ² Or smaller, 5×10 ^-7 A/cm ² Or smaller, or 1X 10 ^-7 A/cm ² Or smaller.

For example, the thickness of the dielectric layer may be Or->Or (b)When the thickness of the dielectric layer is too small, the capacitance per unit volume of the capacitor may be reduced. When the thickness of the dielectric layer is too large, it may be difficult to satisfy the volume of the capacitor required for the memory device. The thickness of the dielectric layer may be measured by, for example, transmission electron microscopy, atomic force microscopy, or the like.

The dielectric layer may have one or more structures selected from, for example, a flat plate structure, a trench structure, and a pillar structure, but is not limited thereto, and any structure available in the art may be used. With such a structure, the dielectric layer can be applied to various types of devices. The dielectric layer may have, for example, a single-layer structure or a multi-layer structure. The multilayer structure may be a two-layer structure, a three-layer structure, a four-layer structure, or the like, but is not necessarily limited thereto, and may have a multilayer structure including more layers depending on the required performance.

For example, the dielectric layer may be an epitaxial layer. For example, the dielectric layer may be formed by epitaxial growth. Thus, the dielectric layer may have the same or similar crystal structure, or the same or similar lattice constant, etc., as the thin film electrode layer, and may have improved interface stability. A portion or the entire dielectric layer may include an epitaxial region.

At least one selected from the first thin film electrode layer and the second thin film electrode layer may include a metal oxide. The metal oxide may be, for example, a ternary metal oxide. The ternary metal oxide included in the electrode layer may include, for example, a first element. Thus, the first thin film electrode layer and/or the second thin film electrode layer, and the dielectric layer may both include the first element.

The first thin film electrode layer and the second thin film electrode layer may each independently include, for example, at least one selected from the group consisting of: srRuO ₃ 、SrVO ₃ 、SrNbO ₃ 、SrMnO ₃ 、SrCrO ₃ 、SrFeO ₃ 、SrCoO ₃ 、SrMoO ₃ 、SrIrO ₃ 、CaRuO ₃ 、CaNiO ₃ 、BaRuO ₃ And (Ba, sr) RuO ₃ 。

The capacitor may further include an intermediate layer disposed between the first thin film electrode layer and the dielectric layer, or between the second thin film electrode layer and the dielectric layer, or both.

Since the ternary metal oxide dielectric material has a small band gap of about 3eV to about 4eV, leakage current between the electrode layer and the dielectric layer may be large. Therefore, control of leakage current between the electrode layer and the dielectric layer is important. In order to correct leakage current characteristics between the electrode layer and the dielectric layer, a method of controlling a Schottky (Schottky) barrier may be considered. The schottky barrier is the difference between the work function (Φ) of the electrode layer and the electron affinity (χ, electron affinity) of the dielectric layer. When the electrode layer and the dielectric layer are in contact with each other, their fermi levels are aligned, and thus an energy barrier called a schottky barrier is formed at the interface between the electrode layer and the dielectric layer, which suppresses movement of charges, thereby improving leakage current. In order to achieve a high Schottky Barrier Height (SBH) between the dielectric layer and the electrode layer, various conditions need to be satisfied. For example, the following may be required: the dielectric layer and the electrode layer have similar crystal structures and lattice constants, the dielectric layer-electrode layer interface has high stability, and the work function of the electrode layer is greater than the electron affinity of the dielectric layer. It may be difficult to obtain (derive) a combination of the dielectric layer and the electrode layer satisfying the above conditions. Therefore, by further introducing an intermediate layer between the electrode layer and the dielectric layer, leakage current of the capacitor can be further suppressed by increasing the schottky barrier height between the electrode layer and the dielectric layer.

The intermediate layer may have, for example, the same type of crystal structure as at least one of the first thin film electrode layer, the second thin film electrode layer, and the dielectric layer, which are each in contact with the intermediate layer, and may have a composition different from those of the first thin film electrode layer, the second thin film electrode layer, and the dielectric layer.

The intermediate layer may have, for example, a perovskite crystal structure. Thus, the electrode layer, the dielectric layer, and the intermediate layer may each have a perovskite crystal structure. For example, the intermediate layer may be a single crystal.

For example, the intermediate layer may include a metal oxide selected from metal oxides represented by formulas 3 to 5:

3

A2B2O _3-δ1

In the case of the method of 3,

a2 may be an element having a valence of 2, B2 may be an element having a valence of 1, an element having a valence of 2, or an element having a valence of 3, and 1.5.ltoreq.3- δ1.ltoreq.3.0,

4. The method is to

A3B3O _3-δ2

In the case of the method of claim 4,

a3 may be an element having a valence of 1, B3 may be an element having a valence of 4, and 1.5.ltoreq.3- δ2.ltoreq.3.0.

5. The method is to

A4B4O _3-δ3

In the case of the method of claim 5,

a4 may be an element having a valence of 3, B4 may be an element having a valence of 3, and 2.5.ltoreq.3- δ3.ltoreq.3.0.

In formula 3, for example, A2 may be a divalent cation, and B2 may be a monovalent cation, a divalent cation, or a trivalent cation and have an atomic weight of 20 or more. In formula 4, for example, A3 may be a monovalent cation, and B3 may be a tetravalent cation. In formula 5, for example, A4 may be a trivalent cation, and B4 may be a trivalent cation.

The intermediate layer may include, for example, the following metal oxides: selected from SrGaO _3-δ1 、CaGaO _3-δ1 、BaGaO _3-δ1 、MgGaO _3-δ1 、BeGaO _3-δ1 、SrInO _3-δ1 、CaInO _3-δ1 、BaInO _3-δ1 、MgInO _3-δ1 、BeInO _3-δ1 、SrBeO _3-δ1 、CaBeO _3-δ1 、BaBeO _3-δ1 、MgBeO _3-δ1 、SrMgO _3-δ1 、CaMgO _3-δ1 、BaMgO _3-δ1 、BeMgO _3-δ1 、SrBaO _3-δ1 、CaBaO _3-δ1 、MgBaO _3-δ1 、BeBaO _3-δ1 、SrCaO _3-δ1 、BaCaO _3-δ1 、MgCaO _3-δ1 、BeCaO _3-δ1 、SrLiO _3-δ1 、CaLiO _3-δ1 、BaLiO _3-δ1 、MgLiO _3-δ1 、BeLiO _3-δ1 、SrNaO _3-δ1 、CaNaO _3-δ1 、BaNaO _3-δ1 、MgNaO _3-δ1 、BeNaO _3-δ1 、SrKO _3-δ1 、CaKO _3-δ1 、BaKO _3-δ1 、MgKO _3-δ1 、BeKO _3-δ1 、SrRbO _3-δ1 、CaRbO _3-δ1 、BaRbO _3-δ1 、MgRbO _3-δ1 And BerbO _3-δ1 The method comprises the steps of carrying out a first treatment on the surface of the Or is selected from LiTiO _3-δ2 、NaTiO _3-δ2 、KTiO _3-δ2 、RbTiO _3-δ2 、LiZrO _3-δ2 、NaZrO _3-δ2 、KZrO _3-δ2 、RbZrO _3-δ2 、LiHfO _3-δ2 、NaHfO _3-δ2 、KHfO _3-δ2 And RbHfO _3-δ2 The method comprises the steps of carrying out a first treatment on the surface of the Or is selected from Scalo _3-δ3 、YAlO _3-δ3 、LaAlO _3-δ3 、CeAlO _3-δ3 、PrAlO _3-δ3 、NdAlO _3-δ3 、SmAlO _3-δ3 、DyAlO _3-δ3 、ScGaO _3-δ3 、YGaO _3-δ3 、LaGaO _3-δ3 、CeGaO _3-δ3 、PrGaO _3-δ3 、NdGaO _3-δ3 、SmGaO _3-δ3 、DyGaO _3-δ3 、ScInO _3-δ3 、YInO _3-δ3 、LaInO _3-δ3 、CeInO _3-δ3 、PrInO _3-δ3 、NdInO _3-δ3 、SmInO _3-δ3 And DyInO (DyIno) _3-δ3 Wherein, 1.5 is less than or equal to 3-delta 1 is less than or equal to 3.0,1.5 is less than or equal to 3-delta 2 is less than or equal to 3.0, and 2.5 is less than or equal to 3-delta 3 is less than or equal to 3.0.

The intermediate layer may have, for exampleOr-> Is a thickness of (c). Since the intermediate layer has a thickness within the above range, the intermediate layer may have an increased Schottky Barrier Height (SBH) while maintaining structural stability of the intermediate layer.

In the capacitor including the intermediate layer, a Schottky Barrier Height (SBH) between the first or second thin film electrode layer and the dielectric layer may be 1.5eV or more, or 1.8eV or more. For example, in a capacitor including the intermediate layer, a Schottky Barrier Height (SBH) between the first or second thin film electrode layer and the dielectric layer may be about 1.5eV to about 2.5eV, or about 1.8eV to about 2.1eV. In the capacitor including the intermediate layer, since the schottky barrier height between the first or second thin film electrode layer and the dielectric layer has a value in the above range, leakage current can be more effectively controlled.

The intermediate layer may be, for example, an epitaxial layer. The intermediate layer may be formed by, for example, epitaxial growth. The intermediate layer may have, for example, the same or similar crystal structure, the same or similar lattice constant, or the like as the thin film electrode layer and/or the dielectric layer, and interface stability may be improved.

The type of the capacitor is not particularly limited. The capacitor may be, for example, a capacitor element included in a memory cell, a multilayer capacitor used in a multilayer ceramic capacitor (condenser), or the like.

Fig. 8A-8G are schematic diagrams of a capacitor 20 according to an embodiment.

Fig. 8A shows the structure of the capacitor 20 including the dielectric layer 12 described above. The capacitor 20 may further include an insulating substrate 100. In this structure, the capacitor 20 may include an insulating substrate 100, and a first thin film electrode 11, a dielectric layer 12, and a second thin film electrode 13. The first and second thin film electrodes 11 and 13 may serve as lower and upper thin film electrodes, respectively. The first and second thin film electrodes 11 and 13 may not be electrically connected, and the dielectric layer 12 may be disposed between the first and second thin film electrodes 11 and 13. The dielectric layer 12 may be doped with a third element, and the first thin film electrode 11, the dielectric layer 12, and the second thin film electrode 13 may have a perovskite-type crystal structure. The third element may be Y, mg, ni, fe, mn, co, al, cr, bi, or Ga, for example. An intermediate layer may be further arranged between the first thin film electrode 11 and the dielectric layer 12 and/or between the second thin film electrode 13 and the dielectric layer 12. For example, as depicted in fig. 8E, the intermediate layer 9 may be between the first thin film electrode 11 and the dielectric layer 12. As depicted in fig. 8F, the intermediate layer 9 may be between the second thin film electrode 13 and the dielectric layer 12.

Fig. 8B-8D and 8G show examples of additional structures of capacitors 20 including dielectric layer 12 as described above.

In fig. 8B, the dielectric layer 12 may be disposed to cover the first thin film electrode 11 on the insulating substrate 100, and the second thin film electrode 13 may be disposed to cover the dielectric layer 12. The dielectric layer 12 may be doped with a third element, and the first thin film electrode 11, the dielectric layer 12, and the second thin film electrode 13 may have a perovskite-type crystal structure. An intermediate layer (not shown) may be further arranged between the first thin film electrode 11 and the dielectric layer 12 and/or between the second thin film electrode 13 and the dielectric layer 12.

In fig. 8C, on the insulating substrate 100, the first and second thin film electrodes 11 and 13 may be disposed, and the dielectric layer 12 may be disposed therebetween. The dielectric layer 12 may be doped with a third element, and the first thin film electrode 11, the dielectric layer 12, and the second thin film electrode 13 may have a perovskite-type crystal structure. An intermediate layer (not shown) may be further arranged between the first thin film electrode 11 and the dielectric layer 12 and/or between the second thin film electrode 13 and the dielectric layer 12.

In fig. 8D, the dielectric layer 12 may be disposed to cover a portion of the first thin film electrode 11 on the insulating substrate 100, and the second thin film electrode 13 may be disposed to cover another portion of the dielectric layer 12. The dielectric layer 12 may be doped with a third element, and the first thin film electrode 11, the dielectric layer 12, and the second thin film electrode 13 may have a perovskite-type crystal structure. An intermediate layer (not shown) may be further arranged between the first thin film electrode 11 and the dielectric layer 12 and/or between the second thin film electrode 13 and the dielectric layer 12.

In fig. 8G, the dielectric layer 12 may be disposed to surround the first thin film electrode 11 on the insulating substrate 100, and the second thin film electrode 13 may surround the dielectric layer 12. The first thin film electrode 11, the dielectric layer 12, and the second thin film electrode 13 may be concentrically arranged, with the dielectric layer 12 being intermediate the first and second thin film electrodes 11 and 13. Although not shown, an intermediate layer may be between at least one of the first and second thin film electrodes 11 and 13 and the dielectric layer 12.

The capacitor can be used in a variety of electronic devices. The above capacitor may be used as a DRAM device together with a transistor. In addition, the above-described capacitor may form part of an electronic circuit that constitutes an electronic device together with other circuit elements.

Fig. 9 shows a circuit diagram showing a schematic circuit configuration and operation of an electronic device employing a capacitor according to an embodiment.

The circuit diagram of the electronic device 1000 relates to a single Dynamic Random Access Memory (DRAM) cell that includes a single transistor TR, a single capacitor CA, a word line WL, and a bit line BL. Capacitor CA may be the capacitor described in FIGS. 1 and 8A-8G.

Data may be written to the DRAM as follows. After a gate voltage (high) that changes the transistor TR to an 'on (conductive)' state is applied to the gate electrode via the word line WL, VDD (high), or 0 (low), which is a data voltage value to be input to the bit line BL, may be applied. Once a high voltage is applied to the word line and the bit line, the capacitor CA may be charged to write data "1". Once a high voltage is applied to the word line and a low voltage is applied to the bit line, capacitor CA is discharged, writing a "0".

When reading data, in order to turn on the transistor TR of the DRAM, a high voltage is applied to the word line WL and a VDD/2 voltage is applied to the bit line BL. If the data of the DRAM is "1", i.e., the voltage of the capacitor CA is VDD, the charge in the capacitor CA slowly moves to the bit line BL, resulting in a bit line BL having a voltage slightly higher than VDD/2. Conversely, when the data of the DRAM is "0", the charge in the bit line BL moves to the capacitor CA, resulting in a bit line BL having a voltage slightly lower than VDD/2. The potential difference thus generated is detected at the sense amplifier, and by amplifying the value, it can be determined whether the corresponding data is "0" or "1".

Fig. 10 is a schematic diagram showing an electronic device according to an embodiment.

Referring to fig. 10, an electronic device 1001 may have a capacitor CA1 and a transistor TR electrically connected to each other through a contact 120. The capacitor CA1 may include a lower electrode 201, an upper electrode 401, and a dielectric film 301 disposed between the lower electrode 201 and the upper electrode 401. The capacitor CA1 may be a capacitor as described above with reference to FIGS. 1 and 8A-8G. Therefore, a further description thereof will be omitted.

The transistor TR may be a field effect transistor. The transistor TR may include a semiconductor substrate SU provided with an active region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU facing the channel region CH and having a gate insulating layer GI and a gate electrode GA.

The channel region CH, which is a region between the source region SR and the drain region DR, may be electrically connected to the source region SR and the drain region DR. The source region SR may be electrically connected or contacted with one end portion of the channel region CH, and the drain region DR may be electrically connected or contacted with the other end portion of the channel region CH. The channel region CH may be defined as a substrate region between the source region SR and the drain region DR in the semiconductor substrate SU.

The semiconductor substrate SU may comprise a semiconductor material. The semiconductor substrate SU may include a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and the like. In addition, the semiconductor substrate SU may include a silicon-on-insulator (SOI) substrate.

The source region SR, the drain region DR, and the channel region CH may be independently formed by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, the channel region CH, and the drain region DR may include a base material as a base material. The source region SR and the drain region DR may be formed of a conductive material. In this case, the source region SR and the drain region DR may include, for example, a metal compound, or a conductive polymer.

The channel region CH may be implemented as a separate material layer (thin film) unlike that shown in the figures. In this case, the channel region CH may include, for example, at least one from among: si, ge, siGe, III-group V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional materials (2D materials), quantum dots, and organic semiconductors. The oxide semiconductor may include, for example, inGaZnO or the like. The 2D material may include, for example, transition Metal Dichalcogenides (TMD) or graphene. The quantum dots may include, for example, colloidal QDs or nanocrystal structures.

The gate electrode GA may be disposed on the semiconductor substrate SU to face the channel region CH while being spaced apart from the semiconductor substrate SU. The gate electrode GA may include at least one from among: metals, metal nitrides, metal carbides, and polysilicon. The metal may include, for example, at least one from the following: aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta). The metal nitride may include, for example, at least one from the following: titanium nitride films (TiN films) and tantalum nitride films (TaN films). The metal carbide may include, for example, one or more from among metal carbides doped with (or containing) aluminum and/or silicon. The metal carbide may include TiAlC, taAlC, tiSiC, or TaSiC, for example.

The gate electrode GA may have a structure in which a plurality of materials are stacked. The gate electrode GA may have, for example, a multilayer structure of a metal nitride layer/metal layer such as TiN/Al or the like, or may have a multilayer structure of a metal nitride layer/metal carbide layer/metal layer such as TiN/TiAlC/W. The foregoing materials used in the gate electrode GA are only examples, and the gate electrode GA is not limited thereto.

A gate insulating layer GI may be further provided between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may include a cis (dielectric) material or a high-k dielectric material. The gate insulating layer GI may have a dielectric constant of, for example, about 20 to about 70.

The gate insulating layer GI may include, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or the like, or may include a 2D insulator such as hexagonal boron nitride (h-BN). The gate insulating layer GI may include, for example, silicon oxide (SiO ₂ ) Silicon nitride (SiN) _x ) Etc., or may include hafnium oxide (HfO ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Lanthanum oxide (La) ₂ O ₃ ) Lanthanum aluminum oxide (LaAlO) ₃ ) Zirconium oxide (ZrO) ₂ ) Hafnium zirconium oxide (HfZrO ₂ ) Zirconia silica (ZrSiO) ₄ ) Tantalum oxide (Ta) ₂ O ₅ ) Titanium oxide (TiO) ₂ ) Strontium titanium oxide (SrTiO) ₃ ) Yttria (Y) ₂ O ₃ ) Alumina (Al) ₂ O ₃ ) Lead scandium tantalum oxide (PbSc) _0.5 Ta _0.5 O ₃ ) Lead zinc niobate (PbZnNbO) ₃ ) Etc. For example, the gate insulating layer GI may include a metal oxynitride such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium Oxynitride (YON), or the like; silicates such as ZrSiON, hfSiON, YSiON, laSiON and the like; or aluminates, e.g. ZrAlON, hfAlON, etc. The gate insulating layer GI may include, for example, a dielectric layer of the above-described capacitor. The gate insulating layer GI may constitute a gate stack together with the gate electrode GA.

One of the electrodes 201, 401 of the capacitor CA1 and one of the source region SR and the drain region DR of the transistor TR may be electrically connected through the contact 120. The contacts 120 may comprise any suitable conductive material, such as tungsten, copper, aluminum, polysilicon, and the like.

The arrangement of the capacitor CA1 and the transistor TR can be variously modified. For example, the arrangement may be such that the capacitor CA1 is provided on the semiconductor substrate SU or embedded in the semiconductor substrate SU.

Although in fig. 10, the electronic device 1001 is illustrated as including one capacitor CA1 and one transistor TR, this is merely an example, and the electronic device 1001 may include a plurality of capacitors and a plurality of transistors.

Fig. 11 shows an electronic device according to another embodiment.

Referring to fig. 11, an electronic device 1002 may include a structure in which a capacitor CA2 and a transistor TR are electrically connected via a contact 21.

The transistor TR may include a semiconductor substrate SU provided with an active region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU facing the channel region CH and having a gate insulating layer GI and a gate electrode GA.

An interlayer (interlayer) insulating film 25 may be provided on the semiconductor substrate SU to cover the gate stack GS. The interlayer insulating film 25 may include an insulating material. The interlayer insulating film 25 may include, for example, si oxide (e.g., siO ₂ ) Al oxide (e.g. Al ₂ O ₃ ) Or a high-k dielectric material (e.g., hfO ₂ ). The contact 21 may pass through the interlayer insulating film 25 and electrically connect the transistor TR and the capacitor CA1 to each other.

Capacitor CA1 may include lower electrode 202, upper electrode 402, and dielectric film 302 disposed between lower electrode 202 and upper electrode 402. The lower electrode 110 and the upper electrode 402 may be proposed to have a shape that maximizes the contact surface with the dielectric film 302, and the material of the capacitor CA2 may be substantially the same as any of the capacitors described in fig. 1 and 8A-8G.

Fig. 12 is a plan view of an electronic device according to another embodiment.

As shown in fig. 12, the electronic device 1003 may include a structure in which a plurality of capacitors and a plurality of field effect transistors are repeatedly arranged. The electronic device 1003 may include: a semiconductor substrate 11' including a source, a drain, and a channel, a field effect transistor including a gate stack 12', a contact structure 20' disposed on the semiconductor substrate 11' so as not to overlap the gate stack 12', and a capacitor CA3 disposed on the contact structure 20', and may further include a bit line structure 13' electrically connecting the plurality of field effect transistors. The material of capacitor CA3 may be substantially the same as any of the capacitors described in FIGS. 1 and 8A-8G.

Fig. 12 illustrates the following arrangement as an example: wherein the contact structure 20' and the capacitor CA3 are repeatedly arranged along the X-direction and the Y-direction, but the arrangement is not limited thereto. The contact structures 20' may be arranged, for example, in the X-direction and the Y-direction, and the capacitors CA3 may be arranged in a hexagonal shape, for example, a honeycomb structure. Alternatively, the capacitor CA3 may have, for example, a circular shape, a triangular shape, a quadrangular shape, a pentagonal shape, or the like. The capacitor CA3 may have, for example, a circular pillar shape, a triangular pillar shape, a quadrangular pillar shape, a pentagonal pillar shape, or the like. The quadrangular prism shape may have, for example, a square prism shape, a rectangular prism shape (sheet shape), or the like.

Fig. 13 is a cross-sectional view taken along A-A' in fig. 12.

Referring to fig. 13, the semiconductor substrate 11' may have a Shallow Trench Isolation (STI) structure including a device separator 14. The device separator 14 may be a single layer composed of one type of insulating film, or a plurality of layers composed of a combination of two or more types of insulating films. The device separator 14 may include a device separation trench 14T within the semiconductor substrate 11', and the device separation trench 14T may be filled with an insulating material. The insulating material may include, but is not limited to, at least one from the following: FSG (fluorosilicate glass), USG (undoped silicate glass), BPSG (boron-phosphorus-silicate glass), PSG (phosphorus-silicate glass), FOX (flowable oxide), PE-TEOS (plasma enhanced tetraethyl orthosilicate), and TOSZ (tonen silazene).

The semiconductor substrate 11 'may further include a channel region CH defined by the device separator 14 and a gate line trench 12T disposed parallel to an upper surface of the semiconductor substrate 11' and extending along the X direction. The channel region CH may have an elongated island shape having a short axis and a long axis. The long axis of the channel region CH may be arranged along a direction D3 parallel to the upper surface of the semiconductor substrate 11', as shown in fig. 12 as an example.

The gate line trench 12T may be disposed to intersect the channel region CH to a desired and/or alternatively predetermined depth from the upper surface of the semiconductor substrate 11', or may be disposed within the channel region CH. The gate line trench 12T may be disposed in the device separation trench 14T, and the gate line trench 12T within the device separation trench 14T may have a bottom surface of the gate line trench 12T lower than the channel region CH. The first source/drain 11' ab and the second source/drain 11"ab may be disposed on upper portions of the channel region CH located at both sides of the gate line trench 12T.

The gate stack 12' may be disposed within the gate line trench 12T. In particular, the gate insulating layer 12a, the gate electrode 12b, and the gate capping layer 12c may be sequentially disposed within the gate line trench 12T. The gate insulating layer 12a and the gate electrode 12b are described above, and the gate capping layer 12c may include at least one from among: silicon oxide, silicon oxynitride, and silicon nitride. A gate capping layer 12c may be disposed on the gate electrode GA to fill the remaining region of the gate line trench 12T.

The bit line structure 13 'may be disposed on the first source/drain 11' ab. The bit line structure 13 'may be arranged parallel to the upper surface of the semiconductor substrate 11' and extend in the Y direction. The bit line structure 13 'may be electrically connected to the first source/drain 11' ab, and may include a bit line contact 13a, a bit line 13b, and a bit line capping layer 13c sequentially on the substrate. The bit line contacts 13a may comprise polysilicon, for example. The bit line 13b may include, for example, a metal material. The bit line capping layer 13c may include an insulating material such as silicon nitride or silicon oxynitride.

Although in fig. 13, the bit line contacts 13a are illustrated as having bottom surfaces at the same level as the upper surface of the semiconductor substrate 11', this is by way of example only and not limitation. For example, in further embodiments, a recess formed to a desired and/or alternatively predetermined depth from the upper surface of the semiconductor substrate 11 'may be further provided, and the bit line contact 13a may extend into the recess such that the bottom surface of the bit line contact 13a may be formed at a lower level than the upper surface of the semiconductor substrate 11'.

The bit line structure 13' may further include a bit line interlayer (not shown) between the bit line contacts 13a and the bit lines 13 b. The bit line interlayer may comprise, for example, a metal silicide such as tungsten silicide, or a metal nitride such as tungsten nitride. Bit line spacers (not shown) may be further formed on sidewalls of the bit line structures 13'. The bit line spacer may have a single-layer structure or a multi-layer structure. The bit line spacers may comprise, for example, an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The bit line spacers may further include, for example, air spaces (not shown).

The contact structure 20' may be disposed on the second source/drain 11 "ab. The contact structures 20 'and bit line structures 13' may be arranged on different sources/drains on the substrate. The contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source/drain 11 "ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the side surfaces and the bottom surface of the upper contact pattern. The lower contact pattern may comprise polysilicon, for example. The upper contact pattern may comprise, for example, a metallic material. The barrier layer may comprise, for example, a metal nitride having conductivity.

The capacitor CA3 may be disposed on the semiconductor substrate 11 'electrically connected to the contact structure 20'. In particular, the capacitor CA3 may include a lower electrode 203 electrically connected to the contact structure 20', an upper electrode 403 spaced apart from the lower electrode 203, and a dielectric film 303 disposed between the lower electrode 203 and the upper electrode 403. The lower electrode 203 may have a cylindrical shape or a cup shape having an inner space with a closed bottom. The upper electrode 403 may have a shape of a comb having teeth extending into the inner space formed by the lower electrodes 203 and in the region between adjacent lower electrodes 203. A dielectric film 303 may be disposed between the lower electrode 203 and the upper electrode 403 to be parallel to the surface thereof.

The materials constituting the lower electrode 203, the dielectric thin film 303, and the upper electrode 403 of the capacitor CA3 may be substantially the same as those of any one of the capacitors described in fig. 1 and 8A to 8G and thus are not further described.

An interlayer insulating layer 15 may be further provided between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating layer 15 may be disposed in a space between the capacitor CA3 and the semiconductor substrate 11' in which other structures are not disposed. In particular, the interlayer insulating layer 15 may be provided to cover wiring and/or electrode structures such as bit line structures 13', contact structures 20', and gate stacks 12' on the substrate. For example, the interlayer insulating layer 15 may surround the walls of the contact structure 20'. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contacts 13a and a second interlayer insulating layer 15b covering side and/or top surfaces of the bit lines 13b and the bit line capping layer 13 c.

The lower electrode 203 of the capacitor CA3 may be disposed on the interlayer insulating layer 15, particularly on the second interlayer insulating layer 15b. When the plurality of capacitors CA3 are provided, bottom surfaces of the plurality of lower electrodes 203 may be separated by the etch stop layer 16. In other words, the etch stop layer 16 may include the opening 16T, and the bottom surface of the lower electrode 203 of the capacitor CA3 may be disposed in the opening 16T. As illustrated, the lower electrode 203 may have a cylindrical shape or a cup shape having an inner space with a closed bottom. The capacitor CA3 may further include a supporting portion (not shown) preventing the lower electrode 203 from tilting or collapsing, and the supporting portion may be provided on a sidewall of the lower electrode 203.

Fig. 14 is a cross-sectional view of an electronic device according to another embodiment.

The electronic device 1004 according to the present embodiment is illustrated as a cross-sectional view corresponding to the A-A' cross-sectional view in fig. 12, and differs from fig. 13 only in the shape of the capacitor CA 4. The capacitor CA4 may be electrically connected to the contact structure 20' and disposed on the semiconductor substrate 11', and may include a lower electrode 204 electrically connected to the contact structure 20', an upper electrode 404 spaced apart from the lower electrode 204, and a dielectric film 304 disposed between the lower electrode 204 and the upper electrode 404. The materials of the lower electrode 204, the dielectric film 304, and the upper electrode 404 may be substantially the same as those of any of the capacitors described above in fig. 1 and 8A-8G.

The lower electrode 204 may have a column shape extending in a vertical direction (Z direction) such as a cylinder, a quadrangular column, or a polygonal column. The upper electrode 404 may have the shape of a comb with teeth extending into the area between adjacent lower electrodes 204. A dielectric film 304 may be disposed between the lower electrode 204 and the upper electrode 404 to be parallel to the surface thereof.

The capacitor and the electronic device according to the above-described embodiments can be applied to various application fields. For example, the electronic device according to the embodiment may be used as a logic device or a memory device. The electronic device according to the embodiment may be used in devices such as mobile devices, computers, laptops, sensors, network devices, neuromorphic devices, etc. for arithmetic operations, program execution, temporary data retention, etc. Further, the electronic component and the electronic device according to the embodiment may be useful for an apparatus in which the data transmission amount is large and the data transmission is continuously performed.

Fig. 15 and 16 are schematic diagrams schematically showing a device architecture applicable to a device according to an embodiment.

Referring to fig. 15, an electronics architecture 1100 may include a memory unit 1010, an Arithmetic Logic Unit (ALU) 1020, and a control unit 1030. The memory unit 1010, ALU 1020, and control unit 1030 may be electrically connected. The electronic device architecture 1100 may be implemented, for example, as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030.

The memory unit 1010, ALU 1020, and control unit 1030 may be connected to each other by on-chip wires and communicate directly. The memory unit 1010, ALU 1020, and control unit 1030 may be integrally formed on a single substrate to form a single chip. The input/output device 2000 may be connected to an electronic device architecture (chip) 1100. The storage unit 1010 may include both main memory and cache (cache) memory. Such an electronic device architecture (chip) 1000 may be an on-chip memory processing unit. The memory cell 1010 may include the aforementioned capacitor and an electronic device using the same. ALU 1020 or control unit 1030 may also each include the aforementioned capacitors.

Referring to FIG. 16, cache memory 1510, ALU 1520, and control unit 1530 may configure a Central Processing Unit (CPU) 1500, and cache memory 1510 may include Static Random Access Memory (SRAM). In addition to the CPU 1500, a main memory 1600 and a secondary memory 1700 may be provided. Main memory 1600 may be a Dynamic Random Access Memory (DRAM) and may include the capacitors described above. The electronic device architecture may be implemented in a form in which the compute unit device and the memory unit device are adjacent to each other on a single chip without distinguishing the sub-units.

Although one or more embodiments have been described with reference to the accompanying drawings and examples, these embodiments are merely examples and those skilled in the art will appreciate that many modifications are possible therefrom.

The above-described capacitor and electronic device including the same are described with reference to the embodiments illustrated in the drawings, but these are merely examples, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the embodiments disclosed herein should be considered in descriptive sense only and not for purposes of limitation. The full scope of the inventive concept should be defined by the appended claims and should be construed to include all modifications that are equivalent thereto.

A method of manufacturing a capacitor according to another embodiment may include: providing a first thin film electrode layer or a second thin film electrode layer; disposing a dielectric layer on one side of the first or second thin film electrode layer by epitaxial growth; and disposing another thin film electrode layer on the dielectric layer to thereby provide the capacitor, wherein the capacitor may include a first thin film electrode layer; a second thin film electrode layer; and a dielectric layer disposed between the first thin film electrode layer and the second thin film electrode layer, wherein the first thin film electrode layer and the second thin film electrode layer have a conductive perovskite-type crystal structure, the dielectric layer may include a metal oxide having a dielectric perovskite-type crystal structure, wherein the metal oxide may include a first element disposed in a cubo-octahedral site, a second element disposed in an octahedral site, and a third element disposed in an octahedral site, a valence of the third element may be lower than a valence of the second element, and the third element may be a dopant. The capacitor manufactured by the above-described method can suppress a decrease in permittivity of the capacitor due to a decrease in volume and reduce leakage current.

In the method of manufacturing a capacitor, the epitaxial growth may be performed at a temperature of 600 ℃ or less, 550 ℃ or less, or 500 ℃ or less. For example, the epitaxial growth may be performed at a temperature of about 400 ℃ to about 600 ℃, about 450 ℃ to about 550 ℃, about 470 ℃ to about 530 ℃, or about 480 ℃ to about 520 ℃. Since the epitaxial growth is performed at a relatively low temperature as above, the production efficiency of the dielectric layer can be significantly improved. Thus, improvement in manufacturing efficiency and reduction in manufacturing cost of devices and capacitors including the dielectric layer can be achieved.

The method of manufacturing a capacitor may further include disposing an intermediate layer on one side of the first or second thin film electrode layer by epitaxial growth before disposing a dielectric layer on one side of the first or second thin film electrode layer by epitaxial growth. Since the capacitor includes the intermediate layer, further reduction of leakage current of the capacitor can be achieved.

Referring to fig. 8A to 8G, the first thin film electrode layer 11 or the second thin film electrode layer 13 may be provided first.

The first and second thin film electrodes 11 and 13 may include, for example, metal oxides selected from the group consisting of: strontium ruthenium oxide (SrRuO) ₃ ) Iridium ruthenium oxide (IrRuO) ₃ ) Calcium ruthenium oxide (CaRuO) ₃ ) Calcium nickel oxide (CaNiO) ₃ ) Barium ruthenium oxide (BaRuO) ₃ ) And oxidationBarium strontium ruthenium ((Ba, sr) RuO ₃ ). The first and second thin film electrodes 11 and 13 may be metal oxides having a perovskite-type crystal structure. The first thin film electrode 11 and/or the second thin film electrode 13 may be strontium ruthenium oxide (SrRuO) ₃ )。

The first thin film electrode 11 and/or the second thin film electrode 13 may be formed by deposition of a metal, a metal oxide, a metal nitride, a metal oxynitride, or an alloy through a process such as an electron beam epitaxy process, a liquid phase epitaxy process, a vapor phase epitaxy process, a chemical vapor deposition process, a sputtering process, an atomic layer deposition process, a pulsed laser deposition process, or the like. The first thin film electrode 11 and/or the second thin film electrode 13 may have a single-layer structure or a multi-layer structure.

In the case where the first thin film electrode 11 is formed by a pulsed laser deposition process, for example, surface-treated SrTiO may be used ₃ The (STO) insulating substrate 100 is loaded into the reaction chamber and the insulating substrate 100 may be maintained at a temperature of about 400 ℃ to about 800 ℃ and the partial pressure of the oxidant inside the chamber, e.g., the partial pressure of oxygen, may be maintained at about 0.01 millibar to about 1 millibar. The gaseous metal and/or gaseous metal ions used to form the first thin film electrode 11 may be supplied by vaporizing the metal and/or metal ions from a metal precursor. Subsequently, the gaseous metal and/or gaseous metal ions may be implanted onto the insulating substrate 100, and an oxidizing agent may be supplied to thereby form the first thin film electrode 11 on the insulating substrate 100. In which the first thin film electrode 11 includes SrRuO ₃ In the case of a layer, the metal precursor may consist of strontium or a first precursor compound containing strontium, and ruthenium or a second precursor compound containing ruthenium, wherein the oxidizing agent may comprise oxygen (O ₂ ) Ozone (O) ₃ ) Nitrogen dioxide (NO) ₂ ) Dinitrogen monoxide (N) ₂ O), and the like. The oxidant may be, for example, oxygen. In the same manner, the second thin film electrode 13 may be formed instead of the first thin film electrode 11.

Next, the dielectric layer 12 may be provided on one side of the first thin film electrode layer 11 or the second thin film electrode layer 13 by epitaxial growth. The epitaxial growth may use, for example, a molecular beam epitaxy process, a pulsed laser epitaxy process, a liquid phase epitaxy process, a vapor phase epitaxy process, or the like.

The dielectric layer 12 may be selected from, for example, doped barium strontium ruthenium oxide ((Ba, sr) RuO ₃ ) Doped strontium titanium oxide (SrTiO) ₃ ) Doped lithium niobium oxide (LiNbO) ₃ ) Doped potassium niobium oxide (KNbO) ₃ ) Doped tantalum potassium oxide (KTaO) ₃ ) Doped barium titanium oxide (BaTiO) ₃ ) Doped calcium titanium oxide (CaTiO) ₃ ) Doped lead titanium oxide (PbTiO) ₃ ) Doped sodium niobium oxide (NaNbO) ₃ ) Doped sodium tantalum oxide (NaTaO) ₃ ) Doped calcium zirconium oxide (CaZrO ₃ ) Doped barium zirconium oxide (BaZrO) ₃ ) Doped strontium zirconium oxide (SrZrO ₃ ) Among them, the dopant used for doping in the foregoing oxide may include yttrium (Y), nickel (Ni), manganese (Mn), etc. as a third element.

In the case where the dielectric layer 12 is formed by a pulsed laser deposition epitaxial process, for example, the insulating substrate 100/first thin film electrode 11 stack prepared by the above method may be loaded into a reaction chamber, and the first thin film electrode 11 may be maintained at a temperature of about 400 ℃ to about 800 ℃, and the partial pressure of an oxidizing agent inside the chamber, for example, oxygen partial pressure, may be maintained at about 0.01 mbar to about 1 mbar. By vaporizing metal and/or metal ions from the metal precursor, gaseous metal and/or gaseous metal ions forming dielectric layer 12 may be supplied. Subsequently, the gaseous metal and/or metal ions may be introduced onto the first thin film electrode 11, and then an oxidizing agent may be supplied to thereby form the dielectric layer 12. When the dielectric layer 12 comprises yttrium (Y) -doped barium strontium ruthenium oxide ((Ba, sr) RuO) ₃ ) When the metal precursor may be formed from barium or a first precursor compound comprising barium, strontium or a second precursor compound comprising strontium, ruthenium or a third precursor compound comprising ruthenium, and yttrium or a dopant compound comprising yttrium, wherein the oxidizing agent may comprise oxygen (O ₂ ) Ozone (O) ₃ ) Nitrogen dioxide (NO) ₂ ) Or nitrous oxide (N) ₂ O), and the like. The oxidant may be, for example, oxygen.

In the case where the dielectric layer 12 is formed by a molecular beam epitaxy process, it may be fabricated by the above methodThe prepared insulating substrate 100/first membrane electrode 11 stack is loaded into a reaction chamber and the first membrane electrode 11 may be maintained at a temperature of about 400 ℃ to about 800 ℃ and the partial pressure of an oxidant inside the chamber, such as oxygen, may be maintained at about 10% ^-8 Tray to about 10 ^-5 And (5) a bracket. By vaporizing metal from a metal precursor, gaseous metal constituting the dielectric layer may be supplied. Next, after the gaseous metal is introduced onto the first thin film electrode 11, a dielectric layer 12 may be formed on the first thin film electrode 11 by supplying an oxidizing agent. When the dielectric layer 12 comprises yttrium (Y) -doped barium strontium ruthenium oxide ((Ba, sr) RuO) ₃ ) When the metal precursor may be formed from barium or a first precursor compound comprising barium, strontium or a second precursor compound comprising strontium, ruthenium or a third precursor compound comprising ruthenium, and yttrium or a dopant compound comprising yttrium, wherein the oxidizing agent may comprise oxygen (O ₂ ) Ozone (O) ₃ ) Nitrogen dioxide (NO) ₂ ) Or nitrous oxide (N) ₂ O), and the like. The oxidant may be, for example, oxygen.

In the case where the dielectric layer 12 is formed by a chemical vapor deposition process, the insulating substrate 100/first thin film electrode 11 stack prepared by the above method may be loaded into a reaction chamber, and the first thin film electrode 11 may be maintained at a temperature of about 500 to about 600 ℃, and a partial pressure of an oxidizing agent inside the chamber, for example, an oxygen partial pressure, may be maintained at about 1 to about 10 torr. Next, after the organometallic precursor is introduced onto the first thin film electrode 11, a dielectric layer 12 may be formed on the first thin film electrode 11 by supplying an oxidizing agent. When the dielectric layer 12 comprises yttrium (Y) -doped barium strontium ruthenium oxide ((Ba, sr) RuO) ₃ ) When the organometallic precursor may be formed from barium or a first precursor compound containing barium, strontium or a second precursor compound containing strontium, ruthenium or a third precursor compound containing ruthenium, and yttrium or a dopant compound containing yttrium, wherein the oxidant may comprise oxygen (O ₂ ) Ozone (O) ₃ ) Nitrogen dioxide (NO) ₂ ) Or nitrous oxide (N) ₂ O), and the like. The oxidant may be, for example, oxygen.

In the case where the dielectric layer 12 is formed by an atomic layer deposition process In case, the insulating substrate 100/first thin film electrode 11 stack prepared by the above method may be loaded into a reaction chamber, and the first thin film electrode 11 may be maintained at a temperature of about 200 ℃ to about 400 ℃, and the concentration of an oxidizing agent inside the chamber, for example, ozone concentration, may be maintained at about 100g/m ³ -about 500g/m ³ . By vaporizing metal and/or metal ions from the metal precursor, gaseous metal and/or gaseous metal ions forming dielectric layer 12 may be supplied. Subsequently, the gaseous metal and/or metal ions may be introduced onto the first thin film electrode 11 and then an oxidizing agent may be supplied to thereby form the dielectric layer 12. When the dielectric layer 12 comprises yttrium (Y) -doped barium strontium ruthenium oxide ((Ba, sr) RuO) ₃ ) When the metal precursor may be formed from barium or a first precursor compound comprising barium, strontium or a second precursor compound comprising strontium, ruthenium or a third precursor compound comprising ruthenium, and yttrium or a dopant compound comprising yttrium, wherein the oxidizing agent may comprise oxygen (O ₂ ) Ozone (O) ₃ ) Nitrogen dioxide (NO) ₂ ) Or nitrous oxide (N) ₂ O), and the like. The oxidizing agent may be, for example, ozone.

Further crystallization of the material constituting the dielectric layer 12 may be possible by subjecting the dielectric layer 12 to an additional heat treatment process. For example, the dielectric layer 12 may be heat treated by: in oxygen (O) ₂ ) Gas, nitrogen (N) ₂ ) Gas, argon (Ar) gas, ammonia (NH) ₃ ) Rapid Thermal Processing (RTP) under an atmosphere of a gas, or a mixture thereof. The RTP may be performed, for example, at a temperature of about 500 ℃ to about 650 ℃ for about 30 seconds to about 3 minutes.

Next, another thin film electrode layer may be disposed on the dielectric layer 12 to provide the capacitor 20. The method of disposing the other thin film electrode layer may be the same method of disposing the first thin film electrode 11 or the second thin film electrode 12 as above.

The following examples and comparative examples are provided to describe the embodiments in more detail. However, it will be appreciated that the examples are provided merely for the purpose of illustrating the embodiments and should not be construed as limiting the scope of the embodiments.

(preparation of capacitor)

Example 1: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y1 atomic%

By deposition on SrTiO using pulsed laser ₃ Growth of SrRuO on (STO) substrate ₃ The thin film forms a first thin film electrode. The thickness of the first film electrode is

The pulse laser deposition process is 1×10 ^-2 Tong-1×10 ^-1 The partial pressure of oxygen was carried out at a temperature of 700 ℃.

According to the same process, a dielectric layer is formed by growing a Y-doped Barium Strontium Titanate (BST) film doped with 1 atomic% yttrium (Y) as a dopant on the first thin film electrode. The thickness of the dielectric layer is

The composition of the Y-doped BST is Ba _1-a Sr _a Ti _0.99 Y _0.01 O ₃ (a=0.5). Ti is a tetravalent element and Y is a trivalent element. In other words, ti is a tetravalent cation and Y is a trivalent cation. Ti (Ti) ⁴⁺ Is 0.061nm and Y ³⁺ The ionic radius of (2) is 0.089nm.

According to the same process, a dielectric layer is arranged on the substrate and is provided withSrRuO of the thickness of (a) ₃ To thereby prepare a capacitor.

The first thin film electrode layer, the second thin film electrode layer, and the dielectric layer may each have a perovskite crystal structure.

Fig. 1 is a cross section of a capacitor thus prepared. As shown in fig. 1, it can be confirmed that a Y-doped BST epitaxial layer is formed.

Implementation of the embodimentsExample 2: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y1 atomic%

A capacitor was prepared by the same process as in example 1, except that: changing the thickness of the dielectric layer to

Example 3: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y1 atomic%

Example 4: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y2 at%

A capacitor was prepared by the same process as in example 1, except that: the dopant content was changed to 2 atomic%.

Example 5: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y2 at%

A capacitor was prepared by the same process as in example 1, except that: changing the dopant content to 2 atomic% and changing the thickness of the dielectric layer to

Example 6: srRuO ₃ Y-doped BST/SrRuO ₃ Thickness of (thickness of)BST doped with Y2 at%

A capacitor was prepared by the same process as in example 1, except that: changing the dopant content to 2 atomic% and changing the thickness of the dielectric layer toComparative example 1: srRuO ₃ /BST/SrRuO ₃ Thickness->BST (dopant 0 atom%)

A capacitor was prepared by the same process as in example 1, except that: doping with dopant (dopant 0 at%) was not performed.

Comparative example 2: srRuO ₃ /BST/SrRuO ₃ Thickness of (thickness of)BST (dopant 0 atom%)

A capacitor was prepared by the same process as in example 1, except that: without doping with dopants and changing the thickness of the dielectric layer toComparative example 3: srRuO ₃ /BST/SrRuO ₃ Thickness->BST (dopant 0 atom%)

A capacitor was prepared by the same process as in example 1, except that: without doping with dopants and changing the thickness of the dielectric layer to Evaluation example 1: permittivity measurement

The relative permittivity at room temperature (25 ℃) of the capacitors prepared in examples 1 to 6 and comparative examples 1 to 3 was measured at 1kHz to 1MHz, and the measurement results are shown in FIG. 2.

As shown in fig. 2, the thickness of the dielectric layer was varied from that of the capacitors of comparative examples 1 to 3Is reduced toThe permittivity of the dielectric layer decreases drastically from 900 or more to 100 or less.

Meanwhile, in the capacitors of examples 1 to 3, the thickness of the dielectric layer was varied fromReduced to-> The permittivity of the dielectric layer gradually decreases from 700 to 400 or more.

The capacitors of examples 4 to 6 also showed smaller decrease in permittivity than the capacitors of comparative examples 1 to 3.

Thus, it was confirmed that Y doping of the dielectric layers in the capacitors of examples 1 to 6 resulted in significant suppression of the decrease in permittivity due to the reduced thickness of the dielectric layers.

Evaluation example 2: leakage current measurement

The leakage current of the capacitors prepared in examples 1 to 6 and comparative examples 1 to 3 was measured.

Leakage current refers to the current density when a voltage of 1V is applied to the capacitor. The measurement results are shown in fig. 3 and table 1 below.

TABLE 1

As shown in fig. 3 and table 1, the leakage current of the Y-doped capacitor of example 4 was reduced to 10 ^-6 A/cm ² Horizontal.

The Y-doped capacitor of example 6 shows a four order of magnitude reduction in leakage current.

It was thus demonstrated that the inclusion of a dopant doped dielectric layer results in a significant reduction of the leakage current of the capacitor. Evaluation example 3: XRD measurement of dielectric layers prepared at 700 DEG C

The dielectric layer was prepared by: by pulsed laser deposition on SrTiO ₃ Growth on (STO) substrate withAn undoped BST dielectric layer and doped with 2 atomic% Y (yttrium) as dopant and havingY-doped Barium Strontium Titanate (BST). The pulse laser deposition process is 1×10 ^-2 Tong-1×10 ^-1 The partial pressure of oxygen was carried out at a temperature of 700 ℃. The STO substrate has a lattice constant of the a-axis and the b-axis of +.>

XRD patterns were obtained for the surfaces of the stack of STO substrate/undoped BST dielectric layer and the stack of STO substrate/Y-doped BST dielectric layer, and the results thereof are shown in fig. 4 and 5.

Fig. 4 shows XRD patterns obtained from theta and 2 theta axis scans (sample and detector scans).

Fig. 5 shows a rocking curve, which is an XRD spectrum obtained from a theta axis scan (sample scan or sample rocking).

As shown in fig. 4, the peak position has been shifted to a lower angle in the Y-doped BST dielectric layer than in the undoped BST dielectric layer. The c-axis of the undoped BST (e.g.,

Direction) lattice constant ofThe c-axis of the Y-doped BST (e.g., [001]Direction) lattice constant ofThus, it was demonstrated that the c-axis lattice constant of the Y-doped BST was increased compared to the c-axis lattice constant of the undoped BST.

It is considered that such an increase in the c-axis lattice constant is caused by doping with Y having an ion radius larger than that of Ti, and compressive strain is applied to the octahedral sites, resulting in an increase in lattice spacing along the c-axis. The c-axis lattice constant in the Y-doped BST is higher than the c-axis lattice constant in the BST, indicating that polarization is more readily inducible in the Y-doped BST.

As shown in fig. 5, in the Y-doped BST, the half width (FWHM) of the peak at the (200) plane at the diffraction angle of θ=22.5° ±0.5° is 0.03 °, indicating very high crystallinity. It was thus confirmed that the Y-doped BST dielectric layer was an epitaxial layer obtained by epitaxial growth and had a high crystallinity of single crystal or equivalent thereto.

Evaluation example 4: XRD measurement of dielectric layers prepared at 500 DEG C

A stack of a STO substrate/undoped BST dielectric layer and a stack of a STO substrate/Y-doped BST dielectric layer were prepared following the same procedure as in evaluation example 3, except for the following: the substrate temperature was changed to 500 ℃.

XRD patterns were obtained for the surfaces of the stack of STO substrate/undoped BST dielectric layer and the stack of STO substrate/Y-doped BST dielectric layer, and the results are shown in fig. 6.

Fig. 6 shows XRD patterns obtained from theta and 2 theta axis scans (sample and detector scans).

As shown in fig. 6, the peak position in the undoped BST dielectric layer was shifted to a higher angle and the peak intensity was also reduced as compared to the results of evaluation example 3.

The c-axis of the undoped BST (e.g., [001]Direction) Lattice constantThe c-axis lattice constant of the Y-doped BST is +.>

In the undoped BST, it is considered that the epitaxial structure is not maintained and crystallinity is deteriorated during the strain relief process at 500 ℃, and the c-axis lattice constant is also lowered due to the deterioration of crystallinity. Meanwhile, in the Y-doped BST, it is considered that a high epitaxial structure and crystallinity are maintained even at 500 ℃, resulting in an increase in c-axis lattice constant. That is, it was confirmed that the Y-doped BST dielectric layer prepared at 500 ℃ was an epitaxial layer obtained by epitaxial growth, and had a high crystallinity of single crystal or equivalent thereto.

Although not shown in the drawings, on the rocking curve of the Y-doped BST, the FWHM of the peak with respect to the (200) plane was 0.05 °, indicating that the crystallinity was still high.

Evaluation example 5: XRD measurement of dielectric layers prepared at 300℃

A stack of a STO substrate/undoped BST dielectric layer and a stack of a STO substrate/Y-doped BST dielectric layer were prepared following the same procedure as in evaluation example 3, except for the following: the substrate temperature was changed to 300 ℃.

XRD spectra were obtained for the surface of the stack of STO substrate/undoped BST dielectric layer and the stack of STO substrate/Y-doped BST dielectric layer, and the results are shown in fig. 7.

Fig. 7 shows XRD patterns obtained from theta and 2 theta axis scans (sample and detector scans).

As shown in fig. 7, only the peak of the STO substrate occurs, and there is no peak of the undoped BST dielectric layer or the Y-doped BST dielectric layer.

It was thus demonstrated that an amorphous or partially crystallized undoped BST dielectric layer, and an amorphous or partially crystallized Y-doped BST dielectric layer, were formed at 300 ℃.

Evaluation example 6: calculation of Schottky Barrier Height (SBH) and intermediate layer

With SrRuO ₃ (electrode)/SrTiO ₃ Compared with the stacked body of (dielectric material), the method is calculated in SrRuO ₃ /SrTiO ₃ A change (Δv) in Schottky Barrier Height (SBH) of the stack with the intermediate layer provided therebetween, and a portion of the result thereof is shown in table 2.

The intermediate layer is arranged on SrRuO ₃ /SrTiO ₃ Between them. The intermediate layer is provided with ABO ₃ A perovskite compound.

Permittivity and band gap were calculated within the framework of Density Functional Theory (DFT) using the vienna de novo modeling package (Vienna ab initio simulation package) (VASP).

The SBH of the stack in which the intermediate layer is provided can be expressed by equation 1.

Equation 1

SBH＝Φ-χ+ΔV

In equation 1, Φ represents the work function of the electrode, χ represents the electron affinity of the dielectric material, and Δv represents the SBH change.

[ Table 2 ]

Intermediate layer	SBH variation [ eV]
		-	-
ScGaO ₃	0.60
		LaAlO ₃	0.50

As shown in table 2, placing the intermediate layer between the electrode and the dielectric layer resulted in an increase in SBH of the stack.

The results demonstrate that the intermediate layer disposed between the electrode and the dielectric layer is suitable as a leakage current blocking layer for capacitors.

According to one aspect, by including the dielectric layer and the electrode having the novel structure, a decrease in permittivity of the capacitor due to a decrease in thickness of the dielectric material can be suppressed, and leakage current of the capacitor can be controlled.

One or more of the elements disclosed above may include or be implemented as follows: processing circuitry, for example, hardware including logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry may include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

It should be understood that the embodiments described herein should be considered in descriptive sense only and not for purposes of limitation. The descriptions of features or aspects in various embodiments should typically be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A capacitor, comprising:

a first thin film electrode layer;

a second thin film electrode layer; and

a dielectric layer between the first thin film electrode layer and the second thin film electrode layer,

wherein the first thin film electrode layer and the second thin film electrode layer each have a conductive perovskite crystal structure,

the dielectric layer comprises a metal oxide having a dielectric perovskite crystal structure, and the dielectric layer is an epitaxial layer,

wherein the metal oxide includes a first element in a cuboctahedral site, a second element in an octahedral site, and a third element in an octahedral site,

Wherein the valence of the third element is lower than the valence of the second element, and

the third element is a dopant.

2. The capacitor according to claim 1, wherein a valence of the second element is 4 or more, and the third element has a valence of 3 or less.

3. The capacitor of claim 1, wherein the third element is at least one of: y, mg, ni, fe, mn, co, al, cr, bi, and Ga.

4. The capacitor of claim 1, wherein an ionic radius of the third element is greater than an ionic radius of the second element.

5. The capacitor of claim 1 wherein

The metal oxide is a ternary metal oxide, and

the lattice of the metal oxide has a compressive strain along the c-axis.

6. The capacitor of claim 5 wherein

In the crystal lattice of the metal oxide, a c-axis lattice constant is larger than at least one of an a-axis lattice constant and a b-axis lattice constant, and

the c-axis lattice constant is

7. The capacitor of claim 1 wherein

The content of the third element is 0.1 atomic% to 9 atomic% with respect to the sum of the second element and the third element.

8. The capacitor of claim 1, wherein the dielectric layer comprises a metal oxide represented by the following formula 1:

1 (1)

A1 _1-a D1 _a B1 _1-b C1 _b O _3-δ

Wherein in the formula 1,

0.ltoreq.a <1,0.001< b <0.09, and 0.ltoreq.delta.ltoreq.0.5,

a1 and D1 are each an element having a valence of 2,

b1 is an element having a valence of 4, and

c1 is an element having a valence of 1, an element having a valence of 2, or an element having a valence of 3.

9. The capacitor of claim 5 wherein C1 is at least one of: y, mg, ni, fe, mn, co, al, cr, bi, and Ga.

10. The capacitor of claim 1, wherein the dielectric layer comprises a metal oxide represented by the following formula 2:

2, 2

Ba _1-a Sr _a Ti _1-b C2 _b O _3-δ

Wherein, in the formula 2,

0< a <1,0.001< b <0.08, and 0.ltoreq.delta.ltoreq.0.5,

wherein C2 is at least one of: y, mg, ni, fe, mn, co, al, cr, bi, and Ga.

11. The capacitor of claim 1 wherein

On the XRD spectrum of the dielectric layer, a rocking curve is observed by theta scanning between the X-ray source and the sample surface,

the rocking curve has a first peak with respect to the (200) plane at a diffraction angle of θ=22.5°±0.5°, and

The first peak has a full width at half maximum (FWHM) of 0.1 ° or less.

12. The capacitor of claim 1 wherein

The dielectric layer is arranged onA second relative permittivity (εr 2) at thickness for said dielectric layer>The ratio (εr2/εr1) of the first relative permittivity (. Epsilon.r1) at thickness is 0.2 or more.

13. The capacitor of claim 1 wherein

The dielectric layer hasIs defined by the thickness of the substrate,

the dielectric layer has at least one of a planar structure, a trench structure, and a pillar structure, and

the dielectric layer has a single-layer film structure or a multi-layer film structure.

14. The capacitor of claim 1 wherein

The first thin film electrode layer, the second thin film electrode layer, or both the first thin film electrode layer and the second thin film electrode layer comprise a ternary metal oxide,

the ternary metal oxide includes the first element,

the first thin film electrode layer, the second thin film electrode layer, or both the first thin film electrode layer and the second thin film electrode layer independently include the followingAt least one of: srRuO ₃ 、SrVO ₃ 、SrNbO ₃ 、SrMnO ₃ 、SrCrO ₃ 、SrFeO ₃ 、SrCoO ₃ 、SrMoO ₃ 、SrIrO ₃ 、CaRuO ₃ 、CaNiO ₃ 、BaRuO ₃ And (Ba, sr) RuO ₃ 。

15. The capacitor of claim 1, further comprising:

an intermediate layer in which

The intermediate layer being between the first thin film electrode layer and the dielectric layer, between the second thin film electrode layer and the dielectric layer, or between the first thin film electrode layer and the dielectric layer and between the second thin film electrode layer and the dielectric layer,

wherein the intermediate layer has a crystal structure of the same type as at least one of the first thin film electrode layer, the second thin film electrode layer, and the dielectric layer,

wherein at least one of the first thin film electrode layer and the second thin film electrode layer and the dielectric layer are in contact with the intermediate layer,

wherein the composition of the intermediate layer is different from the composition of the first thin film electrode layer, the composition of the second thin film electrode layer, and the composition of the dielectric layer.

16. The capacitor of claim 15 wherein said intermediate layer has a perovskite-type crystal structure, and

the intermediate layer includes a metal oxide represented by formula 3, a metal oxide represented by formula 4, or a metal oxide represented by formula 5:

3

A2B2O _3-δ1

Wherein in the formula 3,

a2 is an element having a valence of 2,

b2 is an element having a valence of 1, an element having a valence of 2, or an element having a valence of 3,

1.5≤3-δ1≤3.0

4. The method is to

A3B3O _3-δ2

Wherein in the formula 4,

a3 is an element having a valence of 1,

b3 is an element having a valence of 4, and

1.5≤3-δ2≤3.0

5. The method is to

A4B4O _3-δ3

Wherein in the formula 5,

a4 is an element having a valence of 3,

b4 is an element having a valence of 3, and

2.5≤3-δ3≤3.0。

17. the capacitor of claim 15 wherein

The intermediate layer comprises a metal oxide selected from the group consisting of:

SrGaO _3-δ1 、CaGaO _3-δ1 、BaGaO _3-δ1 、MgGaO _3-δ1 、BeGaO _3-δ1 、

SrInO _3-δ1 、CaInO _3-δ1 、BaInO _3-δ1 、MgInO _3-δ1 、BeInO _3-δ1 、

SrBeO _3-δ1 、CaBeO _3-δ1 、BaBeO _3-δ1 、MgBeO _3-δ1 、

SrMgO _3-δ1 、CaMgO _3-δ1 、BaMgO _3-δ1 、BeMgO _3-δ1 、

SrBaO _3-δ1 、CaBaO _3-δ1 、MgBaO _3-δ1 、BeBaO _3-δ1 、

SrCaO _3-δ1 、BaCaO _3-δ1 、MgCaO _3-δ1 、BeCaO _3-δ1 、

SrLiO _3-δ1 、CaLiO _3-δ1 、BaLiO _3-δ1 、MgLiO _3-δ1 、BeLiO _3-δ1 、

SrNaO _3-δ1 、CaNaO _3-δ1 、BaNaO _3-δ1 、MgNaO _3-δ1 、BeNaO _3-δ1 、

SrKO _3-δ1 、CaKO _3-δ1 、BaKO _3-δ1 、MgKO _3-δ1 、BeKO _3-δ1 、

SrRbO _3-δ1 、CaRbO _3-δ1 、BaRbO _3-δ1 、MgRbO _3-δ1 、BeRbO _3-δ1 、

LiTiO _3-δ2 、NaTiO _3-δ2 、KTiO _3-δ2 、RbTiO _3-δ2 、

LiZrO _3-δ2 、NaZrO _3-δ2 、KZrO _3-δ2 、RbZrO _3-δ2 、

LiHfO _3-δ2 、NaHfO _3-δ2 、KHfO _3-δ2 、RbHfO _3-δ2 、

ScAlO _3-δ3 、YAlO _3-δ3 、LaAlO _3-δ3 、CeAlO _3-δ3 、PrAlO _3-δ3 、NdAlO _3-δ3 、SmAlO _3-δ3 、DyAlO _3-δ3 、

ScGaO _3-δ3 、YGaO _3-δ3 、LaGaO _3-δ3 、CeGaO _3-δ3 、PrGaO _3-δ3 、NdGaO _3-δ3 、SmGaO _3-δ3 、DyGaO _3-δ3 、

ScInO _3-δ3 、YInO _3-δ3 、LaInO _3-δ3 、CeInO _3-δ3 、PrInO _3-δ3 、NdInO _3-δ3 、SmInO _3-δ3 and DyInO (DyIno) _3-δ3 ，

Wherein, 1.5 is less than or equal to 3-delta 1 is less than or equal to 3.0,1.5 is less than or equal to 3-delta 2 is less than or equal to 3.0, and 2.5 is less than or equal to 3-delta 3 is less than or equal to 3.0.

18. The capacitor of claim 15 wherein

The intermediate layer hasIs defined by the thickness of the substrate,

a Schottky Barrier Height (SBH) between the dielectric layer and the first or second thin film electrode layer is 1.5eV or more, and

the intermediate layer is an epitaxial layer.

19. A device, which comprises

A capacitor according to any one of claims 1 to 18.

20. The device of claim 19, wherein the device comprises a memory device, a logic device, or an energy storage device.

21. A method of making the capacitor of any one of claims 1-18, the method comprising:

forming a dielectric layer on one side of the first thin film electrode layer by epitaxial growth; and

a second thin film electrode layer is formed on the dielectric layer to thereby provide the capacitor.

22. The method of claim 21, wherein the epitaxial growth is performed at a temperature of 600 ℃ or less.

23. The method of claim 21, further comprising:

prior to the formation of the dielectric layer,

an intermediate layer is formed on the one side of the first thin film electrode layer by epitaxial growth.