CN117219609A - Chip packaging structure and packaging method - Google Patents

Abstract

The application provides a chip packaging structure and a packaging method. The chip packaging structure comprises a substrate, a first functional chip and a second functional chip. The substrate includes opposing first and second surfaces. The first functional chip is arranged on the first surface of the substrate and comprises a first active surface and a first back surface which are opposite to each other, and the first back surface faces the first surface of the substrate; the second functional chip is arranged on the first surface of the substrate, the second functional chip comprises a second active surface and a second back surface which are opposite, the second active surface faces the first surface of the substrate, the second active surface comprises a first connection area and a second connection area, the first connection area is electrically connected with the first active surface of the first functional chip through a first metal bump, and the second connection area is electrically connected with the substrate through a second metal bump. The method can improve the integration level and the interconnection density of the chip and save the preparation cost.

Description

Chip packaging structure and packaging method

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a chip packaging structure and a packaging method.

Background

With the development of semiconductor technology, the feature size of integrated circuits is continuously decreasing, and moore's law is challenged in many ways. To continue moore's law, one began to turn his eyes toward 2.5D/3DIC technology based on through silicon via (Through Silicon Via, TSV) interconnects. The 2.5D/3DIC achieves shorter interconnect lines by metal filled through silicon vias to make interconnect delays and power consumption smaller, while achieving higher integration density by vertically stacking different layers of circuitry to make electrical performance better.

However, through Silicon Vias (TSVs) are fabricated by a silicon etching process, and then the through silicon vias require techniques such as oxidation of an insulating layer, holding of a thin wafer, etc., and such an interconnection structure has problems of high fabrication cost or complicated fabrication process.

Disclosure of Invention

Aiming at the defects of the related art, the application provides a chip packaging structure and a packaging method, which are used for solving the problems of higher preparation cost or complicated preparation process of the chip packaging structure in the related art.

The application provides a chip packaging structure which comprises a substrate, a first functional chip and a second functional chip, wherein the substrate comprises a first surface and a second surface which are opposite, a circuit layer is arranged in the substrate, and the second surface is used for leading out electricity; the first functional chip is arranged on the first surface of the substrate and comprises a first active surface and a first back surface which are opposite to each other, the first back surface faces the first surface of the substrate, and the first functional chip is electrically connected with the substrate; the second functional chip is arranged on the first surface of the substrate, the second functional chip comprises a second active surface and a second back surface which are opposite, the second active surface faces the first surface of the substrate, the second active surface comprises a first connection area and a second connection area, the orthographic projection of the first connection area on the substrate is overlapped with the orthographic projection of the first functional chip on the substrate, the orthographic projection of the second connection area on the substrate is not overlapped with the orthographic projection of the first functional chip on the substrate, the first connection area is electrically connected with the first active surface of the first functional chip through a first metal bump, and the second connection area is electrically connected with the substrate through a second metal bump.

According to the above embodiment, the chip packaging structure provided by the present application combines the advantages of flip-chip packaging and stack-up packaging, so that the orthographic projection portions of the first functional chip and the second functional chip in the thickness direction of the substrate overlap, and the remaining portions do not overlap. And one part of the second functional chip can be flip-chip packaged on the substrate, and the other part of the second functional chip is flip-chip packaged on the first functional chip, so that the size of the chip packaging structure in the horizontal direction can be reduced, the integration level and the interconnection density of the chip are improved, and the interconnection length is reduced. Meanwhile, the first active surface of the first functional chip and the second active surface of the second functional chip face each other, so that electrical interconnection can be realized between the first active surface and the second active surface without through silicon vias. In addition, as the second active surface of the second functional chip faces the substrate, only the first connecting area is overlapped between the orthographic projection of the second functional chip on the substrate and the orthographic projection of the first functional chip on the substrate, and the second connecting area of the second functional chip is not influenced by the blocking of the first functional chip, the electrical interconnection can be realized without through silicon through holes. Therefore, the first functional chip, the second functional chip and the substrate can be interconnected without through silicon vias, so that the preparation cost is saved, the preparation process is simplified, the electrical property is improved, and the reliability of the chip packaging structure is improved. Moreover, as the first active surface of the first functional chip is far away from the substrate, part of the area is overlapped with the second functional chip, and the rest area is not overlapped with the second functional chip, the area which is not overlapped is not blocked by the second functional chip, so that port interconnection communication with the external environment or other peripheral chips can be realized, more available space is provided for the functional chips in the chip packaging structure to exert more functions, the application range of the chips is widened, and the packaging area is maximally utilized.

In one embodiment, the first metal bump has a dimension along a first direction that is less than a dimension along the first direction of the second metal bump, the first direction being a direction in which the first surface points toward the second surface.

In one embodiment, the first active surface of the first functional chip is electrically connected to the first surface of the substrate by a metal lead.

In one embodiment, an interconnection wiring layer is further disposed on a side, close to the substrate, of the second active surface of the second functional chip, and at least one first metal bump is electrically connected to the second metal bump through the interconnection wiring layer.

In one embodiment, the first functional chip is a sense chip, and the first active surface of the first functional chip includes a photosensitive region and a non-photosensitive region.

In one embodiment, the orthographic projection of the second functional chip on the substrate does not overlap with the orthographic projection of the photosensitive region on the substrate.

In one embodiment, the first functional chip further comprises a sealing ring frame and a light-transmitting cover plate, wherein the sealing ring frame is located in the non-photosensitive region on the first active surface and at least partially surrounds the photosensitive region. The light-transmitting cover plate is positioned on one side of the sealing ring frame far away from the first active surface and at least partially covers the photosensitive area.

In one embodiment, the sealing ring frame and the light-transmitting cover plate are of relatively independent structures;

in one embodiment, the sealing ring frame is integrally formed with the light-transmissive cover plate.

In one embodiment, the chip package structure further includes a filler material at least partially surrounding and covering the first functional chip and the second functional chip.

In one embodiment, the second functional chip is a signal processing chip.

The application also provides a packaging method of the chip packaging structure, which comprises the following steps:

providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite, a circuit layer is arranged in the substrate, and the second surface is used for leading out electricity;

providing a first functional chip, wherein the first functional chip comprises a first active surface and a first back surface which are opposite to each other, and the first back surface of the first functional chip is fixed on the first surface of the substrate so as to enable the first active surface of the first functional chip to be electrically connected with the substrate;

providing a second functional chip, wherein the second functional chip comprises a second active surface and a second back surface which are opposite, the second active surface comprises a first connecting area and a second connecting area, the first connecting area of the second active surface is fixed on the first active surface of the first functional chip and is electrically connected with the first active surface, and the second connecting area of the second active surface is fixed on the first surface of the substrate and is electrically connected with the first surface.

In one embodiment, the providing a second functional chip, where the second functional chip includes a second active surface and a second back surface opposite to each other, the second active surface includes a first connection region and a second connection region, the first connection region of the second active surface is fixed on the first active surface of the first functional chip and electrically connected to the first active surface, and the second connection region of the second active surface is fixed on the first surface of the substrate and electrically connected to the first surface specifically includes:

providing the second functional chip, wherein the second active surface of the second functional chip comprises the first connecting region and the second connecting region, the first connecting region of the second active surface is provided with a plurality of first bonding pads, and the second connecting region of the second active surface is provided with a plurality of second bonding pads;

forming a first solder on the first bonding pad and forming a second solder on the second bonding pad;

planting initial solder balls on the second solder;

forming first solder balls by the first solder, and forming second solder balls by fusing the second solder and the initial solder balls;

flip-chip packaging the first connection region of the second active surface of the second functional chip with the first solder ball and the second solder ball on the first active surface of the first functional chip, and flip-chip packaging the second connection region of the second active surface on the first surface of the substrate.

In one embodiment, after the fixing the first connection region of the second active surface to the first active surface of the first functional chip and electrically connecting with the first active surface, fixing the second connection region of the second active surface to the first surface of the substrate and electrically connecting with the first surface further includes:

and forming a filling material on the substrate, wherein the filling material at least partially surrounds and covers the first functional chip and the second functional chip.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of a chip package structure in the related art;

FIG. 2 is a schematic diagram of another chip package structure according to the related art;

FIG. 3 is a schematic diagram of another chip package structure according to the related art;

FIG. 4 is a schematic diagram of another chip package structure according to the related art;

fig. 5 is a schematic structural diagram of a chip package structure according to the present application;

FIG. 6 is a schematic diagram illustrating an embodiment of the chip package structure shown in FIG. 5;

FIG. 7 is a schematic diagram of another embodiment of the chip package structure shown in FIG. 5;

fig. 8 is a schematic structural diagram of another chip package structure according to the present application;

fig. 9 is a schematic structural diagram of another chip package structure according to the present application;

fig. 10 is a schematic structural diagram of another chip package structure according to the present application;

fig. 11 is a schematic structural diagram of another chip package structure according to the present application;

fig. 12a to 12g are schematic views illustrating the structure of each step of the packaging method of the chip packaging structure according to the present application.

Wherein: 1-a substrate; 101-a first surface; 102-a second surface; 2-a first functional chip; 201-a first active face; 202-a first back side; 21-a sealing ring frame; 22-a light-transmitting cover plate; 3-a second functional chip; 301-a second active surface; 302-a second backside; 31-a first bonding pad; 32-a second bonding pad; 33-an interconnect wiring layer; 4-first metal bumps; 41-a first metal column; 42-third solder balls; 5-a second metal bump; 51-a second metal post; 52-fourth solder balls; 6-metal leads; 7-filling material; 81-a first solder; 82-a second solder; 83-initial solder balls; a1-a first connection region; a2-a second linking region; b1-a photosensitive region; b2-non-photosensitive region.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

Research has found that with the rapid development of science and technology and human society, routing systems built up by high-performance computing and electronic products used by us are large, and integrated circuits (i.e. chips) are indispensable devices. At present, the systems and products are developed towards small size and light weight, so that the requirements on the integration level and the size of the chip are higher and higher, and the packaging difficulty is higher and higher. Fig. 1 to 4 are schematic diagrams of a chip package structure in the related art. Specifically, as shown in fig. 1, active surfaces of the first functional chip 2 and the second functional chip 3 are both located above, and when the two functional chips are stacked and packaged on the substrate 1, both functional chips need to be interconnected and electrically connected to the substrate 1 through-silicon vias TSV. For example, for the integrated sensing and calculating chip, when the first functional chip 2 is a front-illuminated sensing chip and the second functional chip 3 is a calculating chip, the sensing area cannot be shielded because the light sensing surface of the front-illuminated sensing chip needs to collect external signals, the light sensing surface (not shown in the figure) of the front-illuminated sensing chip needs to be disposed above, and the active surface of the front-illuminated sensing chip is also disposed above, so that the front-illuminated sensing chip needs to be electrically connected to the calculating chip and the substrate 1 through the through-silicon vias TSV, and the calculating chip needs to be electrically connected to the substrate 1 through the through-silicon vias TSV. As shown in fig. 2, the active surface of the first functional chip 2 is located below, and the active surface of the second functional chip 3 is located above or below, so that the second functional chip 3 still needs to be electrically connected to the substrate 1 or the first functional chip 2 through the TSV. For example, when the first functional chip 2 is a backside illuminated sensing chip and the second functional chip is a computing chip, the light sensing surface (not shown in the figure) of the backside illuminated sensing chip is disposed on the back surface, and the light sensing surface of the sensing chip needs to collect external signals, so that the back surface of the backside illuminated sensing chip is located above and the active surface is located below, and therefore the backside illuminated sensing chip can be connected with the computing chip without through-silicon-via (TSV), however, when the active surface of the second functional chip 3 is located on the upper surface, the computing chip still needs to be electrically connected with the substrate 1 through the through-silicon-via (TSV), and when the active surface of the second functional chip 3 is located on the lower surface (not shown in the figure), the computing chip still needs to be electrically connected with the sensing chip through the through-silicon-via (TSV). The packaging modes in fig. 1 or fig. 2 all adopt stacked packaging, so that the size of the chip in the horizontal direction can be reduced, the integration level can be improved, however, interconnection packaging can be realized through the TSV (through silicon via) side, and the manufacturing cost is high. As shown in fig. 3, when the active surface of the first functional chip 2 is located above the active surface, interconnection with the substrate 1 is still required by the TSV technology. For example, when the first functional chip 2 is a front-illuminated sensing chip, the light-sensitive surface of the front-illuminated sensing chip is disposed on the active surface, and because the light-sensitive surface of the sensing chip needs to collect external signals, the active surface of the front-illuminated sensing chip is located above, and still needs to be interconnected with the substrate 1 through a through-silicon via TSV technology. As shown in fig. 4, when the active surface of the first functional chip 2 is located below, although interconnection is not required by the through-silicon vias TSV, since the first functional chip 2 and the second functional chip 3 are sequentially arranged on the same plane, the area of the plane occupied by the chips in the package structure is increased, and the lateral dimension is larger, which is disadvantageous for improvement of the integration level. For example, when the first functional chip 2 is a backside illuminated sensing chip, the packaging method can be adopted, however, the thinning and bonding process of the backside illuminated sensing chip is difficult, so that the manufacturing of the backside illuminated sensing chip requires high-end equipment, and the process is complex and the cost is high. Therefore, there is a need for a chip package structure with higher integration, better electrical performance, or lower cost.

The application provides a chip packaging structure and a packaging method, which aim to solve the technical problems in the related art.

The following describes a chip package structure and a packaging method in the embodiment of the present application in detail with reference to the accompanying drawings. The features of the embodiments described below can be supplemented or combined with one another without conflict.

The application provides a chip packaging structure, which comprises a substrate 1, a first functional chip 2 and a second functional chip 3 as shown in fig. 5. The substrate 1 includes a first surface 101 and a second surface 102 opposite to each other, a circuit layer is disposed in the substrate 1, and the second surface 102 is used for electrically leading out; the first functional chip 2 is arranged on the first surface 101 of the substrate 1, the first functional chip 2 comprises a first active surface 201 and a first back surface 202 which are opposite, the first back surface 202 faces the first surface 101 of the substrate 1, and the first functional chip 2 is electrically connected with the substrate 1; the second functional chip 3 is disposed on the first surface 101 of the substrate 1, the second functional chip 3 includes a second active surface 301 and a second back surface 302 opposite to each other, the second active surface 301 faces the first surface 101 of the substrate 1, the second active surface 301 includes a first connection area A1 and a second connection area A2, an orthographic projection of the first connection area A1 on the substrate 1 overlaps an orthographic projection of the first functional chip 2 on the substrate 1, an orthographic projection of the second connection area A2 on the substrate 1 does not overlap an orthographic projection of the first functional chip 2 on the substrate 1, the first connection area A1 is electrically connected with the first active surface 201 of the first functional chip 2 through the first metal bump 4, and the second connection area A2 is electrically connected with the substrate 1 through the second metal bump 5.

As can be seen from the above embodiments, the chip package structure provided by the present application combines the advantages of flip-chip package and stack-package, such that the orthographic projection portions of the first functional chip 2 and the second functional chip 3 in the thickness direction of the substrate 1 overlap, and the remaining portions do not overlap. A part of the second functional chip 3 can be flip-chip packaged on the substrate 1, and the other part of the second functional chip is flip-chip packaged on the first functional chip 2, so that the size of the chip packaging structure in the horizontal direction can be reduced, the integration level and the interconnection density of the chip can be improved, and the interconnection length can be reduced. Meanwhile, since the first active surface 201 of the first functional chip 2 and the second active surface 301 of the second functional chip 3 face each other in the present application, electrical interconnection can be achieved between the two without through silicon vias TSV. In addition, since the second active surface 301 of the second functional chip 3 faces the substrate 1, only the first connection area A1 overlaps between the front projection of the second functional chip 3 on the substrate 1 and the front projection of the first functional chip 2 on the substrate 1, and the second connection area A2 of the second functional chip 3 and the substrate 1 are not affected by the blocking of the first functional chip 2, and the electrical interconnection can be realized without through-silicon vias TSV. Therefore, the first functional chip 2, the second functional chip 3 and the substrate 1 can be interconnected without Through Silicon Vias (TSVs), so that the preparation cost is saved, the preparation process is simplified, the electrical property is improved, and the reliability of the chip packaging structure is improved. Furthermore, since the first active surface 201 of the first functional chip 2 is away from the substrate 1, a part of the area overlaps the second functional chip 3, and the remaining area does not overlap the second functional chip 3, the area which does not overlap is not blocked by the second functional chip 3, so that port interconnection communication with the external environment or other peripheral chips can be realized, more available space is provided for the functional chips in the chip packaging structure to perform more functions, the application range of the chips is widened, and the packaging area is maximized.

In some embodiments, as shown in fig. 5, a dimension d1 of the first metal bump 4 along the first direction y is smaller than a dimension d2 of the second metal bump 5 along the first direction y, where the first direction y is a direction in which the first surface 101 points toward the second surface 102.

In this embodiment, since the first functional chip 2 and the second functional chip 3 are partially stacked along the thickness direction of the substrate 1, when the second functional chip 3 is flip-chip packaged on the substrate 1, if the sizes of the metal bumps for fixing connection are the same, the stacked portion of the second functional chip 3 and the first functional chip 2 may be lifted, which is not beneficial to the stability of the packaging structure of the second functional chip 3, and may cause the second active surface 301 of the second functional chip 3 to receive uneven force, and to be easily bent and deformed. Therefore, the dimension d1 of the first metal bump 4 along the first direction y for fixing the first connection region A1 of the lamination portion is smaller than the dimension d2 of the second metal bump 5 along the first direction y for fixing the second connection region A2, so that the stability and reliability of the second functional chip 3 can be improved.

In some embodiments, the dimension d1 of the first metal bump 4 in the first direction y is 10 μm to 50 μm, and the dimension d2 of the second metal bump 5 in the second direction is 80 μm to 500 μm. It should be noted that, in the present embodiment, the dimensions of the first metal bump 4 and the second metal bump 5 are designed based on the thickness of the first functional chip 2 and the interconnection density, and those skilled in the art can flexibly set the dimensions, which are not limited thereto, so as to ensure that the package structure of the second functional chip 3 is uniformly stressed.

In some embodiments, the first metal bump 4 and the second metal bump 5 are solder balls or metal stud bumps. The second functional chip 3 is interconnected with the first functional chip 2 through the first metal bumps 4, and the second functional chip 3 is interconnected with the substrate 1 through the second metal bumps 5 and information transmission among the first functional chip 2, the second functional chip 3 and other systems is realized.

In one example, as shown in fig. 5 to 10, the first metal bump 4 and the second metal bump 5 are each a solder ball. Illustratively, the solder balls are tin.

In another example, as shown in fig. 11, the first metal bump 4 and the second metal bump 5 are both metal stud bumps, the first metal bump 4 is composed of a first metal stud 41 and a third solder ball 42 stacked in order along a first direction y, and the second metal bump 5 is composed of a second metal stud 51 and a fourth solder ball 52 stacked in order along the first direction y. The interconnection density can be improved by adopting the metal stud bump for interconnection. Illustratively, the first metal pillar 41 and the second metal pillar 51 are both made of copper.

In some embodiments, as shown in fig. 5 to 10, the first connection area A1 of the second active surface 301 in the second functional chip 3 is provided with a first pad 31, the second connection area A2 is provided with a second pad 32, and the size of the first pad 31 is smaller than the size of the second pad 32. The first pads 31 correspond to the interconnections between the first metal bumps 4 and the second pads 32 correspond to the interconnections between the second metal bumps 5. Specifically, the dimensions of the first pads 31 and the second pads 32 are designed to fit between the corresponding first metal bumps 4 and second metal bumps 5.

In some embodiments, as shown in fig. 6, the first active surface 201 of the first functional chip 2 is electrically connected to the first surface 101 of the substrate 1 through the metal lead 6. In this embodiment, since the first active surface 201 of the first functional chip 2 faces away from the substrate 1, the electrical connection between the first functional chip 2 and the substrate 1 can be achieved by wire bonding, and the through silicon vias TSV are not required, so that the manufacturing process can be simplified and the manufacturing cost can be saved.

In some embodiments, as shown in fig. 7, an interconnection wiring layer 33 is further disposed on a side of the second active surface 301 of the second functional chip 3, which is close to the substrate 1, and at least one first metal bump 4 is electrically connected to the second metal bump 5 through the interconnection wiring layer 33. In this embodiment, the interconnection wiring layer 33 is added on the second active surface 301 of the second functional chip 3, so that the electrical connection between the first functional chip 2 and the substrate 1 can be realized through the paths of the first functional chip 2, the first metal bump 4, the interconnection wiring layer 33, the second metal bump 5 and the substrate 1, thereby realizing that the substrate 1 supplies power to the first functional chip 2 and ensuring the normal operation of the chips.

In some embodiments, as shown in fig. 8, the first functional chip 2 is a sensing chip, and the first active surface 201 of the first functional chip 2 includes a photosensitive region B1 and a non-photosensitive region B2.

In this embodiment, the first active surface 201 of the first functional chip 2 includes photosensitive areas B1 and non-photosensitive areas B2 alternately arranged along the second direction x, where the photosensitive areas B1 of the first functional chip 2 are located on the first active surface 201, and then the first functional chip 2 may specifically be a front-illuminated sensing chip, and external signals received by the photosensitive areas B1 of the first functional chip 2 are transmitted to the second functional chip 3 through the first metal bumps 4.

In some embodiments, as shown in fig. 8, the orthographic projection of the second functional chip 3 on the substrate 1 does not overlap with the orthographic projection of the photosensitive region B1 on the substrate 1. In this embodiment, there is no overlapping area between the photosensitive area B1 and the second functional chip 3 in the thickness direction, so as to avoid that the photosensitive area B1 of the first functional chip 2 is blocked, and the reception of external sensing signals is affected.

In some embodiments, as shown in fig. 9, the first functional chip 2 further includes a sealing ring frame 21 and a light-transmitting cover plate 22. Wherein the sealing ring frame 21 is located in the non-photosensitive area B2 on the first active surface 201 and at least partially surrounds the photosensitive area B1. The light-transmitting cover plate 22 is located on one side of the sealing ring frame 21 away from the first active surface 201 and at least partially covers the photosensitive area B1. In this embodiment, the sealing ring frame 21 and the transparent cover plate 22 are added in the chip packaging structure provided with the sensing chip, so that the photosensitive area B1 of the first functional chip 2 can be further protected. The sealing ring frame 21 is made of metal, and the transparent cover plate 22 is made of glass or quartz.

In some embodiments, the sealing ring frame 21 is located in the non-photosensitive area B2, completely surrounds the photosensitive area B1, and the sealing ring frame 21 is square, circular or polygonal and can be adaptively designed according to the shape of the photosensitive area B1.

In some embodiments, the front projection of the transparent cover 22 on the substrate 1 completely overlaps the photosensitive area B1 or is slightly larger than the photosensitive area B1.

In some embodiments, as shown in fig. 9, the sealing ring frame 21 and the transparent cover plate 22 are relatively independent structures.

In some embodiments, the sealing ring frame 21 and the transparent cover plate 22 are integrally formed (not shown in the drawings), so as to improve the tightness of the photosensitive area B1 of the chip package structure and avoid the interference of external dust or water vapor.

In some embodiments, as shown in fig. 10, the chip package structure further includes a filler material 7. The filling material 7 at least partly encloses and covers the first functional chip 2 and the second functional chip 3. The filling material 7 in this embodiment can further fix the positions of the first functional chip 2 and the second functional chip 3 on the substrate 1, and fill the packaging gap, so as to protect the weak links of the packaging from the surrounding environment such as moisture, ion pollutants, and the like. And a part of mechanical support is provided for the packaging body, so that the mechanical stress borne by the welding spots under dynamic impact loads such as vibration, drop and the like is shared, and the mechanical reliability of the packaging is enhanced. The filler material 7 is illustratively an epoxy resin.

In some embodiments, the second functional chip 3 is a signal processing chip. The signal transmitted by the first functional chip 2 can be processed, so that the high-speed transmission and the local real-time processing of the sensing signal are realized, the performance of the chip is improved, and the application range of the chip is widened. The second functional chip 3 is illustratively a memory chip or a computing chip.

In some embodiments, an adhesive layer (not shown in the figures) is further provided between the first functional chip 2 and the substrate 1, for fixing the first functional chip 2 to the substrate 1.

Based on the same inventive concept, as shown in fig. 12a to 12g, the application also provides a packaging method of a chip packaging structure, which comprises the following steps:

step 100: as shown in fig. 12a, a substrate 1 is provided, the substrate 1 includes a first surface 101 and a second surface 102 opposite to each other, a circuit layer is provided in the substrate 1, and the second surface 102 is used for electrically leading out;

step 200: as shown in fig. 12b, a first functional chip 2 is provided, the first functional chip 2 includes a first active surface 201 and a first back surface 202 that are opposite to each other, and the first back surface 202 of the first functional chip 2 is fixed on the first surface 101 of the substrate 1, so that the first active surface 201 of the first functional chip 2 is electrically connected with the substrate 1;

step 300: as shown in fig. 12c to 12g, a second functional chip 3 is provided, the second functional chip 3 includes a second active surface 301 and a second back surface 302 that are opposite, the second active surface 301 includes a first connection region A1 and a second connection region A2, the first connection region A1 of the second active surface 301 is fixed on the first active surface 201 of the first functional chip 2 and electrically connected to the first active surface 201, and the second connection region A2 of the second active surface 301 is fixed on the first surface 101 of the substrate 1 and electrically connected to the first surface 101.

In this embodiment, the packaging method for wind packaging the first functional chip 2 and the second functional chip 3 on the substrate 1 can realize electrical interconnection between the first functional chip 2 and the second functional chip 3 without through silicon vias TSV, thereby saving the manufacturing cost, simplifying the manufacturing process, improving the integration level and interconnection density of the chips, and reducing the interconnection length. The specific beneficial effects can be seen from the chip packaging structure provided in the foregoing embodiment, and the details are not repeated here.

In some embodiments, as shown in fig. 12c to 12g, the step 300 specifically includes:

step 310: as shown in fig. 12c, a second functional chip 3 is provided, the second active surface 301 of the second functional chip 3 includes a first connection area A1 and a second connection area A2, the first connection area A1 of the second active surface 301 is provided with a plurality of first pads 31, and the second connection area A2 of the second active surface 301 is provided with a plurality of second pads 32;

step 320: as shown in fig. 12d, a first solder 81 is formed on the first pad 31, and a second solder 82 is formed on the second pad 32;

step 330: as shown in fig. 12e, an initial solder ball 83 is planted on the second solder 82;

step 340: as shown in fig. 12f, the first solder 81 is formed into a first solder ball, and the second solder 82 and the initial solder ball 83 are fused to form a second solder ball;

step 350: as shown in fig. 12g, the first connection area A1 of the second active surface 301 of the second functional chip 3 with the first solder ball and the second solder ball is flip-chip packaged on the first active surface 201 of the first functional chip 2, and the second connection area A2 of the second active surface 301 is flip-chip packaged on the first surface 101 of the substrate 1.

In this embodiment, solder balls with different sizes can be prepared by one solder ball, so that the second functional chip 3 is fixedly connected with the substrate 1 and the first functional chip 2, the preparation process is simplified, and the reliability of the chip packaging structure is improved.

In some embodiments, the first solder 81 is formed into a first solder ball and the second solder 82 and the initial solder ball 83 are fused to form a second solder ball by a reflow process in step 340.

In some embodiments, as shown in fig. 8, the first active surface 201 of the first functional chip 2 in step 200 includes a photosensitive region B1 and a non-photosensitive region B2, and the front projection of the second functional chip 3 on the substrate 1 does not overlap with the front projection of the photosensitive region B1 on the substrate 1.

In some embodiments, as shown in fig. 9, the first functional chip 2 in step 200 further includes a sealing ring frame 21 and a light-transmitting cover plate 22, where the sealing ring frame 21 is located in the non-photosensitive area B2 on the first active surface 201 and at least partially surrounds the photosensitive area B1; the light-transmitting cover plate 22 is located on one side of the sealing ring frame 21 away from the first active surface 201 and at least partially covers the photosensitive area B1.

In some embodiments, as shown in fig. 10, step 300 further comprises the following steps:

step 400: a filler material 7 is formed on the substrate 1, the filler material 7 at least partially surrounding and covering the first functional chip 2 and the second functional chip 3.

In some embodiments, as shown in fig. 11, the interconnection is implemented by using a metal stud bump in the present application, and the remaining steps in this embodiment are the same as those in the previous embodiment, except that: in step 310, the first metal pillar 41 is disposed on the first bonding pad 31, and the second metal pillar 51 is disposed on the second bonding pad 32; in step 320, the first solder 81 is formed on the first metal pillar 41, and the second solder 82 is formed on the second metal pillar 51. The remaining steps are the same and are described in detail in the previous examples.

The above embodiments of the present application may be complementary to each other without collision.

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, acts, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed herein may be alternated, altered, rearranged, disassembled, combined, or eliminated. Further, steps, measures, schemes in the related art having various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations should and are intended to be comprehended within the scope of the present application.

Claims (13)

1. A chip package structure, comprising:

the substrate comprises a first surface and a second surface which are opposite to each other, a circuit layer is arranged in the substrate, and the second surface is used for leading out electricity;

the first functional chip is arranged on the first surface of the substrate and comprises a first active surface and a first back surface which are opposite to each other, the first back surface faces the first surface of the substrate, and the first functional chip is electrically connected with the substrate;

the second functional chip is arranged on the first surface of the substrate, the second functional chip comprises a second active surface and a second back surface which are opposite, the second active surface faces the first surface of the substrate, the second active surface comprises a first connection area and a second connection area, the orthographic projection of the first connection area on the substrate is overlapped with the orthographic projection of the first functional chip on the substrate, the orthographic projection of the second connection area on the substrate is not overlapped with the orthographic projection of the first functional chip on the substrate, the first connection area is electrically connected with the first active surface of the first functional chip through a first metal bump, and the second connection area is electrically connected with the substrate through a second metal bump.

2. The chip package structure of claim 1, wherein a dimension of the first metal bump in a first direction is smaller than a dimension of the second metal bump in the first direction, the first direction being a direction in which the first surface points to the second surface.

3. The chip package structure of claim 1, wherein the first active surface of the first functional chip is electrically connected to the first surface of the substrate by a metal lead.

4. The chip package structure according to claim 1, wherein an interconnection wiring layer is further disposed on a side of the second active surface of the second functional chip, which is close to the substrate, and at least one of the first metal bumps is electrically connected to the second metal bump through the interconnection wiring layer.

5. The chip package structure of claim 1, wherein the first functional chip is a sense chip, and the first active surface of the first functional chip includes a photosensitive region and a non-photosensitive region.

6. The chip package structure of claim 5, wherein the orthographic projection of the second functional chip on the substrate does not overlap with the orthographic projection of the photosensitive region on the substrate.

7. The chip package structure of claim 5, wherein the first functional chip further comprises:

a seal ring frame located within the non-photosensitive region on the first active surface, at least partially surrounding the photosensitive region;

and the light-transmitting cover plate is positioned on one side of the sealing ring frame away from the first active surface and at least partially covers the photosensitive area.

8. The chip package structure of claim 7, wherein the sealing ring frame and the light-transmitting cover plate are of a relatively independent structure;

or, the sealing ring frame and the light-transmitting cover plate are integrally formed.

9. The chip package structure of claim 7, further comprising:

and a filling material at least partially surrounding and covering the first functional chip and the second functional chip.

10. The chip package structure of claim 1, wherein the second functional chip is a signal processing chip.

11. A packaging method of a chip packaging structure, comprising:

providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite, a circuit layer is arranged in the substrate, and the second surface is used for leading out electricity;

providing a first functional chip, wherein the first functional chip comprises a first active surface and a first back surface which are opposite to each other, and the first back surface of the first functional chip is fixed on the first surface of the substrate so as to enable the first active surface of the first functional chip to be electrically connected with the substrate;

providing a second functional chip, wherein the second functional chip comprises a second active surface and a second back surface which are opposite, the second active surface comprises a first connecting area and a second connecting area, the first connecting area of the second active surface is fixed on the first active surface of the first functional chip and is electrically connected with the first active surface, and the second connecting area of the second active surface is fixed on the first surface of the substrate and is electrically connected with the first surface.

12. The method of claim 11, wherein providing a second functional chip, the second functional chip including a second active surface and a second back surface opposite to each other, the second active surface including a first connection region and a second connection region, the first connection region of the second active surface being fixed to and electrically connected with the first active surface of the first functional chip, the second connection region of the second active surface being fixed to and electrically connected with the first surface of the substrate, specifically comprising:

providing the second functional chip, wherein the second active surface of the second functional chip comprises the first connecting region and the second connecting region, the first connecting region of the second active surface is provided with a plurality of first bonding pads, and the second connecting region of the second active surface is provided with a plurality of second bonding pads;

forming a first solder on the first bonding pad and forming a second solder on the second bonding pad;

planting initial solder balls on the second solder;

forming first solder balls by the first solder, and forming second solder balls by fusing the second solder and the initial solder balls;

flip-chip packaging the first connection region of the second active surface of the second functional chip with the first solder ball and the second solder ball on the first active surface of the first functional chip, and flip-chip packaging the second connection region of the second active surface on the first surface of the substrate.

13. The method of claim 11, further comprising, after the fixing the first connection region of the second active surface to the first active surface of the first functional chip and electrically connecting the first active surface and the second connection region of the second active surface to the first surface of the substrate and electrically connecting the second connection region of the second active surface to the first surface:

and forming a filling material on the substrate, wherein the filling material at least partially surrounds and covers the first functional chip and the second functional chip.