CN117215990A

CN117215990A - Inter-core communication method and device of multi-core chip and multi-core chip

Info

Publication number: CN117215990A
Application number: CN202311175100.3A
Authority: CN
Inventors: 梁申麟; 秦海俊; 赵梓奎
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2023-12-12

Abstract

The application discloses an inter-core communication method and equipment of a multi-core chip and the multi-core chip, and belongs to the technical field of communication. The method comprises the following steps: the first processor core stores the communication data into the shared memory, and writes the communication data into the common memory at a first shared memory address in the shared memory; the first processor core sends a first external interrupt signal to the second processor core through a shared external interrupt source of the second processor core, wherein the first external interrupt signal is used for the second processor core to acquire a first shared memory address from a public memory; and acquiring communication data from the shared memory according to the first shared memory address. The application can complete inter-core communication in a software mode without using hardware, and reduces the hardware requirement.

Description

Inter-core communication method and device of multi-core chip and multi-core chip

Technical Field

The embodiment of the application relates to the technical field of communication, in particular to an inter-core communication method and equipment of a multi-core chip and the multi-core chip.

Background

With the continuous increase of the Chip function requirements, a System on Chip (SoC) internally includes a plurality of processors, each processor includes a plurality of processor cores, and the plurality of processor cores are heterogeneous, so that the communication mechanism among the plurality of processor cores of the SoC can enable each core to exert respective computing advantages.

In the related art, the inter-core communication method of the multi-core chip needs to establish a hardware Mailbox (Mailbox) channel between each group of cores, and the inter-core communication is realized based on the hardware Mailbox channel. However, when the number of processor cores increases, the communication method needs to rely on the support of hardware resources, resulting in lower utilization of hardware resources and increased design cost of the SoC.

Disclosure of Invention

The embodiment of the application provides an inter-core communication method and equipment of a multi-core chip and the multi-core chip, which can be used for solving the problems existing in the related technology. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a method for inter-core communication of a multi-core chip, where the method includes:

the method comprises the steps that a first processor core stores communication data into a shared memory, and a first shared memory address of the communication data in the shared memory is written into a preset public memory according to a preset communication protocol;

the first processor core sends a first external interrupt signal to a second processor core through a shared external interrupt source of the second processor core;

the second processor core receives the first external interrupt signal, and the second processor core acquires the first shared memory address from the public memory according to the first external interrupt signal; and acquiring the communication data from the shared memory according to the first shared memory address.

In another aspect, a multi-core chip is provided, the chip including a first processor core for performing the functions of the first processor core described above and a second processor core for performing the functions of the second processor core in the method described above.

In another aspect, a computer device is provided, where the computer device includes a processor and a memory, where at least one computer program is stored in the memory, where the at least one computer program is loaded and executed by the processor, so that the computer device implements any of the inter-core communication methods of the multi-core chip described above.

In another aspect, there is provided a computer readable storage medium having stored therein at least one computer program loaded and executed by a processor to cause a computer to implement any of the above-described methods of inter-core communication of a multi-core chip.

In another aspect, a computer program product or computer program is provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the computer device performs any of the above-described inter-core communication methods of the multi-core chip.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

according to the inter-core communication method of the multi-core chip, communication data are stored in the shared memory through the first processor core, the first shared memory address of the communication data in the shared memory is stored in the public memory, and the interrupt trigger signal is transmitted in a mode of triggering the external interrupt source multiplexed by the other party, so that the second processor core can acquire the communication data, inter-core communication can be achieved in a software mode, hardware implementation is not needed, and hardware requirements are reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic illustration of an implementation environment provided by an embodiment of the present application;

FIG. 2 is a flow chart of a method for inter-core communication of a multi-core chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an inter-core communication scenario provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of a multi-core chip according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a server according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a terminal according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

It should be noted that the terms "first," "second," and the like in the description of the present application (if any) are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of systems and methods that are consistent with aspects of the application.

The embodiment of the application provides an inter-core communication method of a multi-core chip, please refer to fig. 1, which shows a schematic diagram of an implementation environment of the method provided by the embodiment of the application. The implementation environment may include: a computer device 11.

The product form of the computer device 11 is not limited in the embodiment of the present application. Regardless of the product form, the computer device 11 is provided with a multi-core chip, and the multi-core chip includes a processor, where the processor includes a first processor core and a second processor core, and the first processor core and the second processor core may communicate by using the inter-core communication method of the multi-core chip provided by the embodiment of the present application.

For example, the computer device 11 may be a terminal or a server. Alternatively, the terminal may be a smart device such as a cell phone, tablet computer, personal computer, or the like. The server may be a server, a server cluster comprising a plurality of servers, or a cloud computing service center. The terminal and the server establish communication connection through a wired or wireless network.

Alternatively, the terminal may be any electronic product that can perform man-machine interaction with a user through one or more modes of a keyboard, a touch pad, a touch screen, a remote controller, a voice interaction or handwriting device, such as a PC (Personal Computer ), a mobile phone, a smart phone, a PDA (Personal Digital Assistant, a personal digital assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a smart car machine, a smart television, a smart sound box, etc. The server may be a server, a server cluster comprising a plurality of servers, or a cloud computing service center. The terminal and the server establish communication connection through a wired or wireless network.

Those skilled in the art will appreciate that the above-described computer device 11 and terminals and servers are by way of example only, and that other computer devices 11 and terminals or servers, as may be present or hereafter presented, are intended to be within the scope of the present application and are incorporated herein by reference.

Based on the implementation environment shown in fig. 1, a method for inter-core communication of a multi-core chip according to an embodiment of the present application is shown in fig. 2, and the method is applied to a computer device, for example, and includes steps 201 to 204.

In step 201, the first processor core stores the communication data in the shared memory, and writes the communication data in a first shared memory address in the shared memory into a preset common memory according to a preset communication protocol.

The communication data may be any data that can be transmitted between two cores. The communication data may be generated by the first processor core, or may be transmitted to the first processor core by another core. No matter which way the first processor core obtains the communication data, for the process that the first processor core communicates with the second processor core based on the communication data, the first processor core can store the communication data into the shared memory, and because the shared memory is a memory which can be commonly accessed by two cores, the two cores can realize inter-core communication based on the shared memory.

In the process of implementing inter-core communication based on the shared memory, in order to enable the second processor core to acquire communication data from the shared memory, after the first processor core stores the communication data in the shared memory, the first processor core may further determine an address of the communication data in the shared memory, where the address may be referred to as a first shared memory address. In one possible implementation, the first processor core may store the first shared memory address in a different location than the shared memory, e.g., determining a common memory that is accessible to both the first processor core and the second processor core, writing the first shared memory address to the common memory. For example, the first shared memory address is written into the first interaction data according to a communication protocol of the first interaction data, and the first processor core writes the first interaction data into the common memory.

In one possible implementation manner, at least one of an identifier of the first processor core corresponding to the communication data and a size of the communication data is also stored in the public memory, or at least one of an identifier of the first processor core corresponding to the communication data and a size of the communication data and a first check code are also stored in the public memory; the first check code is a check code of first reference data in the public memory, the first check code is used for checking the correctness of the first reference data, and the first reference data is at least one data except the first check code, which corresponds to the communication data.

Illustratively, if the data stored in the common memory does not contain the first check code, then no check is required; verification is required if the data stored in the common memory contains a first check code. The second processor core obtains first reference data and a first check code from the public memory according to a first external interrupt signal; the second processor core obtains a verification result by performing verification calculation on bytes in the first reference data; and under the condition that the verification result accords with the first verification code, the verification is successful.

For example, if the identifier of the first processor core, the first shared memory address and the first check code corresponding to the communication data are stored in the common memory, the identifier of the first processor core and the first shared memory address corresponding to the communication data are checked; and if the identifier, the first shared memory address, the first indication information and the first check code of the first processor core corresponding to the communication data are stored in the public memory, checking the identifier, the first shared memory address and the first indication information of the first processor core corresponding to the communication data.

Illustratively, taking the checking mode of the first check code as an exclusive-or check as an example, the first check code is a first exclusive-or value, and the common memory stores at least one of a first processor core identifier corresponding to the communication data, the size of the communication data and the first exclusive-or value in addition to the first shared memory address; the first exclusive-or value is an exclusive-or value of first reference data in the common memory, and is used for checking the correctness of the first reference data, and the first reference data is at least two data except the first exclusive-or value, which correspond to the communication data.

And performing exclusive-or checking under the condition that the obtained public memory stores at least one of a first processor core identifier corresponding to the communication data and the size of the communication data and a first exclusive-or value in addition to the first shared memory address. And performing exclusive-or operation on the first byte and the second byte in the first interactive data to obtain a result, performing exclusive-or operation on the result and the next byte until all bytes except the first exclusive-or value are exclusive-or, and finally obtaining the result which is the same as the first exclusive-or value, wherein the exclusive-or check is successful.

The embodiment of the application does not limit the first shared memory address, the first indication information, the identification of the first processor core corresponding to the communication data, the size of the communication data, the length of the first exclusive-or value and the storage sequence of each content in the common memory, and can be flexibly set based on scenes. The first shared memory address, the first indication information, the identifier of the first processor core corresponding to the communication data, the size of the communication data and the first exclusive-or value are stored in the common memory, the length of the first shared memory address is 4, the length of the first indication information is 2, the length of the identifier of the first processor core is 2, the length of the size of the communication data is 4, the size of the first exclusive-or value is 1, and the first shared memory address, the first indication information, the identifier of the first processor core corresponding to the communication data, the size of the communication data and the first exclusive-or value can be stored in a format of first interactive data. For example, the structure of the first interaction data may be as shown in table 1 below.

TABLE 1

In step 202, the first processor core sends a first external interrupt signal to the second processor core via a shared external interrupt source of the second processor core.

In one possible implementation, the shared external interrupt source of the second processor core may be an existing external interrupt source of the second processor core. For example, a first processor core sending a first external interrupt signal to a second processor core through a shared external interrupt source of the second processor core, comprising: determining an external interrupt source from the external interrupt sources of the second processor core as a shared external interrupt source of the second processor core; triggering the shared external interrupt source of the second processor core to send the first external interrupt signal to the second processor core. The embodiment of the application does not limit the external interrupt source of the second processor core, and can be any external interrupt source existing in the second processor core. Exemplary external interrupt sources for the second processor core include GPIO (General Purpose Input Output, general purpose input/output), UART (Universal Asynchronous Receiver Transmitter, universal asynchronous transceiver), SPI (Serial Peripheral Interface ), PWM (Pulse Width Modulation, pulse width modulation), and the like. For example, the GPIO may be determined to be the shared external interrupt source of the second processor core.

And determining the shared external interrupt source in the existing external interrupt sources, so that the multiplexing of the external interrupt sources is realized. That is, under the condition that the external interrupt source can continuously trigger the original interrupt signal, the first external interrupt signal can be sent in the inter-core communication process.

The method of sending the first external interrupt signal to the second processor core by the first processor core through the shared external interrupt source of the second processor core is not limited in the present application, and any method capable of transmitting the first external interrupt signal may be used. Illustratively, the second processor core multiplexes the external interrupt sources by adding software code. After the first processor core writes the communication data into the public memory at the first shared memory address in the shared memory, the first processor core calls the bottom layer driving code to send a first external interrupt signal to the interrupt register of the second processor core. Wherein the interrupt register of the second processor core is a register storing and managing the first external interrupt signal. And after receiving the first external interrupt signal, the second processor core calls an interrupt processing function to process. The multiplexing interrupt source is to add a part of codes into the interrupt processing function, and a step of judging is added, when the external interrupt source multiplexed by the second processor core is triggered, the second processor core takes out the first indication information from the shared memory to judge whether the request is an inter-core communication request, if yes, the inter-core communication is carried out, otherwise, the processing is continued as the original interrupt signal processing.

In step 203, the second processor core receives a first external interrupt signal, and obtains a first shared memory address from the common memory according to the first external interrupt signal.

In one possible implementation manner, for the case where the first indication information is also stored in the common memory described in step 201, after the second processor core receives the first external interrupt signal, the method further includes: acquiring first indication information from a public memory; and executing the operation of acquiring the first shared memory address from the common memory according to the first external interrupt signal under the condition that the communication data is determined to be the inter-core communication data according to the first indication information.

For example, based on the table 1 in step 201, the second processor core may read the first indication information from the first interaction data. To indicate whether the communication data is data of inter-core communication by different values of the first indication information. For example, if the value of the first instruction information is 00, the second processor core determines that the communication data is data of inter-core communication, and if the value of the first instruction information is 11, the second processor core determines that the communication data is not data of inter-core communication. Optionally, taking as an example whether the communication data is inter-core communication data by whether the field where the first indication information is located is empty, if the field where the first indication information is located is empty, the second processor core determines that the communication data is inter-core communication data, and if the field where the first indication information is located is not empty, the second processor core determines that the communication data is not inter-core communication data.

In another possible implementation manner, for the case where the identifier of the first processor core corresponding to the communication data, at least one of the size of the communication data, and the first xor value are also stored in the common memory described in step 201, since the first xor value is an xor value of the first reference data in the common memory, and the first xor value is used to verify the correctness of the first reference data, the first reference data is at least two data corresponding to the communication data except for the first xor value. Therefore, the second processor core can check at least two data except the first exclusive-or value corresponding to the communication data according to the exclusive-or value, and after the checking is passed, the first shared memory address is acquired from the common memory.

In step 204, the second processor core obtains communication data from the shared memory according to the first shared memory address.

And obtaining a first shared memory address from the second processor core, and obtaining communication data from the shared memory indicated by the first shared memory address according to the first shared memory address, thereby realizing the communication process of the first processor core and the second processor core. After the second processor core obtains the communication data, the method provided by the embodiment of the application can consider that the inter-core communication process is finished, and does not limit the processing mode of the communication data by the second processor core.

In one possible implementation, after the second processor core obtains the communication data, as shown in fig. 2, the method provided in the embodiment of the present application may further include the following steps 205-209.

In step 205, the second processor core performs data processing on the acquired communication data to obtain processed data.

The embodiment of the application does not limit the processing mode of the acquired communication data by the second processor core, can determine the processing mode based on the communication requirement, can set the processing mode in advance, and processes the communication data based on the processing mode set in advance. Illustratively, the second processor core selects different processing modes according to the service type agreed in advance, wherein the processing modes comprise data digest value calculation, digital signature verification, function setting (on/off), service registration, key generation, data encryption, decryption and the like. For example, the communication data may be processed by checking a digital signature as a processing means set in advance.

In step 206, the second processor core writes the processed data into the shared memory, and writes the second shared memory address of the processed data in the shared memory into the preset common memory according to the preset communication protocol.

The processed data may be any data that can be transferred between two cores. The processed data may be generated by the second processor core, or may be transmitted to the second processor core by another core. Regardless of the manner in which the second processor core obtains the processed data, for the process that the second processor core communicates with the first processor core based on the processed data, the second processor core may store the processed data in a shared memory, and since the shared memory is a memory that can be commonly accessed by two cores, the two cores can implement inter-core communication based on the shared memory.

In the process of implementing inter-core communication based on the shared memory, in order to enable the first processor core to obtain the processed data from the shared memory, the second processor core may further determine an address of the processed data in the shared memory after storing the processed data in the shared memory, where the address may be referred to as a second shared memory address. In one possible implementation, the second processor core may store the second shared memory address in a different location than the shared memory, e.g., determining a common memory that is accessible to both the second processor core and the first processor core, writing the second shared memory address to the common memory. For example, the second shared memory address is written into the second interaction data according to a communication protocol of the second interaction data, and the second processor core writes the second interaction data into the common memory.

In one possible implementation, the common memory further stores second indication information corresponding to the processed data, where the second indication information is used to indicate whether the processed data is inter-core communication data. The embodiment of the application does not limit the mode of indicating whether the processed data is inter-core communication data by the second indicating information, and can indicate whether the processed data is inter-core communication data by different values of the second indicating information. For example, if the value of the second indication information is 00, it is used to indicate that the processed data is inter-core communication data, and if the value of the second indication information is 11, it is used to indicate that the processed data is not inter-core communication data. Alternatively, whether the processed data is inter-core communication data may also be indicated by whether the field in which the second indication information is located is empty. For example, if the field in which the second indication information is located is null, it is used to indicate that the processed data is inter-core communication data, and if the field in which the second indication information is located is non-null, it is used to indicate that the processed data is not inter-core communication data.

In one possible implementation manner, at least one of an identifier of the second processor core corresponding to the processed data and a size of the processed data is also stored in the common memory, or at least one of an identifier of the second processor core corresponding to the processed data and a size of the processed data and a second check code are also stored in the common memory; the second check code is a check code of second reference data in the public memory, the second check code is used for checking the correctness of the second reference data, and the second reference data is at least one data except the second check code, which corresponds to the processed data.

Illustratively, no verification is required if the data stored in the common memory does not contain the second check code; verification is required if the data stored in the common memory includes a second verification code. The first processor core obtains second reference data and a second check code from the public memory according to a second external interrupt signal; the first processor core obtains a verification result by performing verification calculation on bytes in the second reference data; and under the condition that the verification result accords with the second verification code, the verification is successful.

Illustratively, the identifier of the second processor core corresponding to the processed data, the second shared memory address and the second check code are stored in the common memory, and then the identifier of the second processor core corresponding to the processed data and the second shared memory address are checked; and if the identifier, the second shared memory address, the second indication information and the second check code of the second processor core corresponding to the processed data are stored in the common memory, checking the identifier, the second shared memory address and the second indication information of the second processor core corresponding to the processed data.

Illustratively, taking the checking mode of the second check as the exclusive-or check as an example, the second check code is a second exclusive-or value, and the public memory stores at least one of the identifier of the second processor core corresponding to the processed data, the size of the processed data and the second exclusive-or value in addition to the second shared memory address; the second exclusive-or value is an exclusive-or value of second reference data in the common memory, and the second exclusive-or value is used for checking the correctness of the second reference data, and the second reference data is at least two data except the second exclusive-or value, which correspond to the processed data.

And after acquiring the second exclusive-or value and at least one of the identifier of the second processor core corresponding to the processed data and the size of the processed data, which are stored in the public memory in addition to the second shared memory address, performing exclusive-or verification. And performing exclusive-or operation on the first byte and the second byte in the second interactive data to obtain a result, performing exclusive-or operation on the result and the next byte until all bytes except the second exclusive-or value are exclusive-or, and finally obtaining the result which is the same as the second exclusive-or value, wherein the exclusive-or check is successful.

The embodiment of the application does not limit the second shared memory address, the second indication information, the identifier of the second processor core corresponding to the processed data, the size of the processed data, the length of the second exclusive-or value and the storage sequence of each content in the common memory, and can be flexibly set based on scenes. The second shared memory address, the second indication information, the identifier of the second processor core corresponding to the processed data, the size of the processed data and the second exclusive-or value are stored in the common memory, the length of the second shared memory address is 4, the length of the second indication information is 2, the length of the identifier of the second processor core is 2, the length of the size of the processed data is 4, the size of the second exclusive-or value is 1, and the second shared memory address, the second indication information, the identifier of the second processor core corresponding to the processed data, the size of the processed data and the second exclusive-or value can be stored in the format of second interactive data. For example, the structure of the second interaction data may be as shown in table 2 below.

TABLE 2

In step 207, the second processor core sends a second external interrupt signal to the first processor core via the shared external interrupt source of the first processor core.

In one possible implementation, the shared external interrupt source of the first processor core may be an existing external interrupt source of the first processor core. For example, the second processor core sending a second external interrupt signal to the first processor core through a shared external interrupt source of the first processor core, comprising: determining an external interrupt source from the external interrupt sources of the first processor core as a shared external interrupt source of the first processor core; the shared external interrupt source triggering the first processor core sends a second external interrupt signal to the first processor core.

The embodiment of the application does not limit the external interrupt source of the first processor core, and can be any external interrupt source existing in the first processor core. Illustratively, the external interrupt source of the first processor core includes GPIO, UART, SPI, PWM, or the like. For example, the GPIO may be determined to be the shared external interrupt source of the first processor core.

And determining the shared external interrupt source in the existing external interrupt sources, so that the multiplexing of the external interrupt sources is realized. That is, under the condition that the external interrupt source can continuously trigger the original interrupt signal, the second external interrupt signal can be sent in the inter-core communication process.

The method of sending the second external interrupt signal to the first processor core by the second processor core through the shared external interrupt source of the first processor core is not limited, and any method capable of transmitting the second external interrupt signal may be used. Illustratively, the first processor core multiplexes the external interrupt sources by adding software code. And the second processor core writes the processed data into the public memory at a second shared memory address in the shared memory, and then invokes the bottom driving code to send a second external interrupt signal to the interrupt register of the first processor core. Wherein the interrupt register of the first processor core is a register storing and managing the second external interrupt signal. And after the first processor core receives the second external interrupt signal, calling an interrupt processing function to process. The multiplexing interrupt source is to add a part of codes into the interrupt processing function, and a step of judging is added, when the external interrupt source multiplexed by the first processor core is triggered, the first processor core takes out the second instruction information from the shared memory and judges whether the request is an inter-core communication request, if yes, the inter-core communication is carried out, otherwise, the processing is continued as the original interrupt signal.

In step 208, the first processor core receives the second external interrupt signal, and obtains a second shared memory address from the common memory according to the second external interrupt signal.

In one possible implementation, for the case where the second instruction information is also stored in the common memory described in step 206, after the first processor core receives the second external interrupt signal, the method further includes: acquiring second indication information from the public memory; in the case where it is determined that the processed data is inter-core communication data based on the second instruction information, an operation of acquiring a second shared memory address from the common memory based on the second external interrupt signal is performed.

For example, based on the table 2 in step 206, the first processor core may read the second indication information from the second interaction data. To indicate whether the processed data is inter-core communication data by a different value of the second indication information. For example, if the value of the second instruction information is 00, the first processor core determines that the processed data is inter-core communication data, and if the value of the second instruction information is 11, the first processor core determines that the processed data is not inter-core communication data. Optionally, taking as an example whether the processed data is inter-core communication data by whether a field in which the second indication information is located is empty, if the field in which the second indication information is located is empty, the first processor core determines that the processed data is inter-core communication data, and if the field in which the second indication information is located is not empty, the first processor core determines that the processed data is not inter-core communication data.

In another possible implementation manner, for the case that the second exclusive-or value and at least one of the identifier of the second processor core corresponding to the processed data and the size of the processed data are also stored in the common memory described in step 206, since the second exclusive-or value is an exclusive-or value of the second reference data in the common memory, and the second exclusive-or value is used to verify the correctness of the second reference data, the second reference data is at least two data corresponding to the processed data except for the second exclusive-or value. Thus, the first processor core may verify at least two data corresponding to the processed data other than the second exclusive-or value according to the exclusive-or value, and after the verification is passed, obtain the second shared memory address from the common memory.

In step 209, the first processor core obtains the processed data from the shared memory according to the second shared memory address.

And obtaining a second shared memory address from the first processor core, and obtaining processed data from the shared memory indicated by the second shared memory address according to the second shared memory address, thereby realizing the communication process between the second processor core and the first processor core. After the first processor core acquires the processed data, the method provided by the embodiment of the application can consider that the inter-core communication process is finished.

In summary, in the inter-core communication method of the multi-core chip provided by the embodiment of the application, the first processor core stores the communication data into the shared memory, and the first shared memory address of the communication data in the shared memory is stored into the common memory, and the interrupt trigger signal is transmitted by triggering the external interrupt source multiplexed by the other party, so that the second processor core can acquire the communication data, thereby realizing inter-core communication in a software mode without using hardware implementation, and reducing the hardware requirement.

Because the shared interrupt source is the multiplexing existing external interrupt source, the multiplexing operation is easy to realize by the existing external interrupt source, and the efficiency of inter-core communication is improved.

In addition, the processor with the core in the method provided by the embodiment of the application can be applied to the chip, and because all programs which can be operated by the chip under the whole architecture need to be operated in the chip verification work, the programs in hardware are also included in the programs, and because the requirement of the hardware is reduced, the programs which need to be operated by the chip under the whole architecture are reduced, the chip verification work is quickened, and the development period of the chip is quickened.

For ease of understanding, the method provided by the embodiment of the present application is illustrated by taking the scenario shown in fig. 3 as an example. As shown in fig. 3, the first processor core is a 64-bit riscv core (fifth generation reduced instruction set core), the second processor core is a 32-bit riscv core (fifth generation reduced instruction set core), and the inter-core communication process between the first processor core and the second processor core includes the following steps 1-8. Wherein, the implementation manner of step 1 may refer to the related description of step 201, the implementation manner of step 2 may refer to the related description of step 202, the implementation manner of step 3 may refer to the related description of step 203, the implementation manner of step 4 may refer to the related description of step 204, the implementation manner of step 5 may refer to the related descriptions of steps 205 and 206, the implementation manner of step 6 may refer to the related description of step 207, the implementation manner of step 7 may refer to the related description of step 208, and the implementation manner of step 8 may refer to the related description of step 209, which will not be repeated herein.

Referring to fig. 4, an embodiment of the present application provides a multi-core chip, including: a multi-core chip 401, a processor 402, a first processor core 403, and a second processor core 404.

The first processor core 403 is configured to store communication data in the shared memory, and write a first shared memory address of the communication data in the shared memory into a preset common memory according to a preset communication protocol;

a first processor core 403 for sending a first external interrupt signal to the second processor core 404 via the shared external interrupt source of the second processor core 404;

the second processor core 404 is configured to receive a first external interrupt signal, and the second processor core 404 obtains a first shared memory address from the common memory according to the first external interrupt signal; and acquiring communication data from the shared memory according to the first shared memory address.

In a possible implementation manner, the public memory further stores first indication information corresponding to the communication data, where the first indication information is used to indicate whether the communication data is inter-core communication data; after the second processor core 404 receives the first external interrupt signal, the second processor core 404 is further configured to obtain the first indication information from the common memory.

In the case where the second processor core 404 determines that the communication data is data of inter-core communication according to the first instruction information, the second processor core 404 performs an operation of acquiring the first shared memory address from the common memory according to the first external interrupt signal.

In the case where the second processor core 404 determines that the communication data is not the data of inter-core communication according to the first instruction information, the second processor core 404 performs an interrupt processing operation corresponding to the first external interrupt signal.

In a possible implementation manner, at least one of an identifier of the first processor core 403 corresponding to the communication data and a size of the communication data is also stored in the common memory, or at least one of an identifier of the first processor core 403 corresponding to the communication data and a size of the communication data and a first check code are also stored in the common memory; the first check code is a check code of first reference data in the public memory, the first check code is used for checking the correctness of the first reference data, and the first reference data is at least one data except the first check code, which corresponds to the communication data.

In the case that the first check code is also stored in the common memory, before the second processor core 404 obtains the first shared memory address from the common memory according to the first external interrupt signal, the second processor core 404 is configured to obtain the first reference data and the first check code from the common memory according to the first external interrupt signal; a second processor core 404, configured to obtain a verification result by performing a verification calculation on bytes in the first reference data; and under the condition that the verification result accords with the first verification code, the verification is successful.

In one possible implementation, one external interrupt source is determined from the external interrupt sources of the second processor core 404 as a shared external interrupt source of the second processor core 404; the first processor core 403 is configured to trigger the shared external interrupt source of the second processor core 404 to send a first external interrupt signal to the second processor core 404.

In one possible implementation, the first processor core 403 is configured to call the underlying driver code of the multi-core chip and send a first external interrupt signal to the interrupt register of the second processor core 404.

In one possible implementation, the external interrupt source of the second processor core includes: general purpose input/output GPIO, universal asynchronous receiver/transmitter UART, serial peripheral interface SPI, or pulse width modulation PWM.

It should be noted that, when the chip provided in the above embodiment performs its functions, the above functions may be distributed to be performed by different entities, that is, the chip may be formed by different entities, so as to perform all or part of the functions described above. In addition, the chip and the method embodiments provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the chip and the method embodiments are detailed in the method embodiments and are not repeated herein.

Fig. 5 is a schematic structural diagram of a server according to an embodiment of the present application, where the server may have a relatively large difference due to different configurations or performances, and may include one or more processors 1101 and one or more memories 1102, where the one or more memories 1102 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 1101, so that the server implements the inter-core communication method of the multi-core chip provided by the foregoing method embodiments. Of course, the server may also have a wired or wireless network interface, a keyboard, an input/output interface, and other components for implementing the functions of the device, which are not described herein.

Fig. 6 is a schematic structural diagram of a terminal according to an embodiment of the present application. The terminal may be, for example: smart phones, tablet computers, players, notebook computers or desktop computers. Terminals may also be referred to by other names as user equipment, portable terminals, laptop terminals, desktop terminals, etc.

Generally, the terminal includes: a processor 1501 and a memory 1502.

The processor 1501 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like. The processor 1501 may be implemented in at least one hardware form of DSP (Digital Signal Processing ), FPGA (Field-Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array ). The processor 1501 may also include a main processor, which is a processor for processing data in an awake state, also called a CPU (Central Processing Unit ), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1501 may be integrated with a GPU (Graphics Processing Unit, image processor) for taking care of rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 1501 may also include an AI (Artificial Intelligence ) processor for processing computing operations related to machine learning.

Memory 1502 may include one or more computer-readable storage media, which may be non-transitory. Memory 1502 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 1502 is configured to store at least one instruction for execution by processor 1501 to cause the terminal to implement an inter-core communication method of a multi-core chip provided by an embodiment of a method in the present application.

In some embodiments, the terminal may further optionally include: a peripheral interface 1503 and at least one peripheral device. The processor 1501, memory 1502 and peripheral interface 1503 may be connected by a bus or signal lines. The individual peripheral devices may be connected to the peripheral device interface 1503 via a bus, signal lines, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 1504, a display 1505, a camera assembly 1506, audio circuitry 1507, and a power supply 1509.

A peripheral interface 1503 may be used to connect I/O (Input/Output) related at least one peripheral device to the processor 1501 and the memory 1502. In some embodiments, processor 1501, memory 1502, and peripheral interface 1503 are integrated on the same chip or circuit board; in some other embodiments, either or both of the processor 1501, the memory 1502, and the peripheral interface 1503 may be implemented on separate chips or circuit boards, which is not limited in this embodiment.

The Radio Frequency circuit 1504 is configured to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 1504 communicates with a communication network and other communication devices via electromagnetic signals. The radio frequency circuit 1504 converts an electrical signal into an electromagnetic signal for transmission, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 1504 includes: antenna systems, RF transceivers, one or more amplifiers, tuners, oscillators, digital signal processors, codec chipsets, subscriber identity module cards, and so forth. The radio frequency circuit 1504 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: metropolitan area networks, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and/or WiFi (Wireless Fidelity ) networks. In some embodiments, the radio frequency circuit 1504 may also include NFC (Near Field Communication, short range wireless communication) related circuits, which the present application is not limited to.

Display 1505 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When display screen 1505 is a touch display screen, display screen 1505 also has the ability to collect touch signals at or above the surface of display screen 1505. The touch signal may be input to the processor 1501 as a control signal for processing. At this point, display 1505 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments, the display 1505 may be one, disposed on the front panel of the terminal; in other embodiments, the display 1505 may be at least two, respectively disposed on different surfaces of the terminal or in a folded design; in other embodiments, the display 1505 may be a flexible display disposed on a curved surface or a folded surface of the terminal. Even more, the display 1505 may be arranged in a non-rectangular irregular pattern, i.e., a shaped screen. The display screen 1505 may be made of LCD (Liquid Crystal Display ), OLED (Organic Light-Emitting Diode) or other materials.

The camera assembly 1506 is used to capture images or video. Optionally, the camera assembly 1506 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal and the rear camera is disposed on the rear surface of the terminal. In some embodiments, the at least two rear cameras are any one of a main camera, a depth camera, a wide-angle camera and a tele camera, so as to realize that the main camera and the depth camera are fused to realize a background blurring function, and the main camera and the wide-angle camera are fused to realize a panoramic shooting and Virtual Reality (VR) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1506 may also include a flash. The flash lamp can be a single-color temperature flash lamp or a double-color temperature flash lamp. The dual-color temperature flash lamp refers to a combination of a warm light flash lamp and a cold light flash lamp, and can be used for light compensation under different color temperatures.

The audio circuitry 1507 may include a microphone and a speaker. The microphone is used for collecting sound waves of users and the environment, converting the sound waves into electric signals, inputting the electric signals to the processor 1501 for processing, or inputting the electric signals to the radio frequency circuit 1504 for voice communication. For the purpose of stereo acquisition or noise reduction, a plurality of microphones can be respectively arranged at different parts of the terminal. The microphone may also be an array microphone or an omni-directional pickup microphone. The speaker is used to convert electrical signals from the processor 1501 or the radio frequency circuit 1504 into sound waves. The speaker may be a conventional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, not only the electric signal can be converted into a sound wave audible to humans, but also the electric signal can be converted into a sound wave inaudible to humans for ranging and other purposes. In some embodiments, the audio circuit 1507 may also include a headphone jack.

The power supply 1508 is used to power the various components in the terminal. The power source 1508 may be alternating current, direct current, disposable battery, or rechargeable battery. When the power source 1508 includes a rechargeable battery, the rechargeable battery may support wired or wireless charging. The rechargeable battery may also be used to support fast charge technology.

In some embodiments, the terminal further includes one or more sensors 1509. The one or more sensors 1509 include, but are not limited to: acceleration sensor 1510, gyro sensor 1511, pressure sensor 1512, optical sensor 1513, and proximity sensor 1514.

The acceleration sensor 1510 may detect the magnitudes of accelerations on three coordinate axes of a coordinate system established with a terminal. For example, the acceleration sensor 1510 may be used to detect components of gravitational acceleration in three coordinate axes. The processor 1501 may control the display screen 1505 to display the user interface in either a landscape view or a portrait view based on the gravitational acceleration signal collected by the acceleration sensor 1510. The acceleration sensor 1510 may also be used for acquisition of motion data of a game or user.

The gyro sensor 1511 may detect a body direction and a rotation angle of the terminal, and the gyro sensor 1511 may collect a 3D motion of the user to the terminal in cooperation with the acceleration sensor 1510. The processor 1501, based on the data collected by the gyro sensor 1511, may implement the following functions: motion sensing (e.g., changing UI according to a tilting operation by a user), image stabilization at shooting, game control, and inertial navigation.

The pressure sensor 1512 may be disposed on a side frame of the terminal and/or below the display 1505. When the pressure sensor 1512 is disposed on the side frame of the terminal, a holding signal of the terminal by the user can be detected, and the processor 1501 performs left-right hand recognition or quick operation according to the holding signal collected by the pressure sensor 1513. When the pressure sensor 1513 is disposed at the lower layer of the display screen 1505, the processor 1501 realizes control of the operability control on the UI interface according to the pressure operation of the user on the display screen 1505. The operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

The optical sensor 1513 is used to collect the ambient light intensity. In one embodiment, processor 1501 may control the display brightness of display screen 1505 based on the intensity of ambient light collected by optical sensor 1513. Specifically, when the ambient light intensity is high, the display brightness of the display screen 1505 is turned up; when the ambient light intensity is low, the display luminance of the display screen 1505 is turned down. In another embodiment, the processor 1501 may also dynamically adjust the shooting parameters of the camera assembly 1506 based on the ambient light intensity collected by the optical sensor 1513.

A proximity sensor 1514, also referred to as a distance sensor, is typically provided on the front panel of the terminal. The proximity sensor 1514 is used to collect the distance between the user and the front face of the terminal. In one embodiment, when the proximity sensor 1514 detects a gradual decrease in the distance between the user and the front face of the terminal, the processor 1501 controls the display 1505 to switch from the on-screen state to the off-screen state; when the proximity sensor 1514 detects that the distance between the user and the front face of the terminal gradually increases, the processor 1501 controls the display screen 1505 to switch from the off-screen state to the on-screen state.

It will be appreciated by those skilled in the art that the structure shown in fig. 6 is not limiting of the terminal and may include more or fewer components than shown, or may combine certain components, or may employ a different arrangement of components.

In an exemplary embodiment, a computer device is also provided, the computer device comprising a processor and a memory, the memory having at least one computer program stored therein. The at least one computer program is loaded and executed by one or more processors to cause the computer apparatus to implement any of the methods of inter-core communication for a multi-core chip described above.

In an exemplary embodiment, there is also provided a computer-readable storage medium having stored therein at least one computer program loaded and executed by a processor of a computer device to cause the computer to implement an inter-core communication method of any of the above-described multi-core chips.

In one possible implementation, the computer readable storage medium may be a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), a compact disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

In an exemplary embodiment, a computer program product or a computer program is also provided, the computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform any of the inter-core communication methods of the multi-core chip described above.

It should be noted that, the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, presented data, etc.), and signals related to the present application are all authorized by the user or are fully authorized by the parties, and the collection, use, and processing of the related data is required to comply with the relevant laws and regulations and standards of the relevant countries and regions. For example, the inter-core communication information of the multi-core chip related to the application is acquired under the condition of full authorization.

It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The above embodiments are merely exemplary embodiments of the present application and are not intended to limit the present application, any modifications, equivalent substitutions, improvements, etc. that fall within the principles of the present application should be included in the scope of the present application.

Claims

1. A method of inter-core communication for a multi-core chip, the method comprising:

2. The method of claim 1, wherein the common memory further stores first indication information corresponding to the communication data, the first indication information being used to indicate whether the communication data is inter-core communication data; after the second processor core receives the first external interrupt signal, the method further includes:

the second processor core acquires the first indication information from the public memory;

and under the condition that the second processor core determines that the communication data is inter-core communication data according to the first indication information, the second processor core executes the operation of acquiring the first shared memory address from the public memory according to the first external interrupt signal.

3. The method of claim 1, wherein the common memory further stores first indication information corresponding to the communication data, the first indication information being used to indicate whether the communication data is inter-core communication data; after the second processor core receives the first external interrupt signal, the method further includes:

And under the condition that the second processor core determines that the communication data is not inter-core communication data according to the first indication information, the second processor core executes interrupt processing operation corresponding to the first external interrupt signal.

4. The method of claim 1, wherein the common memory further stores at least one of an identification of the first processor core corresponding to the communication data and a size of the communication data, or wherein the common memory further stores at least one of an identification of the first processor core corresponding to the communication data and a size of the communication data and a first check code;

the first check code is a check code of first reference data in the public memory, and the first check code is used for checking the correctness of the first reference data, and the first reference data is at least one data except the first check code, which corresponds to the communication data;

in the case that the first check code is also stored in the common memory, before the second processor core obtains the first shared memory address from the common memory according to the first external interrupt signal, the method further includes:

The second processor core acquires the first reference data and the first check code from the public memory according to the first external interrupt signal;

the second processor core obtains the verification result by performing verification calculation on bytes in the first reference data;

and under the condition that the verification result accords with the first verification code, the verification is successful.

5. The method of any of claims 1-4, wherein the first processor core sending a first external interrupt signal to a second processor core through a shared external interrupt source of the second processor core, comprising:

determining an external interrupt source from the external interrupt sources of the second processor core as a shared external interrupt source of the second processor core;

the first processor core triggers a shared external interrupt source of the second processor core to send the first external interrupt signal to the second processor core.

6. The method of claim 5, wherein the first processor core triggering the shared external interrupt source of the second processor core to send the first external interrupt signal to the second processor core comprises:

And the first processor core calls a bottom layer driving code of the multi-core chip and sends the first external interrupt signal to an interrupt register of the second processor core.

7. The method of any of claims 1-6, wherein the external interrupt source of the second processor core comprises: general purpose input/output GPIO, universal asynchronous receiver/transmitter UART, serial peripheral interface SPI, or pulse width modulation PWM.

8. A multi-core chip comprising a first processor core for performing the functions of the first processor core in the method of any one of claims 1-7 and a second processor core for performing the functions of the second processor core in the method of any one of claims 1-7.

9. A computer device, characterized in that it comprises a processor and a memory, in which at least one computer program is stored, which is loaded and executed by the processor, so that the computer device implements the inter-core communication method of the multi-core chip according to any of claims 1 to 7.

10. A computer-readable storage medium, wherein at least one computer program is stored in the computer-readable storage medium, the at least one computer program being loaded and executed by a processor to cause a computer to implement the method of inter-core communication of a multi-core chip according to any one of claims 1 to 7.