CN117215686A - Cross cursor display system and method - Google Patents
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- CN117215686A CN117215686A CN202311021789.4A CN202311021789A CN117215686A CN 117215686 A CN117215686 A CN 117215686A CN 202311021789 A CN202311021789 A CN 202311021789A CN 117215686 A CN117215686 A CN 117215686A
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Abstract
The invention relates to a cross cursor display system and a method, wherein the system comprises the following steps: the row counting module is used for counting the pixel clock signals when the row synchronizing signals are valid; the field counting module is used for counting the row synchronous signals when the field synchronous signals are valid; the cursor X coordinate module is used for storing X coordinate values; the cursor Y coordinate module is used for storing Y coordinate values; the comparison module is used for comparing the pixel clock signal count value, the X coordinate value, the row synchronous signal count value and the Y coordinate value and outputting a selection signal; the selection module is used for selecting and outputting video signals or cross cursor signals under the action of the selection signals; and the synthesis module is used for fusing the line synchronous signal and the field synchronous signal with the video signal or the cross cursor signal. The invention is realized based on FPGA logic, does not need memory overhead, occupies less resources, has simple logic, is easy to realize, reduces the design complexity of the display system and saves the cost.
Description
Technical Field
The invention relates to the field of video display, in particular to a cross cursor display system and a cross cursor display method.
Background
In a radar display control system, a cross cursor needs to be displayed for target recording and target indication. At present, the method is mainly realized by adopting graphic acceleration software or a cursor layer superposition mode. The graphic acceleration software has higher requirements on the software and hardware configuration of the computer; the mode of overlapping the cursor layers realizes cross cursor display, requires extra memory expenditure, and requires complex programming, and has difficulty in development.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: cross cursor display requires high demands on computer software and hardware configuration or requires additional memory overhead, and has complex programming and large development difficulty.
The technical scheme for solving the technical problems is as follows: a cross cursor display system comprising the following modules:
the line counting module is used for inputting a line synchronizing signal and a pixel clock signal, and counting the pixel clock signal under the condition that the line synchronizing signal is valid to obtain a pixel clock signal count value;
the field counting module is used for inputting a field synchronizing signal and the line synchronizing signal, and counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value;
a cursor X coordinate module for storing the X coordinate value of the set cross cursor;
a cursor Y coordinate module for storing the Y coordinate value of the set cross cursor;
a comparison module for comparing the pixel clock signal count value, the X-coordinate value, the row synchronization signal count value, and the Y-coordinate value, and outputting a valid or invalid selection signal;
the selection module is used for inputting a video signal and a cross cursor signal and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
and the synthesis module is used for inputting the row synchronous signal and the field synchronous signal, fusing the row synchronous signal and the field synchronous signal with the video signal or the cross cursor signal selected and output by the selection module, and outputting a synthesis signal.
Based on the cross cursor display system, the invention also provides a cross cursor display method.
A cross cursor display method is applied to the cross cursor display system, and comprises the following steps:
s1, inputting a row synchronizing signal and a pixel clock signal, and counting the pixel clock signal under the condition that the row synchronizing signal is effective to obtain a pixel clock signal count value;
s2, inputting a field synchronizing signal and the line synchronizing signal, and counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value;
s3, setting an X coordinate value and a Y coordinate value of a cross cursor;
s4, comparing the pixel clock signal count value, the X coordinate value, the row synchronous signal count value and the Y coordinate value, and outputting an effective or ineffective selection signal;
s5, inputting a video signal and a cross cursor signal, and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
s6, inputting the line synchronization signal and the field synchronization signal, fusing the line synchronization signal and the field synchronization signal with the video signal or the cross cursor signal which are selected to be output, and outputting a synthesized signal.
The beneficial effects of the invention are as follows: in the cross cursor display system and the method, the cross cursor display system and the method are realized based on FPGA logic; the FPGA logic comprises a row counting module, a field counting module, a cursor X-coordinate module, a cursor Y-coordinate module, a comparison module, a selection module and the like, and has the characteristics of simple structure and good universality; specifically, the row counting module, the field counting module, the cursor X coordinate module, the cursor Y coordinate module and the comparison module are connected to realize the cross cursor position comparison function, the output control selection module of the comparison module outputs video signals and signals of the cross cursor as composite signals, and the display function of the cross cursor is realized by combining the input row synchronization and field synchronization signals; the invention does not need memory expenditure, occupies less resources, has simple logic, is easy to realize, reduces the design complexity of the display system and saves the cost.
Drawings
FIG. 1 is a block diagram of a cross cursor display system according to the present invention;
fig. 2 is a flowchart of a cross cursor display method according to the present invention.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in fig. 1, a cross cursor display system includes the following modules:
the row counting module is used for inputting a row synchronizing signal H and a pixel clock signal CLK, and counting the pixel clock signal CLK under the condition that the row synchronizing signal H is valid to obtain a pixel clock signal count value;
the field counting module is used for inputting a field synchronizing signal V and the line synchronizing signal H, and counting the line synchronizing signal H under the condition that the field synchronizing signal V is effective to obtain a line synchronizing signal count value;
a cursor X coordinate module for storing the X coordinate value of the set cross cursor;
a cursor Y coordinate module for storing the Y coordinate value of the set cross cursor;
a comparison module for comparing the pixel clock signal count value, the X-coordinate value, the row synchronization signal count value, and the Y-coordinate value, and outputting a valid or invalid selection signal;
the selection module is used for inputting a video signal and a cross cursor signal and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
and the synthesis module is used for inputting the row synchronous signal and the field synchronous signal, fusing the row synchronous signal and the field synchronous signal with the video signal or the cross cursor signal selected and output by the selection module, and outputting a synthesis signal RGBHV.
In this particular embodiment: the row counting module comprises a first multi-bit counter and a row counting register; the first multi-bit counter is used for counting the pixel clock signal CLK under the condition that the row synchronous signal H is valid to obtain a pixel clock signal count value; the row count register is used for storing the pixel clock signal count value.
Specifically, the first multi-bit counter may be a 12-bit counter. In the line counting module, after the line synchronization signal H is valid, an input pixel clock signal CLK is counted by a 12-bit counter, and the pixel clock signal count value is stored in a line count register.
In this particular embodiment: the field counting module comprises a second multi-bit counter and a field counting register; the field counting module is used for counting the row synchronizing signal H under the condition that the field synchronizing signal V is effective to obtain a row synchronizing signal count value; the field counting register is used for storing the row synchronizing signal counting value; the pixel clock signal CLK is also input into the field count register, and the pixel clock signal CLK is used for synchronously latching the field count register.
In particular, the second multi-bit counter may be a 12-bit counter. In the field counting module, an input row synchronization signal H is counted after a field synchronization signal V is valid by a 12-bit counter, and a row synchronization signal count value is stored in a field count register.
In this particular embodiment: the cursor X coordinate module comprises a first multi-bit register, wherein the X coordinate value is stored in the first multi-bit register, the first multi-bit register is also input with the pixel clock signal, and the pixel clock signal is used for synchronously latching the first multi-bit register.
Specifically, the first multi-bit register may be a 12-bit register. In the cursor X coordinate module, a 12-bit register is set, the cross cursor X coordinate set by the host program is stored, and the first multi-bit register is synchronously latched by the pixel clock signal CLK.
In this particular embodiment: the cursor Y coordinate module comprises a second multi-bit register, wherein the Y coordinate value is stored in the second multi-bit register, the pixel clock signal is also input into the second multi-bit register, and the pixel clock signal is used for synchronously latching the second multi-bit register.
In particular, the second multi-bit register may be a 12-bit register. In the cursor Y coordinate module, a 12-bit register is set, the cross cursor Y coordinate set by the host program is stored, and the second multi-bit register is synchronously latched by the pixel clock signal CLK.
In this specific embodiment, the comparison module is specifically configured to: comparing the pixel clock signal count value with the X coordinate value to obtain a first comparison result, comparing the row synchronizing signal count value with the Y coordinate value to obtain a second comparison result, and outputting an effective selection signal if the first comparison result and the second comparison result are in the range of the horizontal line, the central point and the vertical line of the cross cursor, or outputting an ineffective selection signal if the first comparison result and the second comparison result are not in the range of the horizontal line, the central point and the vertical line of the cross cursor.
Wherein comparing the pixel clock signal count value with the X coordinate value is specifically: subtracting the line starting quantity calculated according to the display resolution from the pixel clock signal count value to obtain a first difference value; and comparing the first difference value with the X coordinate value (namely performing difference processing) to obtain the first comparison result.
Wherein comparing the row synchronization signal count value with the Y coordinate value specifically includes: subtracting the field starting quantity calculated according to the display resolution from the line synchronizing signal count value to obtain a second difference value; and comparing the second difference value with the Y coordinate value (namely performing difference processing) to obtain a second comparison result.
The pixel clock signal is also input into the comparison module and is used for synchronously latching the output of the comparison module.
In this specific embodiment, the selection module is specifically configured to: and outputting the video signal when the selection signal is invalid, and outputting the cross cursor signal when the selection signal is valid.
Specifically, the video signal and the cross cursor signal are both RGB data. The pixel clock signal is also input into the selection module and is used for synchronously latching the output of the selection module.
In this embodiment, the synthesis module forms the output of the selection module, the row synchronization signal H and the field synchronization signal V into a synthesis signal RGBHV, and drives the external VGA display device.
Based on the cross cursor display system, the invention also provides a cross cursor display method.
A cross cursor display method is applied to the cross cursor display system, and comprises the following steps:
s1, inputting a row synchronizing signal and a pixel clock signal, and counting the pixel clock signal under the condition that the row synchronizing signal is effective to obtain a pixel clock signal count value;
s2, inputting a field synchronizing signal and the line synchronizing signal, and counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value;
s3, setting an X coordinate value and a Y coordinate value of a cross cursor;
s4, comparing the pixel clock signal count value, the X coordinate value, the row synchronous signal count value and the Y coordinate value, and outputting an effective or ineffective selection signal;
s5, inputting a video signal and a cross cursor signal, and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
s6, inputting the line synchronization signal and the field synchronization signal, fusing the line synchronization signal and the field synchronization signal with the video signal or the cross cursor signal which are selected to be output, and outputting a synthesized signal.
In the cross cursor display system and the method, the cross cursor display system and the method are realized based on FPGA logic; the FPGA logic comprises a row counting module, a field counting module, a cursor X-coordinate module, a cursor Y-coordinate module, a comparison module, a selection module and the like, and has the characteristics of simple structure and good universality; specifically, the row counting module, the field counting module, the cursor X coordinate module, the cursor Y coordinate module and the comparison module are connected to realize the cross cursor position comparison function, the output control selection module of the comparison module outputs video signals and signals of the cross cursor as composite signals, and the display function of the cross cursor is realized by combining the input row synchronization and field synchronization signals; the invention does not need memory expenditure, occupies less resources, has simple logic, is easy to realize, reduces the design complexity of the display system and saves the cost.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A cross cursor display system, comprising the following modules:
the line counting module is used for inputting a line synchronizing signal and a pixel clock signal, and counting the pixel clock signal under the condition that the line synchronizing signal is valid to obtain a pixel clock signal count value;
the field counting module is used for inputting a field synchronizing signal and the line synchronizing signal, and counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value;
a cursor X coordinate module for storing the X coordinate value of the set cross cursor;
a cursor Y coordinate module for storing the Y coordinate value of the set cross cursor;
a comparison module for comparing the pixel clock signal count value, the X-coordinate value, the row synchronization signal count value, and the Y-coordinate value, and outputting a valid or invalid selection signal;
the selection module is used for inputting a video signal and a cross cursor signal and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
and the synthesis module is used for inputting the row synchronous signal and the field synchronous signal, fusing the row synchronous signal and the field synchronous signal with the video signal or the cross cursor signal selected and output by the selection module, and outputting a synthesis signal.
2. The cross cursor display system of claim 1, wherein the comparison module is specifically configured to: comparing the pixel clock signal count value with the X coordinate value to obtain a first comparison result, comparing the row synchronizing signal count value with the Y coordinate value to obtain a second comparison result, and outputting an effective selection signal if the first comparison result and the second comparison result are in the range of the horizontal line, the central point and the vertical line of the cross cursor, or outputting an ineffective selection signal if the first comparison result and the second comparison result are not in the range of the horizontal line, the central point and the vertical line of the cross cursor.
3. The cross cursor display system of claim 2, wherein comparing the pixel clock signal count value with the X coordinate value is specifically:
subtracting the line starting quantity calculated according to the display resolution from the pixel clock signal count value to obtain a first difference value;
and comparing the first difference value with the X coordinate value to obtain the first comparison result.
4. The cross cursor display system of claim 2, wherein comparing the row synchronization signal count value with the Y coordinate value is specifically:
subtracting the field starting quantity calculated according to the display resolution from the line synchronizing signal count value to obtain a second difference value;
and comparing the second difference value with the Y coordinate value to obtain the second comparison result.
5. The cross cursor display system of claim 1, wherein the selection module is specifically configured to: and outputting the video signal when the selection signal is invalid, and outputting the cross cursor signal when the selection signal is valid.
6. The cross cursor display system of any one of claims 1 to 5, wherein the row count module comprises a first multi-bit counter and a row count register; the first multi-bit counter is used for counting the pixel clock signals under the condition that the row synchronous signals are valid to obtain pixel clock signal count values; the row counting register is used for storing the pixel clock signal count value;
the field counting module comprises a second multi-bit counter and a field counting register; the field counting module is used for counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value; the field counting register is used for storing the row synchronizing signal counting value; the pixel clock signal is also input into the field counting register and is used for synchronously latching the field counting register.
7. The cross cursor display system of any one of claims 1 to 5, wherein the cursor X-coordinate module comprises a first multi-bit register in which the X-coordinate value is stored, the first multi-bit register further having the pixel clock signal input therein, the pixel clock signal being used to synchronously latch the first multi-bit register;
the cursor Y coordinate module comprises a second multi-bit register, wherein the Y coordinate value is stored in the second multi-bit register, the pixel clock signal is also input into the second multi-bit register, and the pixel clock signal is used for synchronously latching the second multi-bit register.
8. The cross cursor display system of any one of claims 1 to 5, wherein the pixel clock signal is further input to the comparison module, and the pixel clock signal is used to synchronously latch the output of the comparison module.
9. The cross cursor display system of any one of claims 1 to 5, wherein the pixel clock signal is further input to the selection module, and the pixel clock signal is used to synchronously latch the output of the selection module.
10. A cross cursor display method, characterized in that it is applied to the cross cursor display system according to any one of claims 1 to 9, comprising the steps of:
s1, inputting a row synchronizing signal and a pixel clock signal, and counting the pixel clock signal under the condition that the row synchronizing signal is effective to obtain a pixel clock signal count value;
s2, inputting a field synchronizing signal and the line synchronizing signal, and counting the line synchronizing signal under the condition that the field synchronizing signal is effective to obtain a line synchronizing signal count value;
s3, setting an X coordinate value and a Y coordinate value of a cross cursor;
s4, comparing the pixel clock signal count value, the X coordinate value, the row synchronous signal count value and the Y coordinate value, and outputting an effective or ineffective selection signal;
s5, inputting a video signal and a cross cursor signal, and selecting and outputting the video signal or the cross cursor signal under the action of the selection signal;
s6, inputting the line synchronization signal and the field synchronization signal, fusing the line synchronization signal and the field synchronization signal with the video signal or the cross cursor signal which are selected to be output, and outputting a synthesized signal.
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