CN117202696A - Display substrate and display panel - Google Patents

Abstract

The application discloses a display substrate and a display panel, wherein the display substrate comprises a plurality of pixel units which are arranged in an array, and the pixel units are mutually cascaded; the pixel units of each stage are provided with semiconductor layers which are arranged in a pattern; the semiconductor layer of the pixel unit of the present stage comprises a semiconductor main body part and a semiconductor connecting part which extends to the semiconductor layer of the pixel unit of the previous stage or the next stage and is connected with the semiconductor layer of the pixel unit of the previous stage; and a first metal pattern serving as a grid electrode is arranged on the surface of the semiconductor layer at a position corresponding to the semiconductor connecting part, a blocking transistor is formed by the first metal pattern and the semiconductor connecting part, and the two ends of the semiconductor connecting part are electrically blocked by controlling the grid electrode of the blocking transistor. Through the structure, the EDS problem is avoided.

Description

Display substrate and display panel

Technical Field

The present application relates to the field of transparent display, and in particular, to a display substrate and a display panel.

Background

With the development of an OLED (organic light emitting diode) in a display panel, currently, LTPS-AMOLED (low temperature polysilicon technology-active matrix organic light emitting diode) has emerged in a dual-reference wiring design, and the dual-reference wiring design can greatly improve the performance of a product. The dual reference trace design optimizes a conventional single Vref (reference) trace into two independent Vref traces, one of which is responsible for initializing the pixel capacitance and the other of which is responsible for initializing the OLED device.

In a dual-net Vref design to ensure proper Vref operation, the polysilicon must be broken in the vertical direction and if the polysilicon is extended in the lateral direction it will cause the environment of the G pixels to be inconsistent, resulting in display Mura. Therefore, the polysilicon in the dual net Vref design must break both laterally and longitudinally, i.e., the polysilicon must be designed independently.

Through mass production practice, under the independent design of the double-net Vref, the tail end (tip) of Si is extremely easy to absorb static electricity in the process, and finally, static Electricity (ESD) damage is generated to the adjacent TFT at the tail end of Si, so that a TFT device is invalid.

Disclosure of Invention

The application mainly solves the technical problem of providing a display panel and a manufacturing method thereof, so as to avoid the ESD problem caused by independent Si design of double-net Vref under conventional pixel arrangement.

In order to solve the above problems, a first aspect of the present application provides a display substrate, where the display substrate includes a plurality of pixel units arranged in an array, and the plurality of pixel units are cascaded with each other; the pixel units of each stage are provided with semiconductor layers which are arranged in a pattern; the semiconductor layer of the pixel unit of the present stage comprises a semiconductor main body part and a semiconductor connecting part which extends to the semiconductor layer of the pixel unit of the previous stage or the next stage and is connected with the semiconductor layer of the pixel unit of the previous stage; and a first metal pattern serving as a grid electrode is arranged on the surface of the semiconductor layer at a position corresponding to the semiconductor connecting part, a blocking transistor is formed by the first metal pattern and the semiconductor connecting part, and the two ends of the semiconductor connecting part are electrically blocked by controlling the grid electrode of the blocking transistor.

The semiconductor main body part of the pixel unit at the current stage comprises a first extension part extending to the semiconductor layer of the pixel unit at the previous stage and a second extension part extending to the semiconductor layer of the pixel unit at the next stage, wherein the extension directions of the first extension part and the second extension part are opposite.

The first extension part is in an inverted S-shaped arrangement, and the second extension part is in an L-shaped arrangement; the first extension part of the pixel unit of the current stage extends to the second extension part of the pixel unit of the previous stage and is connected with the second extension part to form the semiconductor connection part; or, the second extension part of the pixel unit at the current stage extends to the first extension part of the pixel unit at the next stage and is connected to form the semiconductor connection part.

The semiconductor main body part further comprises a first main body part which is arranged in an H shape, and the first extension part and the second extension part are arranged on the same side of the first main body part which is arranged in the H shape, so that the semiconductor connecting parts are correspondingly arranged.

The display substrate is also provided with a second metal pattern and a third metal pattern; the second metal pattern is a linear metal pattern arranged at a position corresponding to the semiconductor main body part; the third metal pattern is a block-shaped metal pattern provided at an intermediate position of the semiconductor body portion; the second metal pattern and the third metal pattern are located on the same layer with the first metal pattern and are arranged at intervals.

Wherein the second metal pattern includes a plurality of lines, and the second metal pattern and the semiconductor layer form a plurality of transistors; the first transistor in the pixel unit of the current stage and the second transistor in the pixel unit of the previous stage or the next stage share one second metal pattern, so that the first transistor in the pixel unit of the current stage and the second transistor in the pixel unit of the previous stage or the next stage are simultaneously conducted.

The isolation transistor is arranged between the first transistor and the second transistor, so that the first transistor and the second transistor are conducted simultaneously and are not interfered with each other.

The first metal pattern, the second metal pattern and the third metal pattern are first-layer metal patterns, the second-layer metal patterns are further arranged on the surfaces of the first-layer metal patterns, and the second-layer metal patterns comprise fourth metal patterns for transmitting blocking voltage; the fourth metal pattern is connected with the first metal pattern through a via hole, and transmits a blocking voltage to the first metal pattern through the via hole so as to control the blocking transistor to be in a normally-off state, so that two ends of the semiconductor connecting part are electrically blocked.

The surface of the first metal pattern is provided with a fourth metal pattern for transmitting the blocking voltage, the surface of the fourth metal pattern is also provided with a fifth metal pattern which is longitudinally distributed, the fifth metal pattern is respectively connected with the first metal pattern and the fourth metal pattern through the through holes, the blocking voltage of the fourth metal pattern is transmitted to the fifth metal pattern through the through holes, and the fifth metal pattern is transmitted to the first metal pattern through another through hole, so that the blocking voltage is transmitted to the grid electrode of the blocking transistor, and the blocking transistor is controlled to be in a normally-off state.

The display substrate further comprises a power signal line which is arranged on the same layer with the fifth metal pattern and is arranged in parallel, wherein the power signal line is connected with the fourth metal pattern through a via hole and is used for transmitting power voltage to the fourth metal pattern and then transmitting the power voltage to the first metal pattern so as to control the isolating transistor to be in a normally-off state.

Wherein, the display substrate is also provided with a first datum line; the first reference line is connected with the semiconductor layer of the first transistor through the fifth metal pattern which is longitudinally arranged, and a first initial voltage is charged into the storage capacitor of the pixel unit of the current stage through the semiconductor layer of the first transistor when the second metal pattern controls the first transistor to be conducted.

The display substrate is further provided with a second reference line, the second reference line is connected with the semiconductor layer of the second transistor through the fifth metal pattern, and when the second metal pattern controls the second transistor to be conducted, a second initial voltage is charged into the pixel electrode of the pixel unit at the upper stage or the lower stage through the semiconductor layer of the second transistor.

The first datum line and the second datum line are connected with the fifth metal patterns of different strips through via holes.

Wherein the first reference line and the second reference line are located in different layers; the first datum line is positioned on one side of the fifth metal pattern far away from the semiconductor layer, and the second datum line is positioned on one side of the fifth metal pattern close to the semiconductor layer.

And a layer of the display substrate far away from the fifth metal pattern is provided with pixel electrodes, and the pixel electrodes and the first datum line are positioned on the same layer and are arranged at intervals.

In order to solve the above problems, a second aspect of the present application provides a display panel, where the display panel includes an array substrate, and the array substrate is a display substrate according to any one of the embodiments of the first aspect.

The beneficial effects of the application are as follows: the semiconductor layer is arranged on the substrate continuously, the first metal pattern serving as the grid electrode is arranged at the connecting part of the semiconductor layer, the first metal pattern and the connecting part of the semiconductor form a partition transistor, the two ends of the connecting part of the semiconductor layer are electrically partitioned by controlling the grid electrode of the partition transistor, and the partition transistor is used for enabling the semiconductor layer to be in an 'electrically partitioned' state to replace the partition of the semiconductor layer on the physical structure, so that some columns of ESD problems caused by independent design of the semiconductor layer are avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a conventional arrangement of semiconductors;

FIG. 2 is a schematic diagram of an embodiment of a display substrate according to the present application;

FIG. 3 is a schematic diagram of a second embodiment of a display substrate according to the present application;

FIG. 4 is a schematic structural diagram of a third embodiment of a display substrate according to the present application;

FIG. 5 is a schematic diagram of a fourth embodiment of a display substrate according to the present application;

FIG. 6 is a schematic diagram of a fifth embodiment of a display substrate according to the present application;

FIG. 7 is a schematic diagram of a sixth embodiment of a display substrate according to the present application;

FIG. 8 is a schematic diagram of a seventh embodiment of a display substrate according to the present application;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present application, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to more clearly describe the embodiments of the present application, the present application provides a conventional lower polysilicon arrangement, and referring to fig. 1, fig. 1 is a conventional arrangement structure of a semiconductor. As shown in fig. 1, the semiconductor layer 11 is disposed on the display substrate, and the semiconductor layer 11 in each pixel unit 10 and the semiconductor layer 11 in the adjacent pixel unit 10 are designed independently of each other. The semiconductor layer 11, which is independently designed, has a tip 101 (end), and the semiconductor layer 11 is likely to absorb static electricity at its end, thereby causing ESD electrostatic shock to occur to the adjacent TFT at its tip (end).

In order to avoid a series of static electricity damage problems at the tail end of the semiconductor layer, the application provides a display substrate with a semiconductor layer continuously designed. Referring specifically to fig. 2-8.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a first embodiment of a substrate according to the present application. As shown in fig. 2, the display substrate includes a plurality of pixel units 20 arranged in an array, and the plurality of pixel units 20 are cascaded, specifically, in a column cascade or a row cascade. For example, the pixel units 20 in the same row are one-level, and the pixel units 20 in the same row are cascaded with the pixel units 20 in the previous row or the next row; or the pixel units 20 in the same column are one-level, and the pixel units 20 in the same column are cascaded with the pixel units 20 in the previous column or the next column, which is not limited herein.

Each level of pixel cells 20 includes a semiconductor layer 21 arranged in a regular pattern. Taking this level of pixel units as an example.

The semiconductor layer 21 of the current-stage pixel unit 20 includes a semiconductor body 211 and a semiconductor connection 212 extending to the semiconductor layer 21 of the previous-stage or next-stage pixel unit 20 and connected to the previous-stage or next-stage semiconductor layer 21. The first metal pattern 221 serving as a gate electrode is provided on the surface of the semiconductor layer 21 at a position corresponding to the semiconductor connection portion 212, and the first metal pattern 221 and the semiconductor connection portion 212 form a blocking transistor T0. By controlling the gate electrode (i.e., the first metal pattern 221) of the blocking transistor T0, it is possible to realize that both ends of the semiconductor connection portion 212 are electrically blocked. Here, both ends of the semiconductor connection portion 212 refer to the semiconductor layer 21 located at both sides of the first metal pattern 221.

In this embodiment, the semiconductor is polysilicon Si, and the semiconductor layer 21 is a thin film formed of semiconductor Si, specifically disposed on the display substrate or the array substrate of the display panel. In one embodiment, the polysilicon may be pSi, and in another embodiment, the polysilicon may be nSi, which forms a P-type transistor or an N-type transistor, respectively, without limitation.

In the present embodiment, the first metal pattern 221 is located at a different layer from the semiconductor layer 21, specifically, the first metal pattern 221 is located at a layer above the semiconductor layer 21. A gate insulating layer GI is further disposed between the first metal pattern 221 and the semiconductor layer 21 to space the first metal pattern 221 and the semiconductor layer 21. The first metal pattern 221 is a patterned gate layer made of metal. Wherein the semiconductor body 211 and the semiconductor connection 212 are located on the same layer and are connected to each other to form a continuous semiconductor layer 21.

In this embodiment, the pixel units in the same row are one-level, and the semiconductor layer 21 of the pixel unit 20 of the present level includes a first extension portion 2111 extending toward the semiconductor layer 21 of the pixel unit 20 of the previous level, and a second extension portion 2112 extending toward the semiconductor layer 21 of the pixel unit 20 of the next level. Specifically, the connection position of the first extension portion 2111 of the current-stage pixel unit 20 and the second extension portion 2112 of the previous-stage pixel unit 20 forms one semiconductor connection portion 212, and the connection position of the second extension portion 2112 of the current-stage pixel unit 20 and the first extension portion 2111 of the next-stage pixel unit 20 forms another semiconductor connection portion 212. Wherein, one semiconductor connection portion 212 is the semiconductor connection portion 212 of the current-stage pixel unit 20, and the other semiconductor connection portion 212 is the semiconductor connection portion 212 of the next-stage pixel unit 20, that is, one pixel unit 20 only includes one semiconductor connection portion 212 and one semiconductor body portion 211, in other words, the semiconductor connection portion 212 is disposed between the current-stage pixel unit 20 and the previous-stage or next-stage pixel unit 20, and is not limited herein, for connecting the semiconductor body portion 211 of the current-stage pixel unit 20 with the semiconductor body portion 211 of the previous-stage or next-stage pixel unit 20.

Wherein the extending directions of the first and second extending portions 2111 and 2112 are opposite. The first extension portion 2111 of the pixel unit 20 of the present stage extends in a direction approaching the second extension portion 2112 of the previous stage, specifically, extends leftward as shown in fig. 2. The second extension portion 2111 of the pixel unit 20 of the present stage extends in a direction approaching the second extension portion 2112 of the next stage, specifically, extends rightward as seen in fig. 2. In other embodiments, the extension may be upward or downward, respectively, without limitation.

In the present embodiment, the semiconductor layer 21 in the current pixel unit 20 is connected to the semiconductor layer 21 in the pixel unit 20 corresponding to the position of the upper line or the lower line thereof, respectively. In another embodiment, the pixel units 20 in the same column are at one level, and the semiconductor layer 21 in the current pixel unit 20 is connected to the semiconductor layer 21 in the pixel unit in the previous column or the next column, respectively, which is not limited herein.

In the present embodiment, the semiconductor body portion 211 further includes a first body portion 2113 provided in an H-shape, and the first extension portion 2111 and the second extension portion 2112 are provided on the same side of the first body portion 2113 provided in an H-shape, so that it is convenient to arrange a plurality of semiconductor connection portions 212 formed by connecting the first extension portion 2111 and the second extension portion 2112 in the same direction. The same direction includes a longitudinal direction (vertical direction) and a transverse direction (horizontal direction). I.e., the first extension 2111 is in the same column or row as the second extension 2112. In other embodiments, the first extending portions 2111 and the second extending portions 2112 may also be staggered according to the staggered pixel units, which is not limited herein. In other embodiments, the first extension 2111 and the second extension 2112 may also be provided on opposite sides of the first body portion 2113 in an H-shaped arrangement.

In the present embodiment, the semiconductor body portion 211 in the present-stage pixel unit 20 is connected to the semiconductor connection portion 212, and the semiconductor body portion 211 includes a first extension portion 2111 and a second extension portion 2112. The first extension portion 2111 of the pixel unit 20 of the present stage is connected to the second extension portion 2112 of the pixel unit 20 of the previous stage, and the second extension portion 2112 of the pixel unit 20 of the present stage is connected to the first extension portion 2111 of the pixel unit 20 of the next stage, thereby forming a continuous semiconductor layer 21 on the display substrate.

In this embodiment, the first extension portion 2111 is disposed in an inverted S-shape, and the second extension portion is disposed in an L-shape. In other embodiments, other shapes are possible.

In the present embodiment, the number of layers in which the first metal pattern 221 is located is defined as a first layer metal pattern M1. The first metal pattern M1 is provided on the surface of the semiconductor layer 21, and is stacked on and spaced apart from the semiconductor layer 21. Wherein the first layer metal pattern M1 includes a second metal pattern and a third metal pattern disposed at the position of the semiconductor body portion 211 in addition to the first metal pattern 221 disposed at the position of the semiconductor connection portion 212; the second metal pattern and the semiconductor body 211 form a plurality of transistors such as a switching transistor and a driving transistor for controlling and adjusting the light emission of the OLED device in the pixel unit. The number of the transistors can be designed according to actual requirements.

Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a second embodiment of a substrate according to the present application. As shown in fig. 3, the first metal pattern M1 includes a first metal pattern 221 disposed at a position corresponding to the semiconductor connection portion 212 and a second metal pattern 222 disposed at the semiconductor body portion 211, where the second metal pattern 222 is a plurality of metal traces arranged in parallel and at intervals, and is also a gate line for forming a gate of a transistor, so as to control the on state of the transistor in the pixel unit 20. Note that, for the sake of making the structure more clear, specific reference numerals of the semiconductor layer 21 are omitted herein, and reference numerals of the semiconductor layer 21 refer to fig. 2 and the description of the first embodiment, which are not repeated herein.

In the second embodiment, the semiconductor body portion 211 includes a first body portion 2113 having an H-shape, a first extension portion 2111 having an S-shape, and a second extension portion 2112 having an L-shape. Specifically, the second metal patterns 222 include a plurality of pixel units, in this embodiment, each of the pixel units includes four pixel units, one of the second metal patterns 222 is located above the first extension portion 2111 (i.e. disposed corresponding to the first extension portion 2111), the other one is disposed corresponding to the second extension portion 2112, and the middle two are disposed corresponding to the upper portion and the lower portion of the first main portion 2113, respectively, in other embodiments, more second metal patterns 222 may be disposed according to the actual transistor number requirement, which is not limited herein. In a specific embodiment, from top to bottom, the first second metal pattern 222 is a first scan line, the second metal pattern 222 is a second scan line, the third second metal pattern 222 is a switching signal line, and the fourth second metal pattern 222 is a third scan line, where the switching signal line is a transistor for controlling the switching transistor, that is, controlling the light emission of the OLED device, which is not limited herein. In other embodiments, the second metal pattern 222 of each level of pixel units may further include two, three, five, six or more, which is not limited herein.

The second metal pattern 222 is a linear metal pattern used as a gate of a transistor for transmitting a gate signal to a different transistor.

In the present embodiment, the first layer metal pattern M1 further includes a third metal pattern 223 provided in a block shape at a middle position of the H-shaped first body portion 2113, wherein the third metal pattern 223 forms a first plate (also a lower plate) of the storage capacitor Cst in the pixel unit 20. Specifically, the third metal pattern 223 is disposed at a middle position of the H-shape, more specifically, at a middle of the middle two second metal patterns 222, which is not limited herein.

In this embodiment, the first metal pattern 221, the second metal pattern 222 and the third metal pattern 223 are all located on the same layer (i.e., the first layer metal pattern M1) and are not intersected, i.e., are disposed at a distance from each other. In the present embodiment, by providing the first metal pattern 221 and the second metal pattern 222 and the third metal pattern 223 in the same layer, the number of wiring layers on the display substrate can be reduced, that is, the thickness of the display panel can be reduced. In other embodiments, the first metal pattern 221, the second metal pattern 222 and the third metal pattern 223 may be disposed in different layers, which is not limited herein. It is understood that the gate insulating layer GI is also provided between the second metal pattern 222 serving as a gate electrode and the semiconductor layer 21. The first metal pattern 221 serves as a gate electrode of the blocking transistor T0, and the second metal pattern 222 serves as a gate electrode of other transistors including a plurality of transistors such as a driving transistor and a switching transistor, which are not limited herein. The third metal pattern 223 serves as a first plate of the storage capacitor Cst.

In one embodiment, the second metal patterns 222 (also referred to as gate lines) include a plurality of second metal patterns 222 arranged in parallel (parallel is merely shown), and in this embodiment, the plurality of second metal patterns 222 are arranged in parallel.

In a more specific embodiment, the first transistor T1 in the pixel unit 20 of the present stage and the second transistor T2 in the pixel unit of the previous stage or the next stage share one second metal pattern 222 (i.e. the gate line), so as to control the same to be turned on simultaneously. This is because in the present embodiment, there is an overlapping portion of the semiconductor layer 21 in the present-stage pixel unit 20 and the projection of the semiconductor layer 21 of the previous-stage pixel unit 20 in the lateral direction (or in the extending direction of the second metal pattern 222). In this embodiment, the second metal pattern 222 is disposed along the lateral direction.

Specifically, the second metal patterns 222 in the pixel unit 20 of the present stage include four lines, and the first second metal patterns 222 in the pixel unit 20 of the present stage and the fourth second metal patterns 222 in the pixel unit 20 of the previous stage share one metal line; the fourth second metal pattern 222 in the pixel unit 20 of the present stage shares one metal line with the first second metal pattern 222 in the pixel unit 20 of the next stage. By sharing the second metal pattern 222 of the present stage with one second metal pattern 222 of the previous stage or the next stage, it is substantially only necessary to provide three second metal patterns 222 for each stage of pixel units, and in this way, wiring of one second metal pattern 222 (gate line) can be saved, and a plurality of pixel units can be cascaded with each other. In other embodiments, the second metal patterns 222 in each level of pixel units 20 may also include five, six, etc., where the first second metal patterns 222 of the level of pixel units 20 are common to the last second metal patterns 222 of the previous level of pixel units 20, which is not limited herein, and the number of second metal patterns 222 is specifically related to the number of transistors.

In this embodiment, the pixel unit 20 of the present stage may include 7 transistors, but of course, may include more transistors, and the gate wiring is specifically set according to the actual requirement, which is not limited in the number of transistors. In this embodiment, the first transistor T1 in the pixel unit 20 of the present stage shares a second metal pattern (gate line) with the second transistor T2 in the pixel unit 20 of the previous stage, and the second transistor T2 in the pixel unit 20 of the present stage shares a gate line with the first transistor T1 in the pixel unit 20 of the next stage. In other words, when the first transistor of the pixel unit of the present stage is T1, it shares one gate line with the other transistor of the pixel unit of the previous stage; when the first transistor of the pixel unit of the present stage is T2, it shares one gate line with the other transistor of the pixel unit of the next stage, and the first transistor is not limited herein. In this way, the pixel unit 20 of the present stage is cascade-connected with the pixel units 20 of the previous stage and the next stage.

Taking the example that the first transistor T1 of the pixel unit 20 of the present stage and the second transistor T2 of the pixel unit 20 of the previous stage share one second metal pattern 222.

Further, the present application also provides a third display substrate, referring to fig. 4, and fig. 4 is a schematic structural diagram of a third embodiment of the display substrate according to the present application. As shown in fig. 4, the display substrate is further provided with a second layer metal pattern M2 on the surface of the first layer metal pattern M1. Also, in order to make the structure look clearer, reference numerals of a part of the semiconductor layer 21 and the first layer metal pattern M1 are omitted in the drawings, and description is made along with reference numerals in the first and second embodiments.

The third metal pattern 23 includes a fourth metal pattern 231 for transmitting a blocking voltage to the first metal pattern 221, and the fourth metal pattern 231 is directly connected to the first metal pattern 221 through a via hole (shown as a black matrix in the drawing) for transmitting a blocking voltage VGH to a gate electrode of the blocking transistor T0 (i.e., the first metal pattern), thereby controlling the blocking transistor T0 to be in a normally-off state. The normally closed state is the state in which it is normally closed. The blocking transistor T0 is controlled to be always in an off state, so that both ends of the semiconductor body 211 are electrically blocked, and both ends of the semiconductor body 211 are connected through the semiconductor connection part 212, thereby avoiding static electricity accumulation. Specifically, the fourth metal pattern 231 is directly connected to the first metal pattern 221 of the first metal pattern M1 through the via hole to transmit the gate voltage to the first metal pattern 221 to control the blocking transistor T0 to be in the off state, wherein the signal transmission direction of the blocking voltage VGH is shown by an arrow in the figure.

In this embodiment, the blocking transistor T0 is located between the first transistor T1 of the current-stage pixel unit 20 and the second transistor T2 of the previous-stage pixel unit 20, and the blocking transistor T0 is controlled to be in an off state while the first transistor T1 and the second transistor T2 are controlled to be turned on by the second metal pattern 222, so that the current-stage pixel unit 20 and the previous-stage pixel unit 20 operate independently.

In the present embodiment, there is a partial overlap of the fourth metal pattern 231 and the first metal pattern 221 in the vertical projection, and a via hole is disposed at the overlapped portion to connect the fourth metal pattern 231 and the first metal pattern 221. Wherein the fourth metal pattern 231 is also coated with metal.

In another embodiment, the fourth metal pattern 231 and the first metal pattern 221 are not directly connected through a via hole. Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of a display substrate according to the present application. Also, in order to make the structure look clearer, part of the reference numerals are omitted from the drawings, and the description of the reference numerals of the above embodiments is followed. As shown in fig. 5, the display substrate is further provided with a second layer metal pattern M2 as shown in fig. 4 on the surface of the first layer metal pattern M1, the second layer metal pattern M2 includes a fourth metal pattern 231 for transmitting the blocking voltage VGH to the first metal pattern 221, the surface of the second layer metal pattern M2 is further provided with a third layer metal pattern M3, and the third layer metal pattern M3 includes a plurality of fifth metal patterns 241 arranged longitudinally. Wherein, a fifth metal pattern 241 arranged longitudinally is connected to the first metal pattern 221 and the fourth metal pattern 231 through the via hole, respectively, so that the blocking voltage VGH of the fourth metal pattern 231 is transmitted to the first metal pattern 221 through the fifth metal pattern 241, thereby transmitting the blocking voltage VGH to the gate of the blocking transistor T0 to control the blocking transistor T0 to be in a normally-off state. It should be noted that, the number of the vias here includes at least two, the fourth metal pattern 231 is connected to the fifth metal pattern 241 through one of the vias, so that the blocking voltage is transmitted to the fifth metal pattern 241, the fifth metal pattern 241 is connected to the first metal pattern 221 through the other via, and the blocking power is transmitted to the first metal pattern 221, so that the semiconductor layer 21 of the current stage and the semiconductor layer 21 of the previous stage are controlled to be in the blocking state, that is, the no-signal-flowing state, through the first metal pattern 221. Specifically, the signal conduction condition is shown in the enlarged view of the upper right part of fig. 5.

In the third and fourth embodiments, the fourth metal pattern 231 needs to be extended up to the edge of the display screen and connected to an IC Pad (control chip) at the edge of the display screen for transmitting the blocking voltage VGH to the fourth metal pattern 231.

In a further embodiment of the fourth embodiment, the third metal pattern M3 further includes a power signal line ELVDD, where the power signal line ELVDD is located at the same layer as the fifth metal pattern 241, and the power signal line ELVDD is also arranged longitudinally and is arranged in parallel without intersecting with the fifth metal pattern 241. The power signal lines ELVDD and the fifth metal patterns 241 are patterned lines made of metal, and the names herein merely indicate that the functions thereof are different, and the manufacturing processes thereof may be the same, which is not limited thereto. In a further embodiment, the fourth metal pattern 231 is further connected to the power signal line ELVDD to transmit the power voltage ELVDD to the fourth metal pattern 231 through the power signal line ELVDD, and the fourth metal pattern 231 is transmitted to the first metal pattern 221 through the fifth metal pattern 241. Wherein, the blocking voltage VGH and the power supply voltage ELVDD can both make the blocking transistor T0 in an off state. Referring to fig. 6, fig. 6 is a schematic structural diagram of a fifth embodiment of a substrate according to the present application. As shown by the dotted arrow in fig. 6, the power signal line ELVDD transmits the power voltage ELVDD to the fourth metal pattern 231, and the fourth metal pattern 231 is transmitted to the first metal pattern 221 through the fifth metal pattern 241. In fig. 6, the structural illustration of the semiconductor layer is omitted, and the lines of the third layer metal pattern M3 are roughened.

Obviously, the power signal line ELVDD is used not only to transmit the power voltage to the first metal pattern but also to input the voltage signal to the pixel electrode in the fifth embodiment. Therefore, in other embodiments, the power signal line ELVDD may not be connected to the fourth metal pattern 231, i.e., the off transistor is controlled to be in an off state by the off voltage VGH in the fourth embodiment. But a power signal line ELVDD for transmitting a power voltage is provided on the display substrate. The power signal line ELVDD is also disposed on a surface of the first metal pattern M1 away from the semiconductor layer 21 and connected to the power signal line ELVDD through a via hole, and is used as a source of a transistor for charging a voltage signal to the pixel electrode. Wherein the power supply voltage is a constant current source voltage.

In this embodiment, the third metal pattern M3 further includes a data line data for writing data signals to the pixel electrode, and the third metal pattern M3 further includes a connection metal line, and referring to fig. 7, the disclosure is not limited thereto.

In the above embodiment, the second metal pattern M2 includes other wirings in addition to the fourth metal pattern 231, and further, as shown in fig. 4, the second metal pattern M2 further includes a sixth metal pattern 232 in a block shape as the second plate of the storage capacitor Cst, and the sixth metal pattern 232 covers the surface of the third metal pattern 223 to form the storage capacitor Cst with the third metal pattern 223. By the same-layer wiring, the superposition of the wiring layers can be effectively reduced.

Further, referring to fig. 7, fig. 7 is a schematic structural diagram of a sixth embodiment of a substrate according to the present application. As shown in fig. 7, the display substrate further includes a first reference line Vref1 and a second reference line Vref2. The first reference line Vref1 and the second reference line Vref2 have a certain width, as specifically shown by the thick line portion in fig. 7. The first reference line Vref1 is laterally aligned and connected to the semiconductor layer of the first transistor T1 through the vertically aligned fifth metal pattern 241, specifically, to the one-side semiconductor layer 21 of the first transistor T1 as the source electrode, so that the first initial voltage is charged to the storage capacitor Cst of the current-stage pixel unit through the semiconductor layer 21 of the first transistor T1 when one of the second metal patterns 222 controls the first transistor T1 to be turned on, and the first initial voltage is used to initialize the storage capacitor Cst.

The display substrate further includes a second reference line Vref2 connected to the semiconductor layer 21 of the second transistor T2 through the fifth metal pattern 241 arranged vertically, specifically, to the one side semiconductor layer 21 of the second transistor T2 as the source electrode, so that the second initial voltage is charged to the pixel electrode of the upper pixel unit through the semiconductor layer 21 of the second transistor T2 when the second metal pattern 222 controls the second transistor T2 to be turned on.

Here, the second reference line Vref2 is connected to the first reference line Vref1 by a different fifth metal pattern 241, thereby ensuring that crosstalk does not occur in the signal lines. The second metal pattern 222 connected to the first transistor T1 and the second transistor T2 is the same, so that the initialization of the storage capacitor Cst in the current-stage pixel unit and the initialization of the pixel electrode inode of the previous-stage pixel unit are performed simultaneously, and the processes do not interfere with each other due to the presence of the blocking transistor T0.

Specifically, the signal flow of the first reference line Vref1 for initializing the storage capacitor Cst in the current level pixel unit is shown by a dotted line in fig. 7, the signal of the first reference line Vref1 is transmitted to one of the third layer metal patterns 241 through the via hole, and is transmitted to the semiconductor layer 21 of the first transistor T1 through the other via hole of the same one of the third layer metal patterns 241, and at the same time, the semiconductor layer 21 transmits the signal of the first reference line Vref1 to the storage capacitor Cst due to the conduction of the first transistor T1. The step of transmitting the signal of the first reference line Vref1 to the storage capacitor Cst by the semiconductor layer 21 may further specifically include: vref1 is first transferred to another fifth metal pattern 241, and then transferred to the first substrate of the storage capacitor Cst (i.e., the third metal pattern 223) through the fifth metal pattern 241. The specific expression is: vref1, M3, T1, M3, and the first plate (M2) of the storage capacitor Cst.

The signal flow of initializing the pixel electrode inode of the pixel unit of the previous stage by the second reference line Vref2 is shown by another broken line in fig. 7. Specifically, the signal of the second reference line Vref2 is transmitted to one of the fifth metal patterns of the third metal pattern M3 through the via hole, and is transmitted to the semiconductor layer 21 of the second transistor T2 through the other via hole of the same fifth metal pattern 241, and at the same time, the semiconductor layer 21 transmits the signal of the second reference line Vref2 to the pixel electrode inode in the upper pixel unit due to the conduction of the second transistor T2. The specific expression is: vref2, M3, T2, semiconductor layer 21, and pixel electrode Anode at the upper stage.

In the present embodiment, the first reference line Vref1 and the second reference line Vref2 are located at different layers from the fifth metal pattern 241. The first reference line Vref1 and the second reference line Vref2 are connected to different pieces of the metal patterns 241 through vias, respectively, and are not limited herein. In a specific embodiment, the first reference line Vref1 and the second reference line Vref2 are located in different layers, the first reference line Vref1 is located on a side surface of the fifth metal pattern 241 away from the semiconductor layer 21, the second reference line Vref2 is located on a side surface of the fifth metal pattern 241 near the semiconductor layer 21, specifically, the second reference line Vref2 is located in the same layer as the second metal pattern M2, that is, in the same layer as the fourth metal pattern 231, and reference may be made to Vref2 specifically as shown in fig. 4. The first reference line Vref1 is located at the same layer as the pixel electrode inode.

Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of a seventh embodiment of a display substrate according to the present application. The fifth metal pattern 241 is also provided with a pixel electrode inode on the surface thereof, and the pixel electrode inode is connected to the semiconductor layer 21 on the drain side of a certain transistor. Specifically, the pixel electrode inode is connected to the fifth metal pattern 241 through a via hole, and the fifth metal pattern 241 is connected to the semiconductor layer 21 as the drain side through another via hole. The transistor may be the second transistor T2 or may be another transistor, and is not limited herein. As shown in fig. 8, the first reference line Vref1 and the pixel electrode inode are provided at the same layer and are provided at a distance from each other. Fig. 8 is a structural layout diagram of a pixel electrode layer, in which a first reference line Vref1 is disposed around a pixel electrode inode and does not intersect the pixel electrode inode. In this embodiment, by disposing the first reference line Vref1 on the layer of the pixel electrode inode, since there is a very thick organic dielectric layer between the pixel electrode inode and the second layer metal pattern (the layer including the scan line), the parasitic capacitance formed by the first reference line Vref1 and the second layer metal pattern M2 is avoided to adversely affect the signal transmission on each metal line in the second layer metal pattern M2.

In this embodiment, the second reference line 202 and the first reference line 201 are further disposed on different layers, specifically, the second reference line Vref2 is disposed on the layer of the second layer metal pattern M2, so that the parasitic capacitance formed by the first reference line 201 and the second reference line 202 can be avoided to adversely affect the signal transmission on the second reference line.

The first reference line Vref1 and the pixel electrode inode are the fourth metal pattern M4, and the semiconductor layer 21 is the M0 layer. The dielectric layers between each of M0, M1, M2, M3 and M4 are arranged in a mutually laminated relationship. The dielectric layer between M0 and M1 is the gate insulating layer GI.

Further, the pixel electrode Anode includes a red pixel electrode, a green pixel electrode, and a blue pixel electrode. In this embodiment, there are differences in the sizes of the pixel electrodes Anode of different colors, wherein the red pixel electrode, the green pixel electrode and the blue pixel electrode are staggered in the horizontal direction, which is not limited herein.

The application also provides a display panel, which comprises an array substrate, wherein the semiconductor layer, the first layer metal pattern M1, the second layer metal pattern M2, the third layer metal pattern M3, the first reference line Vref1, the second reference line Vref2 and the pixel electrode Anode are sequentially arranged on the array substrate.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the application. As shown in fig. 9, the display panel includes an array substrate 91, the array substrate 91 includes a glass substrate 911, and a buffer layer 912 is provided on the glass substrate 911. In this embodiment, the buffer layer 912 includes two layers, and in other embodiments, may be provided as one layer, which is not limited herein.

The surface of the buffer layer 912 is provided with the semiconductor layer 913 arranged in a pattern, and the patterned arrangement of the semiconductor layer 913 is described in the above embodiment of the top-view structure (specifically described in fig. 2), which is not described herein.

The surface of the semiconductor layer 913 is provided with a gate insulating layer GI, and a first metal pattern M1 is disposed on a side of the gate insulating layer GI away from the semiconductor layer 913, and the first metal pattern M1 includes the first metal pattern 221, the second metal pattern 222 and the third metal pattern 223.

The surface of the second metal pattern M1 is provided with a first dielectric layer CI and a second dielectric layer ILD, wherein a second metal pattern M2 is disposed between the first dielectric layer CI and the second dielectric layer ILD, and the second metal pattern M2 includes a sixth metal pattern 232 disposed at a position corresponding to the storage capacitor, which is a second plate of the storage capacitor Cst, a fourth metal pattern 231 for transmitting a blocking voltage at a position adjacent to the blocking transistor T0, and a second reference line Vref2 for transmitting a reference voltage at a position adjacent to a transistor of a previous pixel unit.

The second dielectric layer ILD is provided with a third metal pattern M3 on a side surface thereof away from the semiconductor layer 913, the third metal pattern M3 including a fifth metal pattern 241 connecting the first metal pattern 221 and the fourth metal pattern 231. The third layer metal pattern M3 further includes a Data signal line Data for transmitting a Data voltage, and a power signal line ELVDD for transmitting a power signal. In this embodiment, the third metal pattern M3 further includes other fifth metal patterns 241 connecting the semiconductor layer 913 and the second reference line Vref2, which are not labeled here.

The surface of the third layer metal pattern M3 is provided with an Anode flat layer PLA, and the surface of the flat layer PLA is provided with a pixel electrode inode, also referred to as a pixel Anode. The pixel electrode inode further includes a first reference line Vref1 at the same layer.

In this embodiment, the drain D of the first transistor T1 is connected to the storage capacitor Cst of the current-stage pixel unit, and the first reference line Vref1 transmits the first reference voltage to the storage capacitor Cst of the current-stage pixel unit through the first transistor T1. The drain D of the second transistor T2 is connected to the pixel electrode of the previous stage pixel unit, and the second reference line Vref2 transmits the second reference voltage to the pixel electrode of the previous stage pixel unit through the second transistor T2. A blocking transistor T0 is disposed between the first transistor T1 and the second transistor T2, and is used for blocking signal transmission of the first transistor T1 and the second transistor T2. Specifically, the second transistor T2 is a transistor in the pixel unit of the previous stage.

In this embodiment, the surface of the pixel electrode inode is further provided with a pixel defining layer PDL, the surface of the pixel defining layer PDL is provided with an OLED device connected to the pixel Anode inode, and the surface of the OLED device is provided with a pixel Cathode captode. The light emission of the OLED device disposed therebetween is controlled by the voltage difference between the pixel Anode and the pixel Cathode, and the Cathode, cathode.

The beneficial pixels of the application are: the first metal pattern serving as the grid electrode is arranged at the corresponding position on the surface of the semiconductor layer through arranging the continuous semiconductor layer, so that the first metal pattern and the semiconductor layer form the isolation transistor, the isolation voltage is transmitted to the grid electrode of the isolation transistor, so that the isolation transistor is always in an off state, the transistors at two sides of the isolation transistor can work simultaneously without mutual interference, and on the other hand, the isolation transistor is utilized to enable the semiconductor layer to be in an 'electric isolation' state to replace the isolation of the semiconductor layer on the physical structure, so that some columns of ESD problems caused by independent design of the semiconductor layer are avoided.

The foregoing is only illustrative of the present application and is not to be construed as limiting the scope of the application, and all equivalent structures or equivalent flow modifications which may be made by the teachings of the present application and the accompanying drawings or which may be directly or indirectly employed in other related art are within the scope of the application.

Claims (10)

1. The display substrate is characterized by comprising a plurality of pixel units which are arranged in an array, and the pixel units are mutually cascaded; each stage of pixel units is provided with semiconductor layers which are arranged in a pattern;

the semiconductor layer of the pixel unit of the present stage comprises a semiconductor main body part and a semiconductor connecting part which extends to the semiconductor layer of the pixel unit of the previous stage or the next stage and is connected with the semiconductor layer of the pixel unit of the previous stage; and a first metal pattern serving as a grid electrode is arranged on the surface of the semiconductor layer at a position corresponding to the semiconductor connecting part, a blocking transistor is formed by the first metal pattern and the semiconductor connecting part, and the two ends of the semiconductor connecting part are electrically blocked by controlling the grid electrode of the blocking transistor.

2. The display substrate according to claim 1, wherein the semiconductor body portion of the pixel unit of the present stage includes a first extension portion extending toward the semiconductor layer of the pixel unit of the previous stage, and a second extension portion extending toward the semiconductor layer of the pixel unit of the next stage, the extension directions of the first extension portion and the second extension portion being opposite;

preferably, the first extension part is in an inverted S-shaped arrangement, and the second extension part is in an L-shaped arrangement; the first extension part of the pixel unit of the current stage extends to the second extension part of the pixel unit of the previous stage and is connected with the second extension part to form the semiconductor connection part; or, the second extension part of the pixel unit at the current stage extends to the first extension part of the pixel unit at the next stage and is connected with the first extension part to form the semiconductor connection part;

Preferably, the semiconductor main body portion further includes a first main body portion disposed in an H-shape, and the first extension portion and the second extension portion are disposed on the same side of the first main body portion disposed in the H-shape, so that the semiconductor connection portions are disposed correspondingly.

3. The display substrate according to claim 1, wherein the display substrate is further provided with a second metal pattern and a third metal pattern; the second metal pattern is a linear metal pattern arranged at a position corresponding to the semiconductor main body part; the third metal pattern is a block-shaped metal pattern provided at an intermediate position of the semiconductor body portion;

the second metal pattern and the third metal pattern are positioned on the same layer with the first metal pattern and are arranged at intervals;

preferably, the second metal pattern includes a plurality of lines, and the second metal pattern and the semiconductor layer form a plurality of transistors; the first transistor in the pixel unit of the current stage and the second transistor in the pixel unit of the previous stage or the next stage share one second metal pattern, so that the first transistor in the pixel unit of the current stage and the second transistor in the pixel unit of the previous stage or the next stage are simultaneously conducted.

4. A display substrate according to claim 3, wherein the blocking transistor is disposed between the first transistor and the second transistor so that the first transistor and the second transistor are turned on at the same time and do not interfere with each other.

5. The display substrate according to claim 4, wherein the first metal pattern, the second metal pattern, and the third metal pattern are first-layer metal patterns, the first-layer metal pattern surface is further provided with a second-layer metal pattern including a fourth metal pattern for transmitting a blocking voltage; the fourth metal pattern is connected with the first metal pattern through a via hole, and transmits a blocking voltage to the first metal pattern through the via hole so as to control the blocking transistor to be in a normally-off state, so that two ends of the semiconductor connecting part are electrically blocked.

6. The display substrate according to claim 4, wherein a fourth metal pattern for transmitting a blocking voltage is disposed on the surface of the first metal pattern, and a fifth metal pattern arranged longitudinally is disposed on the surface of the fourth metal pattern, and is connected to the first metal pattern and the fourth metal pattern through vias, respectively, so that the blocking voltage of the fourth metal pattern is transmitted to the fifth metal pattern through a via, and the fifth metal pattern is transmitted to the first metal pattern through another via, thereby transmitting the blocking voltage to the gate of the blocking transistor, so as to control the blocking transistor to be in a normally-off state.

7. The display substrate according to claim 6, further comprising a power signal line disposed on the same layer as the fifth metal pattern and parallel to the fifth metal pattern, wherein the power signal line is connected to the fourth metal pattern through a via hole, and is configured to transmit a power voltage to the fourth metal pattern and further to the first metal pattern, so as to control the blocking transistor to be in a normally-off state.

8. The display substrate of claim 6, further comprising a first fiducial line disposed thereon;

the first reference line is connected with the semiconductor layer of the first transistor through the fifth metal pattern which is longitudinally arranged, and a first initial voltage is charged into the storage capacitor of the pixel unit of the current stage through the semiconductor layer of the first transistor when the second metal pattern controls the first transistor to be conducted.

9. The display substrate according to claim 8, wherein a second reference line is further provided on the display substrate, the second reference line being connected to the semiconductor layer of the second transistor through the fifth metal pattern, and a second initial voltage is charged to a pixel electrode of the pixel unit of a previous or next stage through the semiconductor layer of the second transistor when the second metal pattern controls the second transistor to be turned on;

Preferably, the fifth metal pattern includes a plurality of lines, and the first reference line and the second reference line are connected to the fifth metal pattern of different lines through vias.

Further preferably, the first reference line and the second reference line are located in different layers; the first datum line is positioned on one side of the fifth metal pattern far away from the semiconductor layer, and the second datum line is positioned on one side of the fifth metal pattern near the semiconductor layer;

further preferably, a layer of the display substrate far from the fifth metal pattern is provided with pixel electrodes, and the pixel electrodes and the first reference line are located on the same layer and are spaced from each other.

10. A display panel, characterized in that the display panel comprises an array substrate, the array substrate being the display substrate according to any one of claims 1 to 9.