CN117198862A - Method for improving warpage of discrete device - Google Patents
Method for improving warpage of discrete device Download PDFInfo
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- CN117198862A CN117198862A CN202311453729.XA CN202311453729A CN117198862A CN 117198862 A CN117198862 A CN 117198862A CN 202311453729 A CN202311453729 A CN 202311453729A CN 117198862 A CN117198862 A CN 117198862A
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- 238000000034 method Methods 0.000 title claims abstract description 100
- 239000004065 semiconductor Substances 0.000 claims abstract description 124
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 85
- 229920005591 polysilicon Polymers 0.000 claims abstract description 85
- 230000008569 process Effects 0.000 claims abstract description 75
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 99
- 230000000694 effects Effects 0.000 description 10
- 230000008021 deposition Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000005452 bending Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- 238000007669 thermal treatment Methods 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a method for improving the warpage of a discrete device, wherein the method for improving the warpage of the discrete device comprises the following steps: depositing an ILD film layer on the topmost layer of the semiconductor device, and flattening the ILD film layer by adopting a CMP process; forming polysilicon stress layers on the front surface and the back surface of the semiconductor device respectively, wherein the temperature range for depositing the polysilicon stress layers comprises 500-600 ℃, and the polysilicon stress layers are used for applying stress to the semiconductor device so as to reduce the warping degree of the semiconductor device; removing the polysilicon stress layer positioned on the front surface of the semiconductor device; and forming a contact hole, and subsequently, not comprising a thermal annealing process. The application can form the polysilicon stress layer on the back of the semiconductor device by adopting a relatively simple process, so that the polysilicon stress layer applies tensile stress to the semiconductor device on the back, thereby improving the warping degree of the semiconductor device, avoiding the relatively complex process of turning over the semiconductor device with great operation difficulty and reducing the corresponding process cost.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a method for improving warpage of a discrete device.
Background
Warpage problems are common in discrete devices, particularly split gate high voltage devices (SGT), and excessive wafer (wafer) distortion is severe. When the wafer with serious deformation is conveyed by the machine, the conveying component cannot carry out vacuum adsorption on the wafer back, the wafer cannot be conveyed, and even the wafer is fallen. In the patterned area, the process cannot be performed due to the excessive warpage. In the wet etching area, the wafer spacing between adjacent grooves is too small in the acid etching process due to the overlarge warpage, and the wafer is stuck due to the surface tension of liquid. In the high temperature process of the furnace tube, the edge of the wafer is tilted and contacts with the wafer boat groove to scratch due to the overlarge tilting degree. The warpage problem described above occurs during the wafer production front-end process.
The prior method for solving the front-stage warping degree is mainly improved by the methods of overturning a wafer back deposition film layer, designing and adjusting the direction of a groove, pasting a film on the wafer back and the like, but the problems of complex process, high cost and potential pollution exist in the methods.
Disclosure of Invention
In view of this, the present application provides a method for improving warpage of discrete devices to solve the problems of complex process, high cost and potential pollution in the conventional solution.
The application provides a method for improving warpage of a discrete device, which comprises the following steps:
depositing an ILD film layer on the topmost layer of the semiconductor device, and flattening the ILD film layer by adopting a CMP process;
forming polysilicon stress layers on the front surface and the back surface of the semiconductor device respectively, wherein the temperature range for depositing the polysilicon stress layers comprises 500-600 ℃, and the polysilicon stress layers are used for applying stress to the semiconductor device so as to reduce the warping degree of the semiconductor device;
removing the polysilicon stress layer positioned on the front surface of the semiconductor device;
and forming a contact hole, and subsequently, not comprising a thermal annealing process.
Optionally, the polysilicon stress layer located on the back side of the semiconductor device applies tensile stress to the semiconductor device.
Optionally, the thickness range of the polysilicon stress layer includes 100 a-32000 a.
Optionally, the removing the polysilicon stress layer on the front surface of the semiconductor device includes: and removing the polysilicon layer positioned on the front surface of the semiconductor device by adopting a CMP process or an etching process.
According to the method for improving the warpage of the discrete device, the polysilicon stress layers are respectively formed on the front surface and the back surface of the semiconductor device, the polysilicon stress layers can be formed on the back surface of the semiconductor device by adopting a relatively simple process, so that tensile stress is applied to the semiconductor device by the polysilicon stress layers on the back surface, the warpage of the semiconductor device is improved, the formation of the polysilicon stress layers on the back surface of the semiconductor device in the process of overturning the semiconductor device is avoided, the relatively complex and high-operation difficulty process of overturning the semiconductor device is avoided, the corresponding process cost is reduced, the front surface of the semiconductor device contacts with a deposition chamber and related structures in the deposition chamber after overturning is avoided, and loss and/or pollution to the front surface of the semiconductor device can be avoided; and removing the polysilicon stress layer positioned on the front surface of the semiconductor device so as to continuously develop other processes on the front surface of the semiconductor device to form structures such as contact holes, and the subsequent thermal annealing process is not included so that the warping degree improving effect can be kept, and each developed process has higher quality, so that the finally obtained semiconductor device has higher performance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for improving warpage of a discrete device according to an embodiment of the present application;
FIGS. 2a and 2b are schematic views of the structures obtained by the related steps in an embodiment of the present application;
FIGS. 3a and 3b are diagrams illustrating a bending statistics analysis according to an embodiment of the present application;
fig. 4a, 4b and 4c are schematic structural views illustrating related steps in an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
The first aspect of the present application provides a method of improving warpage of a discrete device, wherein the discrete device may comprise a discrete semiconductor device. Referring to fig. 1, the method for improving warpage of discrete devices includes the following steps S110 to S140.
S110, depositing an ILD (Inter-Layer Dielectrics, inter-layer dielectric material) film layer on the top layer of the semiconductor device, and flattening the ILD film layer by adopting a CMP (chemical mechanical polishing) process.
In the semiconductor device, the ILD film layer may be disposed on a surface of the metal layer to serve as a dielectric layer on the surface of the metal layer. Alternatively, the ILD film layer may be formed using BPSG (boron and phosphorous containing dielectric material) or the like.
The inventors have found that after depositing the ILD film layer, the surface of the semiconductor device is uneven, and if Polysilicon (POLY) is directly deposited on the uneven ILD film layer, then neither the polysilicon CMP nor the polysilicon back etching process can be completely removed in the subsequent polysilicon removal process for the front side of the semiconductor device. Based on this finding, the above step S110 adopts a CMP process to planarize the ILD film layer to continue depositing polysilicon on the planarized ILD film layer surface.
According to the method, the ILD film layer is flattened through a CMP process, polysilicon is deposited on the front side and the back side of the semiconductor device with the ILD film layer as the topmost layer, the polysilicon on the front side of the semiconductor device can be removed completely, the polysilicon layer does not cause other influences on the semiconductor device, and the performance of the finally obtained semiconductor device can be guaranteed on the basis of improving the warpage of the semiconductor device.
S120, referring to fig. 2a, polysilicon stress layers (POLY film layers) are formed on the front and back surfaces of the semiconductor device 210, respectively, and as shown in fig. 2a, the polysilicon stress layers include a first stress layer 221 on the front surface of the semiconductor device 210 and a second stress layer 222 on the back surface of the semiconductor device 210. The temperature range for depositing the polysilicon stress layer includes 500 ℃ to 600 ℃, and the polysilicon stress layer is used for applying stress to the semiconductor device 210 so as to reduce the warpage of the semiconductor device 210. Further, the semiconductor device 210 shown in fig. 2a includes an ILD film layer on top.
Specifically, the second stress layer 222 located at the rear surface of the semiconductor device 210 applies tensile stress to the semiconductor device 210 to improve the warpage of the semiconductor device 210 by the tensile stress.
Alternatively, the polysilicon stress layer may be made of a material or the like that is low in cost, easy to deposit, and capable of applying tensile stress to the semiconductor device 210 at the back surface of the semiconductor device 210 to reduce warpage thereof.
The semiconductor device 210 may further include a substrate and/or a metal layer. The inventors have studied the formation process of some semiconductor devices and found that on these products, the chip size design is relatively large, the design of the back-end connection layer (Contact, connection layer connected to the metal layer) is long and large, and the grooves and the connection layer strip holes are all in the same direction. After tungsten (W) and Metal (Metal) are deposited on the connecting layer, the wafer is seriously deformed due to the stress of the tungsten and the Metal, the warping is overlarge, the Bending (BOW) value reaches more than 400um, and the warping is serious even 760um, so that the next Metal patterning process cannot be performed, stable standard quantity production cannot be realized, and particularly, the product with double-connecting-layer design is more serious in warping. The step S120 forms the polysilicon stress layer on the front surface and the back surface of the semiconductor device 210, and forms the second stress layer 222 on the back surface of the semiconductor device 210 by using a relatively simple process, so that the second stress layer 222 applies tensile stress to the semiconductor device 210 on the back surface to improve the warpage of the semiconductor device 210, and forms the corresponding polysilicon stress layer on the back surface of the semiconductor device 210 by turning over the semiconductor device 210 during the formation of the second stress layer 222 on the back surface of the semiconductor device 210, thereby avoiding the relatively complex process of turning over the semiconductor device 210 with great operation difficulty, reducing the corresponding process cost, avoiding the front surface of the semiconductor device 210 from contacting the deposition chamber and the related structures in the deposition chamber after turning over, avoiding loss and/or pollution to the front surface of the semiconductor device 210, and improving the quality of the related process based on the front surface of the semiconductor device 210.
The polysilicon stress layer may comprise a doped polysilicon layer. Specifically, the polysilicon may be deposited in a furnace tube, where the polysilicon is deposited on both the front and back surfaces, without performing complex operations such as flipping the semiconductor device 210.
The temperature range of depositing the polysilicon stress layer comprises 500-600 ℃, and the aim of improving the warpage can be achieved by utilizing the stress characteristic of the polysilicon at the temperature range of 500-600 ℃; the inventors found through research and have shown through a lot of experimental data that the temperature for depositing the polysilicon stress layer in the above step S120 must be 500-600 degrees, and other temperatures may cause the opposite effects.
Optionally, the thickness range of the polysilicon layer, particularly the thickness range of the polysilicon layer located on the back side of the semiconductor device 210 includes 100a to 32000a, so that the polysilicon layer can apply an appropriate stress to the semiconductor device 210 on the back side of the semiconductor device 210.
And S130, removing the first stress layer 221 positioned on the front surface of the semiconductor device 210 so as to continue other processes on the front surface of the semiconductor device 210 and continue the related processes of the semiconductor device 210.
And S140, forming a contact hole so that the semiconductor device 210 provides conditions for the requirements of access and the like of the subsequent related contact devices, and the subsequent thermal annealing process is not included, so as to maintain the effect of improving the warpage of the semiconductor device 210.
The method for improving the warpage of the discrete device forms the polysilicon stress layer on the front surface and the back surface of the semiconductor device 210 respectively, and can form the second stress layer 222 on the back surface of the semiconductor device 210 by adopting a relatively simple process, so that the second stress layer 222 applies tensile stress to the semiconductor device on the back surface to improve the warpage of the semiconductor device 210, and can avoid forming the polysilicon stress layer on the back surface of the semiconductor device 210 by turning over the form of the semiconductor device 210 in the process of forming the second stress layer 222 on the back surface of the semiconductor device 210, thereby avoiding the relatively complex and difficult process of turning over the semiconductor device 210, reducing the corresponding process cost, avoiding the front surface of the semiconductor device 210 from contacting a deposition chamber and related structures in the deposition chamber after turning over, and avoiding loss and/or pollution to the front surface of the semiconductor device 210; the polysilicon stress layer on the front surface of the semiconductor device 210 is removed, so that other processes are continuously performed on the front surface of the semiconductor device 210 to form structures such as contact holes, and a thermal annealing process is not included in the following processes, so that the warping degree improving effect can be maintained, each process performed has higher quality, and the finally obtained semiconductor device 210 has higher performance.
In one embodiment, the removing the polysilicon stress layer on the front surface of the semiconductor device includes: and removing the polysilicon layer on the front side of the semiconductor device 210 by adopting a CMP process or an etching process (such as a polysilicon back side etching process) to expose the structure of the top layer of the semiconductor device 210, such as the ILD film layer, so as to continuously develop the semiconductor process for the structure of the top layer of the semiconductor device 210.
In one example, the inventors continue to research and find that after the polysilicon is subjected to a high temperature process for a long time above 600 ℃, the effect of stress adjustment of the polysilicon with different temperatures and different thicknesses is counteracted, and the warpage of the wafer returns to the level before adjustment, so that the subsequent process is not improved.
Further, the inventors perform statistical analysis on the warpage characteristics of the semiconductor device 210 during the related process to obtain a warpage characteristic diagram as shown in fig. 3a and 3b, wherein fig. 3a represents the X-direction bending values of the front and back side deposited doped polysilicon, the front side polysilicon removed and the high temperature furnace annealing of the wafer (e.g. the semiconductor device 210), and fig. 3b represents the Y-direction bending values of the front and back side deposited doped polysilicon, the front side polysilicon removed and the high temperature furnace annealing of the wafer. Fig. 3a and 3b show that the polysilicon film layer applies a tensile stress to the wafer on the back surface of the wafer, so that the wafer warpage can be effectively improved, and the wafer is subjected to heat treatment, so that the influence of the polysilicon film layer on the wafer warpage can be weakened or eliminated.
In the method for improving the warpage of the discrete device, the thermal annealing process is not included in the follow-up process, so that the effect of improving the warpage of the discrete device is not influenced by the thermal treatment process, and the effect of improving the warpage of the discrete device can be effectively ensured.
In an example, the method for improving warpage of discrete devices described above may also be described with reference to fig. 4a to 4c, and includes the following processes: as shown in fig. 4a, the surface of the ILD film layer on the top layer of the semiconductor device is uneven, and the ILD film layer is polished flat by a CMP process; as shown in fig. 4b, after the ILD film layer is planarized, polysilicon layers are deposited on the front and back surfaces of the semiconductor device, respectively, where the polysilicon layers are also present on the front surface of the semiconductor device; as shown in fig. 4c, the polysilicon layer on the front side of the semiconductor device is removed, so that the subsequent process is performed based on the ILD film layer on the top layer of the semiconductor device, and then a contact hole is formed, so that the semiconductor device provides conditions for the subsequent requirements of access of related contact devices, and the subsequent thermal annealing process is not included, so as to maintain the effect of improving the warpage of the semiconductor device.
The inventors have studied on semiconductor related processes and found that the stress exhibited by polysilicon layers deposited at different temperatures varies greatly, even inversely. As shown in fig. 3a and fig. 3b, the polysilicon layer is deposited at 525 ℃ and 560 ℃ and the stress is quite opposite after the polysilicon layer on the front surface is removed, so that the problem of positive warpage in the rear section can be solved, only the polysilicon layer deposited in a specific temperature range can be selected, and the purpose of improving the warpage can be achieved by adopting the stress characteristic of polysilicon in the temperature range of 500 ℃ to 600 ℃. In addition, the embodiment has relatively high realizability, has proved to be feasible in engineering products, and has lower cost and safety compared with a solution of depositing polysilicon at the front section and carrying out turn-over etching pattern on a wafer even by matching with other films.
In this embodiment, a certain thickness of polysilicon is deposited on the wafer in a certain temperature range in a certain process step before the ILD back-end connection layer, then the polysilicon on the front surface of the wafer is removed, leaving a polysilicon layer on the back of the wafer, and the stress of the polysilicon layer with a certain thickness left on the back of the wafer is used to adjust the warpage of the back-end of the wafer. And the effect of improving stress of the polysilicon layer deposited at a specific temperature range is achieved in the specific process steps which do not involve the heat treatment process, so that the wafer can normally perform the subsequent process, particularly the subsequent patterning process.
The method for improving the warpage of the discrete device forms the polysilicon stress layer on the front surface and the back surface of the semiconductor device 210 respectively, and can form the second stress layer 222 on the back surface of the semiconductor device 210 by adopting a relatively simple process, so that the second stress layer 222 applies tensile stress to the semiconductor device on the back surface to improve the warpage of the semiconductor device 210, and can avoid forming the polysilicon stress layer on the back surface of the semiconductor device 210 by turning over the form of the semiconductor device 210 in the process of forming the second stress layer 222 on the back surface of the semiconductor device 210, thereby avoiding the relatively complex and difficult process of turning over the semiconductor device 210, reducing the corresponding process cost, avoiding the front surface of the semiconductor device 210 from contacting a deposition chamber and related structures in the deposition chamber after turning over, and avoiding loss and/or pollution to the front surface of the semiconductor device 210; the polysilicon stress layer on the front surface of the semiconductor device 210 is removed, so that other processes are continuously performed on the front surface of the semiconductor device 210 to form structures such as contact holes, and a thermal annealing process is not included in the following processes, so that the warping degree improving effect can be maintained, each process performed has higher quality, and the finally obtained semiconductor device 210 has higher performance.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (4)
1. A method for improving warpage of a discrete device, comprising the steps of:
depositing an ILD film layer on the topmost layer of the semiconductor device, and flattening the ILD film layer by adopting a CMP process;
forming polysilicon stress layers on the front surface and the back surface of the semiconductor device respectively, wherein the temperature range for depositing the polysilicon stress layers comprises 500-600 ℃, and the polysilicon stress layers are used for applying stress to the semiconductor device so as to reduce the warping degree of the semiconductor device;
removing the polysilicon stress layer positioned on the front surface of the semiconductor device;
and forming a contact hole, and subsequently, not comprising a thermal annealing process.
2. The method of improving warpage of a discrete device of claim 1, wherein the polysilicon stress layer on the back side of the semiconductor device applies a tensile stress to the semiconductor device.
3. The method of claim 1, wherein the thickness of the polysilicon stress layer ranges from 100a to 32000a.
4. The method of claim 1, wherein the removing the polysilicon stress layer on the front side of the semiconductor device comprises:
and removing the polysilicon layer positioned on the front surface of the semiconductor device by adopting a CMP process or an etching process.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118231347A (en) * | 2024-05-22 | 2024-06-21 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
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| CN114284133A (en) * | 2021-12-21 | 2022-04-05 | 华虹半导体(无锡)有限公司 | Method for improving sheet warping |
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Patent Citations (4)
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| KR19980060898A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Method for manufacturing field oxide film of semiconductor device |
| JP2001007099A (en) * | 1999-06-22 | 2001-01-12 | Mitsumi Electric Co Ltd | Manufacturing semiconductor substrate and semiconductor substrate |
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