CN117198348A

CN117198348A - Semiconductor memory and control method

Info

Publication number: CN117198348A
Application number: CN202210600408.7A
Authority: CN
Inventors: 丁小雪; 黄炜
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2023-12-08

Abstract

The application provides a semiconductor memory and a control method, the semiconductor memory comprises a word line driving module, a read-write module and a detection module, wherein the word line driving module comprises a plurality of first word line driving circuits, each first word line driving circuit is connected with a first word line, the read-write module writes first storage data in a storage unit connected with one first word line in the plurality of first word lines connected with the word line driving module, writes second storage data with opposite level to the first storage data in the storage units connected with the remaining first word lines, reads the storage units connected with the remaining first word lines when one first word line is activated, the detection module obtains a first target storage unit of the first storage data from which the second storage data in the storage units connected with the remaining first word line are reversely written, and determines that the first word line driving circuit corresponding to the first target word line has defects, thereby effectively detecting the defects in the word line driving circuit in a chip test stage and improving the product yield.

Description

Semiconductor memory and control method

Technical Field

The present application relates to the field of semiconductor memories, and more particularly, to a semiconductor memory and a control method thereof.

Background

The memory comprises a word line driving circuit (sub-wordline driver SWD), and the word line driving circuit outputs a high level signal or a low level signal to a memory cell in the memory through a word line, so that the read-write operation of the memory cell is realized.

Since the manufacturing process of the memory includes etching, deposition, etc., the word line driving circuit in the memory may have defects, which cannot be effectively detected in the chip (chip) testing stage, and the product yield is affected.

Disclosure of Invention

The application provides a semiconductor memory and a control method thereof, which are used for effectively detecting defects in a word line driving circuit in a chip test stage and improving the product yield.

A first aspect of the present application provides a semiconductor memory comprising:

a word line driving module including a plurality of first word line driving circuits, each of the first word line driving circuits being connected to one of the first word lines;

the read-write module is used for writing first storage data into the storage units connected with one first word line in the plurality of first word lines, writing second storage data into the storage units connected with the rest first word lines, and reading the storage units connected with the rest first word lines when the one first word line is activated, wherein the levels of the first storage data and the second storage data are opposite;

The detection module is used for acquiring a first target storage unit of which second storage data is rewritten into first storage data and a first target word line connected with the first target storage unit, and determining that a first word line driving circuit connected with the first target word line has defects.

In some embodiments, the first word line driving circuits to which even first word lines are connected are located at a first end of the first word lines, and the first word line driving circuits to which odd first word lines are connected are located at a second end of the first word lines;

the read-write module is used for reading the memory cells connected with the rest of the even first word lines when one of the even first word lines is activated, and reading the memory cells connected with the rest of the odd first word lines when one of the odd first word lines is activated.

In some embodiments, each first word line driver circuit is provided with an input terminal and an output terminal;

the input end of each first word line driving circuit is connected with a first main word line and is used for receiving an input signal sent by the first main word line;

the output end of each first word line driving circuit is connected with the corresponding first word line.

In some embodiments, each first word line driver circuit is provided with a first end and a second end;

The first end of each first word line driving circuit is connected with a corresponding first power supply end, and the first power supply end is used for providing a first voltage or a second voltage for the corresponding first word line driving circuit;

the second end of each first word line driving circuit is connected with a corresponding second power supply end, and the second power supply end is used for providing a third voltage for the corresponding first word line driving circuit;

the first voltage is greater than the second voltage, which is greater than the third voltage.

In some embodiments, each of the first word line driving circuits includes a first P-type transistor, a first N-type transistor, and a second N-type transistor;

the grid electrode of the first P-type transistor and the grid electrode of the first N-type transistor are connected with each other to serve as the input end of a corresponding first word line driving circuit;

the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected with each other to serve as the output end of the corresponding first word line driving circuit;

the second pole of the first P-type transistor is used as the first end of the corresponding first word line driving circuit, and the second pole of the first N-type transistor is used as the second end of the corresponding first word line driving circuit;

the grid electrode of the second N-type transistor is connected with a corresponding control signal end, the first electrode of the second N-type transistor is connected with the first electrode of the first N-type transistor, the second electrode of the second N-type transistor is connected with the second electrode of the first N-type transistor, and the control signal end is used for providing a control signal.

In some embodiments, the first voltage is greater than a first preset value and the second voltage is greater than a second preset value.

In some embodiments, the word line driving module further comprises: a plurality of second word line driving circuits, each of which is connected to one of the second word lines;

the read-write module is further used for writing second storage data into the storage units connected with one second word line in the plurality of second word lines, writing first storage data into the storage units connected with the rest second word lines, and reading the storage units connected with the rest second word lines when the one second word line is activated;

the detection module is further used for acquiring a second target storage unit, in which the first storage data is rewritten into second storage data, and a second target word line connected with the second storage unit, and determining that a second word line driving circuit connected with the second target word line has defects.

In some embodiments, each second word line driver circuit is provided with an input terminal and an output terminal;

the input end of each second word line driving circuit is connected with a second main word line and is used for receiving an input signal sent by the second main word line;

the output end of each second word line driving circuit is connected with the corresponding second word line.

In some embodiments, each of the second word line driving circuits is provided with a third terminal and a fourth terminal;

the third end of each second word line driving circuit is connected with a corresponding first power supply end, and the first power supply end is used for providing a first voltage or a second voltage for the corresponding second word line driving circuit;

the fourth end of each second word line driving circuit is connected with a corresponding second power supply end, and the second power supply end is used for providing a third voltage for the corresponding second word line driving circuit;

In some embodiments, each of the second word line driving circuits includes a second P-type transistor, a third N-type transistor, and a fourth N-type transistor;

the grid electrode of the second P-type transistor and the grid electrode of the third N-type transistor are connected with each other to serve as the input end of a corresponding second word line driving circuit;

the first pole of the second P-type transistor and the first pole of the third N-type transistor are connected with each other to serve as the output end of the corresponding second word line driving circuit;

a second pole of the second P-type transistor is used as a third end of a corresponding second word line driving circuit, and a second pole of the third N-type transistor is used as a fourth end of the corresponding second word line driving circuit;

The grid electrode of the fourth N-type transistor is connected with a corresponding control signal end, the first electrode of the fourth N-type transistor is connected with the first electrode of the third N-type transistor, the second electrode of the fourth N-type transistor is connected with the second electrode of the third N-type transistor, and the control signal end is used for providing a control signal.

In some embodiments, further comprising: a sense amplifier;

the sense amplifier is connected with a bit line and a complementary bit line of each memory cell and is used for amplifying the stored data of the memory cell.

In a second aspect, the present application provides a method for controlling a semiconductor memory according to the first aspect and any one of the possible designs of the first aspect, including:

writing first storage data into a storage unit connected with one first word line in a plurality of first word lines corresponding to the row word line driving module, and writing second storage data into storage units connected with the rest first word lines, wherein the levels of the first storage data and the second storage data are opposite;

reading memory cells connected to the remaining first word lines while activating the one first word line;

and acquiring a first target memory cell of which the second memory data is rewritten into first memory data, and a first target word line connected with the first target memory cell, and determining that a first word line driving circuit connected with the first target word line has defects.

In some embodiments, the reading the memory cells connected to the remaining first word lines when the one first word line is activated specifically includes:

activating the first word line for a first preset number of times, and reading the memory cells connected with the remaining first word lines during each activation;

the first target storage unit for acquiring the second storage data and being rewritten into the first storage data specifically includes:

and acquiring a first target storage unit of which the second storage data is rewritten into the first storage data for a second preset number of times.

activating one of the even first word lines, and reading the memory cells connected with the rest first word lines in the even first word lines;

and/or activating one of the odd first word lines, and reading the memory cells connected with the rest first word lines in the odd first word lines.

In some embodiments, the activating one of the even first word lines, reading the memory cells connected to the remaining first word lines in the even first word lines, and/or activating one of the odd first word lines, reading the memory cells connected to the remaining first word lines in the odd first word lines specifically includes:

Reading the memory cells connected with the remaining first word lines in the even first word lines when a first power supply end connected with a first word line driving circuit corresponding to one first word line in the even first word lines supplies a first voltage to the one first word line;

and/or when the first power supply end connected with the first word line driving circuit corresponding to one of the odd first word lines supplies a first voltage to the first word line, reading the memory cells connected with the rest first word lines in the odd first word lines.

In some embodiments, activating one of the even first word lines, reading the memory cells connected to the remaining first word lines in the even first word lines, and/or activating one of the odd first word lines, reading the memory cells connected to the remaining first word lines in the odd first word lines, specifically includes:

activating one of the even first word lines, and reading the memory cells connected with the remaining first word lines in the even first word lines when the third N-type transistor in the first word line driving circuit connected with the remaining first word lines in the even first word lines is conducted under the action of the control voltage provided by the corresponding control signal end;

And/or activating one first word line in the odd first word lines, and reading the memory cells connected with the remaining first word lines in the odd first word lines when the third N-type transistor in the first word line driving circuit connected with the remaining first word lines in the odd first word lines is conducted under the action of the control voltage provided by the corresponding control signal end.

In some embodiments, the method further comprises:

writing second storage data into a storage unit connected with one second word line in a plurality of second word lines corresponding to the word line driving module, and writing first storage data into storage units connected with the rest second word lines;

reading memory cells connected to the remaining second word lines while activating the one second word line;

and acquiring a second target memory cell of which second memory data is rewritten into first memory data, and a second target word line connected with the second target memory cell, and determining that a second word line driving circuit connected with the second target word line has defects.

and after the first preset time of the first word line is activated, reading the memory cells connected with the rest first word lines.

The application provides a semiconductor memory, which comprises a word line driving module, a read-write module and a detection module, wherein the word line driving module comprises a plurality of first word line driving circuits, each first word line driving circuit is connected with a first word line, the read-write module writes first storage data in a storage unit connected with one first word line in the plurality of first word lines connected with the word line driving module, writes second storage data with opposite level to the first storage data in the storage unit connected with the remaining first word line, reads the storage unit connected with the remaining first word line when one first word line is activated, and the detection module acquires a first target storage unit of which the second storage data in the storage unit connected with the remaining first word line is rewritten into the first storage data, so that the first word line driving circuit corresponding to the first target word line has defects.

Drawings

In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a circuit diagram of a semiconductor memory according to an embodiment of the present application;

FIG. 2 is a circuit diagram of a semiconductor memory according to an embodiment of the present application;

FIG. 3 is a circuit diagram of a first word line driving circuit according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a semiconductor memory according to an embodiment of the present application;

FIG. 5 is a circuit diagram of a second word line driving circuit according to an embodiment of the present application;

FIG. 6 is a circuit diagram of a sense amplifier according to an embodiment of the present application;

fig. 7 is a flowchart of a control method of a semiconductor memory according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Fig. 1 is a circuit diagram of a semiconductor memory according to an embodiment of the present application. As shown in fig. 1, an embodiment of the present application provides a semiconductor memory, which includes a word line driving module 102, a read/write module 101, and a detection module 103. The word line driving module 102 includes a plurality of first word line driving circuits, each of which is connected to one first word line, and each of which transmits a high level signal or a low level signal to the corresponding first word line to enable or disable the read/write operation of the bit line on the memory cell. Since each first word line driving circuit is connected to one first word line, the word line driving module 102 is connected to a plurality of first word lines, writes first memory cells into memory cells connected to one first word line of the plurality of first word lines, writes second memory data into memory cells connected to the remaining first word lines of the plurality of first word lines, the second memory data is opposite in level to the first memory data, and reads the memory cells connected to the remaining first word lines when one first word line is activated. The detection module 103 is connected with the read-write module 101, acquires a read result of the read-write module 101, acquires a first target storage unit of the second storage data which is reversely written as the first storage data, namely acquires the first target storage unit from the storage data units connected with the remaining first word lines, acquires the first target word line connected with the first target storage unit, and determines that a first word line driving circuit connected with the first target word line has a defect.

Note that one first word line to which the memory cell writing the first stored data is connected may be any one of a plurality of first word lines, and for convenience of description, this one first word line is referred to as a first selected word line.

The first word line driving circuit connected to the first selected word line has a defect with the first word line driving circuit connected to the first target word line. For example, the first selected word line is shorted to the first target word line. When the first selected word line is turned on and the first target word line is turned off, the first selected word line receives a high level signal, resulting in a voltage rise of the first target word line, which cannot be completely turned off. And because the first selected word line and the first target word line share the same bit line, the high-potential charge of the memory cell connected with the first selected word line enters the memory cell connected with the first target word line through the bit line, so that the second memory data in the first target word line is rewritten into the first memory data.

For example, the first power supply terminal FXT of the first word line driving circuit connected to the first selected word line is short-circuited to the first target word line. The first selected word line is turned on and the first target word line is turned off, and the first power supply terminal FXT supplies a high voltage to the first selected word line, resulting in a voltage rise of the first target word line, which cannot be completely turned off. The first selected word line and the first target word line share the same bit line, and high-level charges of the memory cells connected with the first selected word line enter the memory cells connected with the first target word line through the bit line, so that second stored data in the first target word line are rewritten into first stored data.

For another example, the control signal terminal FXB of the third N-type transistor N3 in the first word line driving circuit connected to the first target word line is short-circuited to the first target word line. Since the first target word line tends to be turned off when the first power supply terminal FXT supplies the second voltage VSS, but cannot be turned off completely, the control signal terminal FXB of the third N-type transistor N3 needs to supply the high voltage to turn on the third N-type transistor N3, so that the first target word line is connected to the second power supply terminal VKK, and the first target word line is turned off completely under the action of the third voltage supplied by the second power supply terminal VKK. However, since the control signal terminal FXB of the third N-type transistor N3 in the first word line driving circuit connected to the first target word line is shorted to the first target word line, the voltage of the first target word line rises and cannot be completely turned off, and when the first selected word line is turned on, the high-level charge of the memory cell connected to the first selected word line enters the memory cell connected to the first target word line through the bit line, so that the second memory data in the first target word line is rewritten into the first memory data.

Thus, if the second storage data in the first target word line is rewritten to the first storage data, the first word line driving circuit to which the first target word line is connected has a defect.

As shown in fig. 1, the word line driving module 102 includes eight first word line driving circuits, respectively denoted as SWD0, SWD1, SWD2, SWD3, SWD4, SWD5, SWD6, and SWD7, each of which is connected to one first word line, SWD0 connection WL0, SWD1 connection WL1, SWD2 connection WL2, SWD3 connection WL3, SWD4 connection WL4, SWD5 connection WL5, SWD6 connection WL6, and SWD7 connection WL7, and the word line driving module 102 connects eight first word lines.

Referring to table 1, the first selected word line is WL0, the remaining first word lines are WL1 to WL7, and if the first memory data is written into the memory cells connected to WL0 and the second memory data is written into the memory cells connected to WL1 to WL7, the memory data in the memory cells connected to WL1 to WL7 are read when WL0 is activated. The first stored data is for example 1 and the second stored data is for example 0. Then, the detection module 103 obtains a first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL1-WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 1

BG	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	1	0	0	0	0	0	0	0
BL1	1	0	0	0	0	0	0	0
									BL2	1	0	0	0	0	0	0	0
BL3	1	0	0	0	0	0	0	0
									BL4	1	0	0	0	0	0	0	0
BL5	1	0	0	0	0	0	0	0
									BL6	1	0	0	0	0	0	0	0
BL7	1	0	0	0	0	0	0	0

Referring to table 2, the first selected word line is WL1, the remaining first word lines are WL0 and WL2 to WL7, and if the first memory data is written into the memory cells connected to WL1 and the second memory data is written into the memory cells connected to WL0 and WL2 to WL7, the memory data in the memory cells connected to WL0 and WL2 to WL7 are read when WL1 is activated. Then, the detection module 103 obtains the first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL0 and WL2-WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 2

Referring to table 3, the first selected word line is WL2, the remaining first word lines are WL0, WL1 and WL3 to WL7, and if the first memory data is written in the memory cells connected to WL2 and the second memory data is written in the memory cells connected to WL0, WL1 and WL3 to WL7, the memory data in the memory cells connected to WL0, WL1 and WL3 to WL7 are read when WL2 is activated. Then, the detection module 103 obtains the first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL0, WL1, and WL3-WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 3 Table 3

BG	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	1	0	0	0	0	0
BL1	0	0	1	0	0	0	0	0
									BL2	0	0	1	0	0	0	0	0
BL3	0	0	1	0	0	0	0	0
									BL4	0	0	1	0	0	0	0	0
BL5	0	0	1	0	0	0	0	0
									BL6	0	0	1	0	0	0	0	0
BL7	0	0	1	0	0	0	0	0

Referring to Table 4, the first selected word line is WL3, the remaining first word lines are WL0-WL2 and WL4-WL7, and if the first memory data is written into the memory cells connected to WL3 and the second memory data is written into the memory cells connected to WL0-WL2 and WL4-WL7, the memory data in the memory cells connected to WL0-WL2 and WL4-WL7 are read when WL3 is activated. Then, the detection module 103 obtains the first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL0-WL2 and WL4-WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 4 Table 4

Referring to Table 5, the first selected word line is WL4, the remaining first word lines are WL0-WL3 and WL5-WL7, and if the first memory data is written into the memory cells connected to WL4 and the second memory data is written into the memory cells connected to WL0-WL3 and WL5-WL7, the memory data in the memory cells connected to WL0-WL3 and WL5-WL7 are read when WL4 is activated. Then, the detection module 103 obtains the first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL0-WL3 and WL5-WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 5

BG	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	1	0	0	0
BL1	0	0	0	0	1	0	0	0
									BL2	0	0	0	0	1	0	0	0
BL3	0	0	0	0	1	0	0	0
									BL4	0	0	0	0	1	0	0	0
BL5	0	0	0	0	1	0	0	0
									BL6	0	0	0	0	1	0	0	0
BL7	0	0	0	0	1	0	0	0

Referring to table 6, the first selected word line is WL5, the remaining first word lines are WL0 to WL4, WL6 and WL7, and if the first memory data is written in the memory cells connected to WL5 and the second memory data is written in the memory cells connected to WL0 to WL4, WL6 and WL7, the memory data in the memory cells connected to WL0 to WL4, WL6 and WL7 are read when WL5 is activated. Then, the detection module 103 obtains a first target memory cell, in which the second memory data is rewritten into the first memory data, from among the memory cells connected to WL0-WL4, WL6, and WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 6

Referring to Table 7, the first selected word line is WL6, the remaining first word lines are WL0-WL5 and WL7, and if the first memory data is written into the memory cells connected to WL6 and the second memory data is written into the memory cells connected to WL0-WL5 and WL7, the memory data in the memory cells connected to WL0-WL5 and WL7 are read when WL6 is activated. Then, the detection module 103 obtains the first target memory cell, in which the second memory data is rewritten into the first memory data, from the memory cells connected to WL0-WL5 and WL7, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 7

BG	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	1	0
BL1	0	0	0	0	0	0	1	0
									BL2	0	0	0	0	0	0	1	0
BL3	0	0	0	0	0	0	1	0
									BL4	0	0	0	0	0	0	1	0
BL5	0	0	0	0	0	0	1	0
									BL6	0	0	0	0	0	0	1	0
BL7	0	0	0	0	0	0	1	0

Referring to Table 8, the first selected word line is WL7, the remaining first word lines are WL0-WL6, and if the first memory data is written into the memory cells connected to WL7 and the second memory data is written into the memory cells connected to WL0-WL6, the memory data in the memory cells connected to WL0-WL6 are read when WL7 is activated. Then, the detection module 103 obtains the first target memory cell, which is the first memory data, from the memory cells connected to WL0-WL6, and the first word line driving circuit corresponding to the first target word line connected to the first target memory cell has a defect.

TABLE 8

BG	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	1
BL1	0	0	0	0	0	0	0	1
									BL2	0	0	0	0	0	0	0	1
BL3	0	0	0	0	0	0	0	1
									BL4	0	0	0	0	0	0	0	1
BL5	0	0	0	0	0	0	0	1
									BL6	0	0	0	0	0	0	0	1
BL7	0	0	0	0	0	0	0	1

In some embodiments, first word line driving circuits connecting adjacent first word lines are respectively arranged at two ends of the first word lines to simplify the process and reduce the short circuit condition of the device. The first word line driving circuits connected with the even first word lines are located at the first ends of the first word lines, the first word line driving circuits connected with the odd first word lines are located at the second ends of the first word lines, and as shown in fig. 1, the even first word lines comprise WL0, WL2, WL4 and WL6, wherein SWD0 connected with WL0, SWD2 connected with WL2, SWD4 connected with WL4, and SWD6 connected with WL6 are located at the first ends of the first word lines. The odd first word lines include WL1, WL3, WL5 and WL7, wherein SWD1 connected by WL1, SWD3 connected by WL3, SWD5 connected by WL5, and SWD7 connected by WL7 are located at the second ends of the first word lines, and since the eight first word lines are sequentially arranged, the first ends of the first word lines may be understood as first ends of the eight first word lines, and the second ends of the first word lines may be understood as second ends of the eight first word lines.

Since the first word line driving circuits connected to the even first word lines are located at the same side, the first word line driving circuits connected to the odd first word lines may be short-circuited between the first word line driving circuits connected to the even first word lines, and the short-circuited between the first word line driving circuits connected to the odd first word lines may be generated. Thus, the read-write module reads the memory cells connected to the remaining first word lines of the even first word lines when one of the even first word lines is activated, and reads the memory cells connected to the remaining first word lines of the odd first word lines when one of the odd first word lines is activated. For example, WL0 is on, WL2, WL4, WL6 are off, and WL2 connected memory cell, WL4 connected memory cell, and WL6 connected memory cell are read when WL0 is activated. For example, WL1 is on, WL0, WL4, WL6 are off, and WL0 connected memory cell, WL4 connected memory cell, and WL6 connected memory cell are read when WL1 is activated.

In some embodiments, to further determine that the first word line driving circuit has a defect, after determining that the first word line driving circuit corresponding to the first target word line has a defect, the memory cells in the memory array may be refreshed, the first memory data may be written in the memory cells connected to the first target word line, and the second memory data may be written in other first word lines than the first target word line. And opening the first target word line, closing other first word lines, and further determining that the first word line driving circuit connected with the first target word line has defects if the condition of reverse writing of stored data occurs in the memory cells connected with the other first word lines.

As an implementation manner, the first storage data can be written into each first word line in sequence according to the arrangement sequence of the first word lines, and the storage data in the storage unit can be read once every time the first storage data is written, so that detection of all the first word line driving circuits is completed. As shown in tables 1-8, first storage data is written in WL0, second storage data is written in WL1-WL7, WL0 is turned on, WL1-WL7 is turned off, and storage units connected with WL1-WL7 are read; then, refreshing (REF) each memory cell, writing first memory data in WL1, writing second memory data in WL0 and WL2-WL7, turning on WL1 to turn off WL0 and WL2-WL7, and reading memory cells connected with WL0 and WL2-WL 7; and so on until the first storage data is written in the WL7, the second storage data is written in the WL0-WL6, the WL7 is turned on, the WL0-WL6 is turned off, and the storage units connected with the WL0-WL6 are read. Each time, writing data into the memory cells in the whole memory array by a Y-direction writing operation mode (Y-Page Write), for example, firstly starting WL0, and after the corresponding memory cells on WL0 are sequentially written, closing WL0; starting WL1, and after the corresponding memory cells on WL1 are sequentially written, turning off WL1; and so on until the corresponding memory cell on WL7 is written. The time to refresh each memory cell may be 16ms to 200ms.

Fig. 2 is a circuit diagram of a semiconductor memory according to an embodiment of the present application. As shown in fig. 2, an input terminal of each first word line driving circuit is connected to the first main word line MWL0, and is configured to receive an input signal provided by the first main word line MWL0, and an output terminal of each first word line driving circuit is connected to a corresponding first word line. For example, SWD0 has its input terminal connected to the first main word line MWL0 and SWD0 has its output terminal connected to WL0; an input end of SWD1 is connected with the first main word line MWL0, and an output end of SWD1 is connected with WL1; an input end of the SWD2 is connected with the first main word line MWL0, and an output end of the SWD2 is connected with the WL2; an input end of the SWD3 is connected with the first main word line MWL0, and an output end of the SWD3 is connected with the WL3; an input end of the SWD4 is connected with the first main word line MWL0, and an output end of the SWD4 is connected with the WL4; an input end of SWD5 is connected with the first main word line MWL0, and an output end of SWD5 is connected with WL5; an input end of the SWD6 is connected with the first main word line MWL0, and an output end of the SWD6 is connected with the WL6; an input terminal of SWD7 is connected to the first main word line MWL0, and an output terminal of SWD7 is connected to WL7.

The first end of each first word line driving circuit is connected with a corresponding first power supply end, the first power supply end provides a first voltage VPP or a second voltage VSS for the corresponding first word line driving circuit, the first voltage VPP is larger than the second voltage VSS, the first voltage VPP is high voltage, for example, the first voltage can be 3.7V, and the second voltage VSS is low voltage, so that a high level signal or a low level signal can be provided for the corresponding word line. The second end of each first word line driving circuit is connected with a corresponding second power supply end, the second power supply end provides a third voltage for the corresponding first word line, the third voltage is lower than the second voltage VSS, the third voltage can be-0.1V, for example, so that a low-level signal is provided for the corresponding first word line, and the corresponding first word line is effectively closed. For example, a first end of SWD0 is connected to FXT0 and a second end of SWD0 is connected to VKK0; the first end of SWD1 is connected with FXT1, and the second end of SWD1 is connected with VKK1; the first end of SWD2 is connected with FXT2, and the second end of SWD2 is connected with VKK2; the first end of SWD3 is connected with FXT3, and the second end of SWD3 is connected with VKK3; the first end of SWD4 is connected with FXT4, and the second end of SWD4 is connected with VKK4; a first end of SWD5 is connected with FXT5, and a second end of SWD5 is connected with VKK5; a first end of SWD6 is connected with FXT6, and a second end of SWD6 is connected with VKK6; the first end of SWD7 is connected to FXT7 and the second end of SWD7 is connected to VKK7. The first power supply terminal of each first word line driving circuit may supply the same or different first voltage VPP, or may supply the same or different second voltage VSS, and the second power supply terminal of each first word line driving circuit may supply the same or different third voltage. As an implementation manner, the first voltage VPP may be greater than a first preset value, so as to increase the voltage for turning on the word line, strengthen the current at the defective position, and better induce the word line connected to the defective first word line driving circuit to be turned on, so as to increase the speed of writing back the stored data. The second voltage VSS may be greater than a second preset value, so that the second voltage VSS is greater than the third voltage VKK, so that the corresponding word line tends to be turned off, so that the word line connected to the defective first word line driving circuit is easily brought open, and the speed of writing back the stored data is increased.

Fig. 3 is a circuit diagram of a first word line driving circuit according to an embodiment of the application. As shown in fig. 3, the first word line driving circuit includes two NMOS transistors and one PMOS transistor, and the gate of the first N-type transistor N1 and the gate of the first P-type transistor P1 are connected to each other as an input terminal of the first word line driving circuit, and the input terminal of the first word line driving circuit is connected to the first main word line MWL0 for receiving an input signal provided by the first main word line WML 0. The first pole of the first P-type transistor P1 and the first pole of the first N-type transistor N1 are connected to each other as an output terminal of the first word line driving circuit, the output terminal of the first word line driving circuit is connected to a corresponding word line, and the first word line driving circuit outputs a high level signal or a low level signal to the corresponding word line under the action of an input signal. The second pole of the first P-type transistor P1 is used as the first end of the corresponding first word line driving circuit, connected with the corresponding first power supply end FXT, and the second end of the first N-type transistor N1 is used as the second end of the corresponding first word line driving circuit, connected with the corresponding second power supply end VKK.

The gate of the second N-type transistor N2 is connected to a corresponding control signal terminal FXB, and the control signal terminal FXB provides a control signal to the corresponding second N-type transistor N2, where the control signal may be a high level signal. For example, the second N-type transistor N2 in SWD0 is connected to FXB0, the second N-type transistor N1 in SWD1 is connected to FXB1, the second N-type transistor N2 in SWD2 is connected to FXB2, the second N-type transistor N2 in SWD3 is connected to FXB3, the second N-type transistor N2 in SWD4 is connected to FXB4, the second N-type transistor N2 in SWD5 is connected to FXB5, the second N-type transistor N2 in SWD6 is connected to FXB6, and the second N-type transistor N2 in SWD7 is connected to FXB7. The first pole of the second N-type transistor N2 is connected with the first pole of the first N-type transistor N1, and the second pole of the second N-type transistor N2 is connected with the second pole of the first N-type transistor.

When the input signal provided by the first main word line WML0 is a low level signal, the first N-type transistor N1 is turned off, the first P-type transistor P1 is turned on, the first power supply terminal FXT provides the first voltage VPP or the second voltage VSS to the corresponding word line, when the first power supply terminal FXT provides the first voltage VPP to the corresponding word line, the corresponding word line tends to be turned off, but cannot be completely turned off, and thus a control signal needs to be sent to the gate of the second N-type transistor N2 through the control signal terminal FXB, and the second N-type transistor N2 is turned on under the action of the control signal, so that the second power supply terminal VKK provides the third voltage to the corresponding word line, thereby completely turning off the corresponding word line. When the input signal provided by the first main word line MWL0 is a high level signal, the first P-type transistor P1 is turned off, the first N-type transistor N1 is turned on, the second power supply end VKK provides a third voltage to the corresponding word line, the corresponding word line is turned off, and meanwhile, a control signal can be sent to the gate of the corresponding second N-type transistor N2 through the control signal end FXB, and the speed of completely turning off the corresponding word line is increased by the second N-type transistor N2 under the action of the control signal.

Fig. 4 is a circuit diagram of a semiconductor memory according to an embodiment of the present application. As shown in fig. 4, the word line driving module 102 includes a plurality of first word line driving circuits each connected to one first word line and a plurality of second word line driving circuits each connected to a second word line. The read-write module 101 writes second storage data in a storage unit connected to one of the plurality of second word lines connected to the word line driving module 102, and writes first storage data in a storage unit connected to the remaining second word lines of the plurality of second word lines, where the storage data in the storage unit connected to the first word line is different from the storage data in the storage unit connected to the second word line, so that the storage data of a storage unit corresponding to a first word line connected to an adjacent first word line driving circuit is different from the storage data of a storage unit corresponding to a second word line connected to the second word line driving circuit, so that the defective first word line driving circuit and/or second word line driving circuit can be accurately acquired later. The read/write module 101 reads the memory cells connected to the remaining second word line when one second word line is activated. The detection module 103 obtains second target memory cells, which are connected with the remaining second word lines and in which the first memory data is rewritten into the second memory data, and determines that a second word line driving circuit corresponding to the second target word line connected with the second target memory cells has a defect.

Note that one of the second word lines to which the memory cells for writing the second stored data are connected may be any one of the plurality of second word lines, and for convenience of description, this one of the second word lines is referred to as a second selected word line.

If the first storage data in the second target word line is rewritten into the second storage data, the second word line driving circuit to which the second target word line is connected has a defect.

The word line driving module 102 may further include a plurality of third word line driving circuits, a plurality of fourth word line driving circuits, and the like, and is not limited thereto, and the memory data in the memory array connected to the word lines corresponding to the two adjacent sets of word line driving circuits may be different.

As shown in fig. 4, the word line driving module 102 includes eight first word line driving circuits, which are respectively denoted as SW0, SWD1, SW2, SWD3, SWD4, SWD5, SWD6, SWD7, and eight second word line driving circuits, which are respectively denoted as SW8, SWD9, SW10, SWD11, SWD12, SWD13, SWD14, SWD15. Each first word line driving circuit is connected with one first word line, SWD0 connection WL0, SWD1 connection WL1, SWD2 connection WL2, SWD3 connection WL3, SWD4 connection WL4, SWD5 connection WL5, SWD6 connection WL6, SWD7 connection WL7, each second word line driving circuit is connected with one second word line, SWD8 connection WL8, SWD9 connection WL9, SWD10 connection WL10, SWD11 connection WL11, SWD12 connection WL12, SWD13 connection WL13, SWD14 connection WL14, SWD15 connection WL15, and then the word line driving module 102 connects eight first word lines and eight second word lines.

Referring to Table 9, the first selected word line is WL0, the remaining first word lines are WL1-WL7, the second selected word line is WL8, and the remaining second word lines are WL9-WL15. First storage data are written into storage units connected with WL0, second storage data are written into storage units connected with WL1-WL7, second storage data are written into storage units connected with WL8, and first storage data are written into storage units connected with WL9-WL15.WL0 and WL8 may be activated simultaneously, the stored data in the memory cells connected to WL1-WL7, and the stored data in the memory cells connected to WL9-15 are read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL1-WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL9-WL15. The first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

TABLE 9

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
1	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
																	2	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
3	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
																	4	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
5	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
																	6	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
7	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1

Referring to Table 10, the first selected word line is WL1, the remaining first word lines are WL0 and WL2-WL7, the second selected word line is WL9, and the remaining second word lines are WL8 and W10-WL15. First storage data are written into storage units connected with WL1, second storage data are written into storage units connected with WL0 and WL2-WL7, second storage data are written into storage units connected with WL9, and first storage data are written into storage units connected with WL8 and W10-WL15.WL1 and WL9 may be activated simultaneously, and the memory data in the memory cells connected to WL0 and WL2-WL7, and the memory data in the memory cells connected to WL8 and W10-WL15 may be read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0 and WL2-WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8 and W10-WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

Table 10

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
1	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
																	2	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
3	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
																	4	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
5	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1
																	6	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1

Referring to Table 11, the first selected word line is WL2, the remaining first word lines are WL0, WL1 and WL3-WL7, the second selected word line is WL10, and the remaining second word lines are WL8, WL9 and W11-WL15. First storage data are written into storage units connected with WL2, second storage data are written into storage units connected with WL0, WL1 and WL3-WL7, second storage data are written into storage units connected with WL10, and first storage data are written into storage units connected with WL8, WL9 and W11-WL15.WL2 and WL10 may be activated simultaneously, the stored data in the memory cells connected to WL0, WL1 and WL3-WL7, and the stored data in the memory cells connected to WL8, WL9 and W11-WL15 are read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0, WL1, and WL3-WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8, WL9, and W11-WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

TABLE 11

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
1	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
																	2	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
3	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
																	4	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
5	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1
																	6	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	1

Referring to Table 12, the first selected word line is WL3, the remaining first word lines are WL0-WL2 and WL4-WL7, the second selected word line is WL11, and the remaining second word lines are WL8-WL10 and W12-WL15. First storage data are written into storage units connected with WL3, second storage data are written into storage units connected with WL0-WL2 and WL4-WL7, second storage data are written into storage units connected with WL11, and first storage data are written into storage units connected with WL8-WL10 and W12-WL15.WL3 and WL11 may be activated simultaneously, the memory data in the memory cells connected to WL0-WL2 and WL4-WL7, and the memory data in the memory cells connected to WL8-WL10 and W12-WL15 are read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0-WL2 and WL4-WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8-WL10 and W12-WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

Table 12

Referring to Table 13, the first selected word line is WL4, the remaining first word lines are WL0-WL3 and WL5-WL7, the second selected word line is WL12, and the remaining second word lines are WL8-WL11 and W13-WL15. First storage data are written into storage units connected with WL4, second storage data are written into storage units connected with WL0-WL3 and WL5-WL7, second storage data are written into storage units connected with WL12, and first storage data are written into storage units connected with WL8-WL11 and W13-WL15.WL4 and WL12 may be activated simultaneously, the stored data in the memory cells connected to WL0-WL3 and WL5-WL7, and the stored data in the memory cells connected to WL8-WL11 and W13-WL15 are read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0-WL3 and WL5-WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8-WL11 and W13-WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

TABLE 13

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
1	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
																	2	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
3	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
																	4	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
5	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1
																	6	0	0	0	0	1	0	0	0	1	1	1	1	0	1	1	1

Referring to Table 14, the first selected word line is WL5, the remaining first word lines are WL0-WL4 and WL6, WL7, the second selected word line is WL13, and the remaining second word lines are WL8-WL12 and W14, WL15. First storage data are written into storage units connected with WL5, second storage data are written into storage units connected with WL0-WL4, WL6 and WL7, second storage data are written into storage units connected with WL13, and first storage data are written into storage units connected with WL8-WL12, W14 and WL15.WL5 and WL13 may be activated simultaneously, and the stored data in the memory cells connected to WL0-WL4 and WL6, WL7, and the stored data in the memory cells connected to WL8-WL12 and W14, WL15 may be read. Then, the detection module 103 obtains the first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0-WL4 and WL6, WL7, and obtains the second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8-WL12 and W14, WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

TABLE 14

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
1	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
																	2	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
3	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
																	4	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
5	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1
																	6	0	0	0	0	0	1	0	0	1	1	1	1	1	0	1	1

Referring to Table 15, the first selected word line is WL6, the remaining first word lines are WL0-WL5 and WL7, the second selected word line is WL14, and the remaining second word lines are WL8-WL13 and WL15. First storage data are written into storage units connected with WL6, second storage data are written into storage units connected with WL0-WL5 and WL7, second storage data are written into storage units connected with WL14, and first storage data are written into storage units connected with WL8-WL13 and WL15.WL6 and WL14 may be activated simultaneously, and the memory data in the memory cells connected to WL0-WL5 and WL7, and the memory data in the memory cells connected to WL8-WL13 and WL15 may be read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0-WL5 and WL7, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8-WL13 and WL15. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

TABLE 15

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
																	2	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
3	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
																	4	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
5	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1
																	6	0	0	0	0	0	0	1	0	1	1	1	1	1	1	0	1

Referring to Table 16, the first selected word line is WL7, the remaining first word lines are WL0-WL6, the second selected word line is WL15, and the remaining second word lines are WL8-WL14. First storage data are written into storage units connected with WL7, second storage data are written into storage units connected with WL0-WL6, second storage data are written into storage units connected with WL15, and first storage data are written into storage units connected with WL8-WL14.WL7 and WL15 may be activated simultaneously, the stored data in the memory cells connected to WL0-WL6 and the stored data in the memory cells connected to WL8-WL14 are read. Then, the detection module 103 obtains a first target memory cell in which the second memory data is rewritten as the first memory data in the memory cells connected to WL0-WL6, and obtains a second target memory cell in which the first memory data is rewritten as the second memory data in the memory cells connected to WL8-WL14. It is determined that the first word line driving circuit corresponding to the first target word line connected to the first target memory cell and the second word line driving circuit corresponding to the second target word line connected to the second target memory cell have defects.

Table 16

WL/BL	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
																	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
																	2	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
3	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
																	4	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
5	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0
																	6	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	0

As shown in fig. 4, an input terminal of each second word line driving circuit is connected to the second main word line MWL1, and is configured to receive an input signal provided by the second main word line MWL1, and an output terminal of each second word line driving circuit is connected to a corresponding second word line. For example, the input terminal of SWD8 is connected to the second main word line MWL1, and the output terminal of SWD8 is connected to WL8; an input end of the SWD9 is connected with the second main word line MWL1, and an output end of the SWD9 is connected with the WL9; an input end of the SWD10 is connected with the second main word line MWL1, and an output end of the SWD10 is connected with the WL10; an input end of the SWD11 is connected with the second main word line MWL1, and an output end of the SWD11 is connected with the WL11; an input end of the SWD12 is connected with the second main word line MWL1, and an output end of the SWD12 is connected with the WL12; an input end of the SWD13 is connected with the second main word line MWL1, and an output end of the SWD13 is connected with the WL13; an input end of the SWD14 is connected with the second main word line MWL1, and an output end of the SWD14 is connected with the WL14; an input terminal of SWD15 is connected to second main word line MWL1, and an output terminal of SWD15 is connected to WL15.

The third end of each second word line driving circuit is connected with a corresponding first power supply end, and the first power supply end provides a first voltage VPP or a second voltage VSS for the corresponding second word line driving circuit, wherein the first voltage VPP is larger than the second voltage VSS, so that a high level signal or a low level signal can be provided for the corresponding word line. The fourth end of each second word line driving circuit is connected with a corresponding second power supply end, the second power supply end provides a third voltage for the corresponding second word line, and the third voltage is lower than the second voltage VSS, so that a low-level signal is provided for the corresponding first word line, and the corresponding second word line is effectively closed. For example, a first end of SWD8 is connected to FXT0 and a second end of SWD8 is connected to VKK0; the first end of SWD9 is connected with FXT1, and the second end of SWD9 is connected with VKK1; a first end of SWD10 is connected with FXT2, and a second end of SWD10 is connected with VKK2; a first end of SWD11 is connected with FXT3, and a second end of SWD11 is connected with VKK3; a first end of SWD12 is connected with FXT4, and a second end of SWD12 is connected with VKK4; a first end of SWD13 is connected with FXT5, and a second end of SWD13 is connected with VKK5; a first end of SWD14 is connected to FXT6 and a second end of SWD14 is connected to VKK6; the first end of SWD15 is connected to FXT7 and the second end of SWD15 is connected to VKK7.

Then both the first end of SWD0 and the first end of SWD8 are connected to FXT0 so that WL0 and WL8 can be turned on simultaneously; the first end of SWD1 and the first end of SWD9 are connected with FXT1, so that WL1 and WL9 can be simultaneously turned on; the first end of SWD2 and the first end of SWD10 are connected with FXT2, so that WL2 and WL10 can be simultaneously turned on; the first end of SWD3 and the first end of SWD11 are connected with FXT3, so that WL3 and WL11 can be simultaneously turned on; the first end of SWD4 and the first end of SWD12 are connected to FXT4, so that WL4 and WL12 can be turned on simultaneously; the first end of SWD5 and the first end of SWD13 are connected with FXT5, so that WL5 and WL13 can be simultaneously turned on; the first end of SWD6 and the first end of SWD14 are connected to FXT6, so that WL6 and WL14 can be turned on simultaneously; the first end of SWD7 and the first end of SWD15 are both connected to FXT7 so that WL7 and WL15 can be turned on simultaneously.

Fig. 5 is a circuit diagram of a second word line driving circuit according to an embodiment of the present application. As shown in fig. 5, the second word line driving circuit includes a second P-type transistor P2, a third N-type transistor N3, and a fourth N-type transistor N4, where the gate of the third N-type transistor N3 and the gate of the second P-type transistor P2 are connected to each other as an input terminal of the second word line driving circuit, and the input terminal of the second word line driving circuit is connected to the second main word line MWL1 for receiving an input signal provided by the second main word line WML 1. The first pole of the second P-type transistor P2 and the first pole of the third N-type transistor N3 are connected to each other as an output terminal of the second word line driving circuit, the output terminal of the second word line driving circuit is connected to a corresponding word line, and the second word line driving circuit outputs a high level signal or a low level signal to the corresponding word line under the action of an input signal. The second pole of the second P-type transistor P2 is used as the first end of the corresponding second word line driving circuit, connected with the corresponding first power supply end FXT, and the second end of the third N-type transistor N3 is used as the second end of the corresponding second word line driving circuit, connected with the corresponding second power supply end VKK.

The first pole of the fourth N-type transistor N4 is connected with the first pole of the third N-type transistor N3, the second pole of the fourth N-type transistor N4 is connected with the second pole of the third N-type transistor N3, the grid electrode of the fourth N-type transistor N4 is connected with a corresponding control signal end FXB, the control signal end FXB provides a control signal for the corresponding fourth N-type transistor N4, and the grid electrode of the fourth N-type transistor N4 in the second word line driving circuit and the grid electrode of the second N-type transistor N2 in the first word line driving circuit can be connected with the same control signal end. As shown in fig. 4, the second N-type transistor N2 in SWD0 and the fourth N-type transistor N4 in SWD8 are connected to FXB0, the second N-type transistor N1 in SWD1 and the fourth N-type transistor N4 in SWD9 are connected to FXB1, the second N-type transistor N2 in SWD2 and the fourth N-type transistor N4 in SWD10 are connected to FXB2, the second N-type transistor N2 in SWD3 and the fourth N-type transistor N4 in SWD11 are connected to FXB3, the second N-type transistor N2 in SWD4 and the fourth N-type transistor N4 in SWD12 are connected to FXB4, the second N-type transistor N2 in SWD5 and the fourth N-type transistor N4 in SWD13 are connected to FXB5, the second N-type transistor N2 in SWD6 and the fourth N-type transistor N4 in SWD14 are connected to FXB6, and the second N-type transistor N2 in SWD7 and the fourth N-type transistor N4 in SWD7 are simultaneously controlled to turn on.

In some embodiments, the semiconductor memory further includes a Sense Amplifier (SA) connecting the bit line of each memory cell and the complementBit lines for amplifying the memory data of the memory cells. As shown in fig. 6, the sense amplifier is connected to the bit line BL and the complementary bit line BLB of the memory cell 204, the memory cell 204 includes a storage capacitor C and an access transistor T, and a first terminal of the storage capacitor C is connected to a fixed power supply, for example, 0.5V _CC The second terminal of the storage capacitor C is connected to the first terminal of the access transistor T, the second terminal of the access transistor T is connected to the bit line BL, and the control terminal of the access transistor T is connected to the word line WL. Logical 1 s and 0 s are represented by more and less charge stored in the storage capacitor C, or by high and low voltage differences across the storage capacitor C. The access transistor T is used to control whether the information stored in the storage capacitor C is allowed or prohibited from being read or rewritten.

As shown in fig. 6, the sense amplifier 20 includes an amplifying module 201, an equivalent module 202, and a column selecting module 203, and the sense amplifier 20 is connected to a bit line BL and a complementary bit line BLB of the memory cell 204.

The amplifying module 201 includes at least one cross-coupled amplifying circuit, each of which has a first end, a second end, a third end and a fourth end, the first end of the cross-coupled amplifying circuit is connected to a third power supply end PCS, and the third power supply end PCS provides a high potential voltage V _ary The second end of the cross-coupling amplifying circuit is connected with a fourth power supply end NCS which provides a low potential voltage V _ss The third terminal of the cross-coupled amplifying circuit is connected to the bit line BL, and the fourth terminal of the cross-coupled amplifying circuit is connected to the complementary bit line BLB.

Wherein the cross-coupled amplifying circuit includes: the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4. The first end of the first transistor T1 is the second end of the cross-coupled amplifying circuit, the second end of the third transistor T3 is the second end of the cross-coupled amplifying circuit, the second end of the first transistor T1 is the third end of the cross-coupled amplifying circuit, and the second end of the second transistor T2 is the fourth end of the cross-coupled amplifying circuit. The second terminal of the first transistor T1 is connected to the first terminal of the third transistor T3, the second terminal of the second transistor T2 is connected to the first terminal of the fourth transistor T4, the first terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, and the second terminal of the third transistor T3 is connected to the second terminal of the fourth transistor T4. The control end of the first transistor T1 is connected with the second end of the second transistor T2, and the control end of the third transistor T3 is connected with the second end of the second transistor T2; the control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the control terminal of the fourth transistor T4 is connected to the second terminal of the first transistor T1. The first transistor T1 and the second transistor T2 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.

The equivalent module 202 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, wherein the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all connected to an equalization signal terminal EQ for providing an equalization signal VEQ. The first pole of the fifth transistor T5 and the first pole of the sixth transistor T6 are connected to a precharge voltage terminal BLP for providing a precharge voltage V _BLP . The second pole of the fifth transistor T5 is connected to the bit line BL, the second pole of the sixth transistor T6 is connected to the complementary bit line BLB, the first pole of the seventh transistor T7 is connected to the bit line BL, and the second pole of the seventh transistor T7 is connected to the complementary bit line BLB. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are N-type transistors.

The column selection module 203 includes an eighth transistor T8, a gate of the eighth transistor T8 is connected to a column selection signal terminal YS, the column selection signal terminal YS provides a column selection signal YSW, a first pole of the eighth transistor T8 is connected to a bit line BL, and a second pole of the eighth transistor T8 is connected to a data input/output line LIO. The eighth transistor T8 is turned on by the column selection signal YSW so that the bit line BL is connected to the data input output line LIO.

The read data includes a precharge phase, a charge sharing phase, and an amplifying phase. In the precharge phase, the voltage of the bit line BL and the voltage of the complementary bit line BLB are pulled to the precharge voltage V _BLP When the equalizing signal VEQ is a high level signal, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on to precharge the bit line BL and the complementary bit line BLB to the precharge voltage V _BLP . In the charge sharing stage, the word corresponding to the memory cell 204 is controlledThe signal on the line WL turns on the access transistor T in the memory cell 204, and the storage capacitor C increases the voltage on the bit line BL. Charge sharing occurs between the charge stored in the storage capacitor C and the charge stored in the bit line BL. In the amplifying stage, the sense amplifier 20 pulls up the voltage of the bit line BL to a first preset value and pulls down the voltage of the complementary bit line BLB to a second preset value based on the voltage difference between the bit line BL and the complementary bit line BLB to increase the voltage difference between the bit line BL and the complementary bit line BLB.

As shown in fig. 7, includes:

s101, writing first storage data into a storage unit connected with one first word line in a plurality of first word lines corresponding to the word line driving module, and writing second storage data into storage units connected with the rest first word lines.

The word line driving module comprises a plurality of first word line driving circuits, wherein each first word line driving circuit is connected with one first word line, and each first word line is connected with one memory cell. First storage data is written into a storage unit connected with one first word line in the plurality of first word lines connected with the word line driving module, and second storage data with the opposite level to the first storage data is written into storage units connected with the rest first word lines in the plurality of first word lines.

S102, reading the memory cells connected with the rest first word lines when one first word line is activated.

And opening one first word line in the plurality of first word lines, closing the rest first word lines in the plurality of first word lines, and reading the storage data in the storage units connected with the rest first word lines.

In some embodiments, the first word line driving circuits of the even first word line connections are located at the first end of the first word line, the first word line driving circuits of the odd first word line connections are located at the second end of the first word line, e.g., SWD0, SWD2, SWD4, SWD6 are located at the first end of the first word line, and SWD1, SWD3, SWD5, SWD7 are located at the second end of the first word line.

One of the even first word lines may be turned on, and the remaining first word lines of the even first word lines may be turned off, so that the stored data in the memory cells connected to the remaining first word lines of the even first word lines may be read. For example, even word lines include WL0, WL2, WL4, WL6, WL0 is turned on, WL2, WL4, and WL6 are turned off, and memory data in the memory cells connected to WL2, memory data in the memory cells connected to WL4, and memory data in the memory cells connected to WL6 are read. If WL2 and WL0 are shorted, WL0 receives a high voltage when WL0 is turned on, resulting in that the voltage of WL2 is raised and cannot be completely turned off, and since WL2 and WL0 share the same bit line, in the charge sharing stage and the amplifying stage, the high-potential charges in the WL0 connected memory cells enter the WL2 connected memory cells through the bit line, resulting in that the second memory data in the WL2 connected memory cells are rewritten into the first memory data.

One of the odd first word lines may be turned on, and the remaining first word lines of the odd first word lines may be turned off to read the stored data in the memory cells connected to the remaining first word lines of the odd first word lines.

In some embodiments, each first word line driving circuit is provided with a first end and a second end, the first end of each first word line driving circuit is connected with a corresponding first power supply end, the second end of each first word line driving circuit is connected with a corresponding second power supply end, the first power supply end provides a first voltage or a second voltage for the corresponding first word line driving circuit, the second power supply end provides a third voltage for the corresponding first word line driving circuit, the first voltage is larger than the second voltage, and the second voltage is larger than the third voltage.

And when the first power supply end connected with the first word line driving circuit corresponding to one of the even number first word lines supplies a first voltage to the one first word line, reading the memory cells connected with the rest first word lines in the even number first word lines. For example, when the first power supply terminal FXT0 corresponding to SWD0 connected to WL0 supplies the first voltage to WL0, the storage data in the storage unit connected to WL2, the storage data in the storage unit connected to WL4, and the storage data in the storage unit connected to WL6 are read. If the first power supply terminal FXT0 corresponding to the SWD0 connected to the WL0 is shorted with the WL4, when the WL0 is turned on and the WL4 is turned off, the first power supply terminal FXT0 connected to the SWD0 connected to the WL0 provides a high voltage to the WL0, so that the voltage of the WL4 cannot be completely turned off, and since the WL0 and the WL4 share the same bit line, the high-potential charges in the memory cells connected to the WL0 enter the memory cells connected to the WL4 through the bit line, so that the second memory data in the memory cells connected to the WL4 are rewritten into the first memory data.

And when the first power supply end connected with the first word line driving circuit corresponding to one of the odd first word lines supplies a first voltage to the one first word line, reading the memory cells connected with the rest first word lines in the odd first word lines. For example, when the first power supply terminal FXT1 corresponding to the SWD1 connected to WL1 supplies the first voltage to WL1, the storage data in the storage unit connected to WL3, the storage data in the storage unit connected to WL5, and the storage data in the storage unit connected to WL7 are read.

In some embodiments, each first word line driving circuit includes a first P-type transistor, a first N-type transistor, and a second N-type transistor, the gate of the first P-type transistor and the gate of the first N-type transistor are connected to each other as an input terminal of the corresponding first word line driving circuit, the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected to each other as an output terminal of the corresponding first word line driving circuit, the second pole of the first P-type transistor serves as a first terminal of the corresponding first word line driving circuit, the second pole of the first N-type transistor serves as a second terminal of the corresponding first word line driving circuit, the gate of the second N-type transistor is connected to a corresponding control signal terminal, the first pole of the second N-type transistor is connected to the first pole of the first N-type transistor, and the second pole of the second N-type transistor is connected to the second pole of the second N-type transistor, the control signal terminal is used for providing the control voltage. The second N-type transistor in each first word line driving circuit has a corresponding control signal terminal, for example, a second N-type transistor in SWD0 is connected to FXB0, a second N-type transistor in SWD1 is connected to FXB1, a second N-type transistor in SWD2 is connected to FXB2, a second N-type transistor in SWD3 is connected to FXB3, a second N-type transistor in SWD4 is connected to FXB4, a second N-type transistor in SWD5 is connected to FXB5, a second N-type transistor in SWD6 is connected to FXB6, and a second N-type transistor in SWD7 is connected to FXB7.

And activating one of the even first word lines, and reading the memory cells connected with the remaining first word lines in the even first word lines when the third N-type transistor in the first word line driving circuit connected with the remaining first word lines in the even first word lines is turned on under the action of a control signal provided by a corresponding control signal end, for example, activating WL0, and reading the memory data in the memory cells connected with WL2, the memory data in the memory cells connected with WL4 and the memory data in the memory cells connected with WL6 when the third N-type transistor in the SWD0 is turned on under the action of the control signal provided by FXB 0. If FXB6 corresponding to the third N-type transistor in SWD0 corresponding to WL6 is shorted, when WL0 is turned on and WL6 is turned off, FXB6 corresponding to WL6 provides high voltage, so that voltage of WL6 cannot be turned off, and since WL0 and WL6 share the same bit line, charges of high potential in the WL0 connected memory cells enter the WL6 connected memory cells through the bit line, resulting in that second memory data in the WL6 connected memory cells are rewritten into first memory data.

And activating one of the odd first word lines, and reading the memory cells connected with the remaining first word lines in the odd first word lines when the third N-type transistor in the first word line driving circuit connected with the remaining first word lines in the odd first word lines is turned on under the action of a control signal provided by a corresponding control signal end, for example, reading the memory data in the memory cells connected with WL3, the memory data in the memory cells connected with WL5 and the memory data in the memory cells connected with WL7 when the third N-type transistor in the SWD1 is turned on under the action of the control signal provided by FXB 1.

In some embodiments, after activating one first word line for a first predetermined time, the remaining memory cells connected to the first word line may be read, and then the precharging of the bit line and the complementary bit line connected to the memory cells connected to the first word line may be delayed, thereby providing a sufficient charge sharing time and ensuring that the sense amplifier is turned on. The first preset time may be, for example, 100ns.

S103, acquiring a first target storage unit of which second storage data is rewritten into first storage data and a first target word line connected with the first target storage unit, and determining that a first word line driving circuit connected with the first target word line has defects.

In some embodiments, a first word line may be activated a first predetermined number of times, and each time the memory cells connected to the remaining first word line are read, the result of the first predetermined number of times may be obtained. And acquiring the second storage data in the storage units connected with the remaining first word lines to be reversely written into the first target storage unit with the second preset times of the first storage data, and improving the accuracy of the result by activating the mode for multiple times and reading the second storage data. The first preset number of times may be, for example, 50000 times or more, and the second preset number of times is determined according to specific situations.

The word line driving module may further include a plurality of second word line driving circuits, each of the second word line driving circuits being connected to the second word line, and the word line driving module being connected to the plurality of second word lines. And writing second storage data into a storage unit connected with one second word line in the plurality of second word lines corresponding to the word line driving module, writing first storage data into storage units connected with the rest second word lines, activating the one second word line, and reading the storage units connected with the rest second word lines. And then, acquiring second storage data in the storage units connected with the remaining second word lines, which are reversely written into second target storage units of the first storage data, and determining that a second word line driving circuit corresponding to the second target word line connected with the second target storage units has defects.

In the above embodiment, first storage data is written into a storage unit connected with one first word line of a plurality of first word lines connected with a word line driving module, second storage data with opposite level to the first storage data is written into a storage unit connected with the remaining first word lines, the storage unit connected with the remaining first word line is read when one first word line is activated, the second storage data is reversely written into a first target storage unit of the first storage data in the storage unit connected with the remaining first word line, and it is determined that a defect exists in a first word line driving circuit corresponding to the first target word line connected with the first target storage unit, so that the defect in the word line driving circuit is effectively detected in a chip testing stage, and the product yield is improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same. Although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A semiconductor memory device, comprising:

2. The semiconductor memory of claim 1, wherein the first word line driving circuits to which even first word lines are connected are located at a first end of the first word lines, and the first word line driving circuits to which odd first word lines are connected are located at a second end of the first word lines;

3. The semiconductor memory according to claim 1, wherein each of the first word line driver circuits is provided with an input terminal and an output terminal;

4. The semiconductor memory according to claim 3, wherein each of the first word line driver circuits is provided with a first terminal and a second terminal;

5. The semiconductor memory according to claim 4, wherein each of the first word line driver circuits includes a first P-type transistor, a first N-type transistor, and a second N-type transistor;

6. The semiconductor memory according to claim 4, wherein the first voltage is greater than a first preset value and the second voltage is greater than a second preset value.

7. The semiconductor memory of claim 1, wherein the word line driving module further comprises: a plurality of second word line driving circuits, each of which is connected to one of the second word lines;

the detection module is further used for acquiring a second target storage unit of which the first storage data is rewritten into second storage data and a second target word line connected with the second target storage unit, and determining that a second word line driving circuit connected with the second target word line has defects.

8. The semiconductor memory according to claim 7, wherein each of the second word line driver circuits is provided with an input terminal and an output terminal;

9. The semiconductor memory according to claim 8, wherein each of the second word line driver circuits is provided with a third terminal and a fourth terminal;

10. The semiconductor memory according to claim 9, wherein each of the second word line driver circuits includes a second P-type transistor, a third N-type transistor, and a fourth N-type transistor;

11. The semiconductor memory according to claim 1, further comprising: a sense amplifier;

12. A control method of a semiconductor memory, characterized in that the method is for controlling the semiconductor memory according to any one of claims 1 to 11, comprising:

writing first storage data into a storage unit connected with one first word line in a plurality of first word lines corresponding to the word line driving module, and writing second storage data into storage units connected with the rest first word lines, wherein the levels of the first storage data and the second storage data are opposite;

13. The method of claim 12, wherein the reading the remaining first word line connected memory cells while activating the one first word line, in particular comprises:

14. The method of claim 12, wherein the reading the remaining first word line connected memory cells while activating the one first word line, in particular comprises:

15. The method of claim 14, wherein the activating one of the even first word lines, reading the memory cells connected to the remaining first word lines in the even first word lines, and/or activating one of the odd first word lines, reading the memory cells connected to the remaining first word lines in the odd first word lines, specifically comprises:

16. The method of claim 14, wherein activating one of the even first word lines, reading the remaining first word line connected memory cells in the even first word lines, and/or activating one of the odd first word lines, reading the remaining first word line connected memory cells in the odd first word lines, comprises:

17. The method according to claim 12, wherein the method further comprises:

18. The method of claim 12, wherein the reading the remaining first word line connected memory cells while activating the one first word line, in particular comprises: