CN117194304A - Signal transmission circuit and computing device - Google Patents

Abstract

The embodiment of the application provides a signal transmission circuit and computing equipment. The signal transmission circuit includes mainboard and patch cord, and the patch cord includes: the first connector is used for being connected with the main board; a second connector provided with a slot for installing a PCIe card of the high-speed serial computer expansion bus; the cable assembly, its first end is connected with first connector, and its second end is connected with the pin in the slot of second connector, and cable assembly is used for transmitting the working signal in order to make the PCIe card of installing in the second connector communicate with the mainboard, and the working signal includes power signal, low-speed signal and high-speed signal. In the signal transmission circuit provided by the embodiment of the application, the adapter cable does not need to be matched with the circuit board, so that the additional development of the circuit board can be avoided, meanwhile, the structure of the connector for installing the PCIe card of the adapter cable is simplified, the cost is reduced, the size of the connector for installing the PCIe card is smaller, the fixing mode is more flexible, and the application range is enlarged.

Description

Signal transmission circuit and computing device

Technical Field

The present application relates to the field of computing devices, and in particular, to a signal transmission circuit and a computing device.

Background

Fifth generation and above PCIe (peripheral component interconnect express) technology is generally adopted in the current server, the transmission rate of PCIe signals is faster, and the link loss requirement is higher and higher. In order to ensure flexibility and diversity of the server in the application process, a connector of the PCIe card (i.e., a connector for installing the PCIe card) is generally not arranged on the motherboard, but the motherboard is connected with the connector of the PCIe card in a mode of cable external connection, and the connector of the PCIe card is installed on the PCIe card carrier board and is electrically connected with the PCIe card carrier board.

Therefore, the connector of the PCIe card needs to be matched with the PCIe card carrier plate to be used, the fixing mode of the connector is single, the expansion of the application range is not facilitated, meanwhile, a circuit board needs to be additionally developed, the connector of the PCIe card needs to be designed to be electrically connected with the PCIe card carrier plate, the structure is complex, the size is large, and the cost is not facilitated to be reduced.

Disclosure of Invention

The embodiment of the application provides a signal transmission circuit and a computing device, an adapter cable does not need to be matched with a circuit board, the additional development of the circuit board can be avoided, and meanwhile, the structure of a connector for installing a PCIe card of the adapter cable is simplified, so that the cost is reduced, the connector for installing the PCIe card is smaller in size, the fixing mode is more flexible, and the application range is enlarged.

In a first aspect, the present application provides a signal transmission circuit, the signal transmission circuit including a motherboard and an adapter cable, wherein the adapter cable includes: the first connector is used for being connected with the main board; the second connector is provided with a slot, and the slot is used for installing a PCIe card of the high-speed serial computer expansion bus; the cable assembly, the first end of cable assembly with first connector is connected, the second end of cable assembly with pin in the slot of second connector is connected, the cable assembly is used for transmitting the working signal, so that install the PCIe card in the second connector can communicate with the mainboard, wherein, the working signal includes power signal, low-speed signal and high-speed signal.

In the signal transmission circuit provided by the embodiment of the application, the adapter cable does not need to be matched with the circuit board, so that the additional development of the circuit board can be avoided, and meanwhile, the structure of the connector for installing the PCIe card of the adapter cable is simplified, thereby reducing the cost, and the connector for installing the PCIe card has smaller volume, more flexible fixing mode and contribution to expanding the application range. Meanwhile, the device on the circuit board does not need to be provided with power or signals because the device does not depend on the circuit board, and cable signal resources can be simplified.

In one possible implementation, the high speed signal comprises a PCIe high speed signal and the second connector is a PCIe standard connector. That is, in this implementation, the high speed signal may be a PCIe high speed signal in order for the PCIe card to operate. It will be appreciated that in other implementations, the high speed signal may also include other signals, if desired.

In one possible implementation, the low-speed signal includes at least one of an IIC signal, an in-place signal, a clock signal, and a reset signal, where the in-place signal is used to indicate whether the PCIe card is electrically connected to the slot, and the IIC signal includes a communication signal of the PCIe card and the motherboard. That is, in this implementation, the kind of the low-speed signal may be selected according to the operation requirement, and for example, may include at least one of an IIC signal, a bit signal, a clock signal, and a reset signal. It will be appreciated that in other implementations, the low speed signal may also include other signals, if desired.

In one possible implementation, the power signal is provided by the motherboard to the socket; the low-speed signals comprise a first low-speed signal and a second low-speed signal, the first low-speed signal is sent to the PCIe card in the slot by the main board, and the second low-speed signal is sent to the main board by the PCIe card in the slot; the high-speed signals comprise a first high-speed signal and a second high-speed signal, wherein the first high-speed signal is sent to the slot by the main board, and the second high-speed signal is sent to the main board by a PCIe card in the slot. That is, in this implementation, in order for the PCIe card to function properly, the motherboard needs to provide power signals for the PCIe card, and in addition, the communication between the motherboard and the PCIe card is bi-directional, the motherboard may send high speed signals and low speed signals to the PCIe card, and the PCIe card may also send high speed signals and low speed signals to the motherboard.

In one possible implementation, the cable assembly includes a first set of cables for transmitting the power signal, a second set of cables for transmitting the low-speed signal, and a third set of cables for transmitting the high-speed signal, the number of the third set of cables being the same as the number of the second connectors. That is, in this implementation, different signals need to be transmitted over different cables.

In one possible implementation, the number of the first connectors is one, and the number of the second connectors is one; the first ends of the first group of cables, the second group of cables and the third group of cables are connected with one first connector, and the second ends of the first group of cables, the second group of cables and the third group of cables are connected with one second connector. That is, in this implementation, the patch cable may be a one-to-one type of cable, i.e., including one first connector and one second connector.

In one possible implementation, the number of the first connectors is one, the number of the second connectors is a plurality, and the number of the first group of cables, the number of the second group of cables and the number of the third group of cables are the same as the number of the second connectors; the first ends of the first group of cables, the second group of cables and the third group of cables are connected with one first connector, the second ends of the first group of cables are connected with the second connectors in a one-to-one correspondence mode, the second ends of the second group of cables are connected with the second connectors in a one-to-one correspondence mode, and the second ends of the third group of cables are connected with the second connectors in a one-to-one correspondence mode. That is, in this implementation, the patch cable may be a one-to-many type cable, that is, includes one first connector and a plurality of second connectors, and the number of the plurality of second connectors may be two or more.

In one possible implementation manner, the number of the first connectors is one, the number of the second connectors is a plurality, the second ends of the first group of cables comprise a plurality of first sub-connection ends, the second ends of the second group of cables comprise a plurality of second sub-connection ends, and the number of the third group of cables is a plurality; the first ends of the first group of cables, the second group of cables and the third group of cables are connected with one first connector, each first sub-connecting end is connected with each second connector in a one-to-one correspondence mode, each second sub-connecting end is connected with each second connector in a one-to-one correspondence mode, and the second ends of the third group of cables are connected with each second connector in a one-to-one correspondence mode. That is, in this implementation, when the patch cable is a one-to-many type cable, the first group cable and the second group cable may be split cables, which may reduce the number of cables, facilitate manufacturing, and make the structure simple. Wherein, the third group of cables can be buses, such as X16 bandwidth, the X16 bandwidth can be divided into two X8, but the X16 bandwidth can not be divided into two to form 32. The first set of cables and the second set of cables are not buses, can be common cables, and can be divided into two.

In one possible implementation, the first connector is a double density unified bus connector.

In a second aspect, the present application provides a computing device, where the computing device includes the signal transmission circuit and a PCIe card, where the PCIe card is connected to the signal transmission circuit through the second connector of the signal transmission circuit.

Additional features and advantages of the application will be set forth in the detailed description which follows.

Drawings

The drawings that accompany the detailed description can be briefly described as follows.

FIG. 1 is a schematic diagram of a signal transmission circuit;

fig. 2 is a schematic perspective view of a CEM connector of the signal transmission circuit shown in fig. 1;

FIG. 3A is a schematic view of a partial structure of the CEM connector of FIG. 2 mounted on a circuit board;

FIG. 3B is a schematic top view of the CEM connector of FIG. 2 mounted on a circuit board;

fig. 4 is a schematic structural diagram of a signal transmission circuit according to a first embodiment of the present application;

fig. 5 is a schematic structural diagram of a signal transmission circuit according to a second embodiment of the present application;

fig. 6 is a schematic structural diagram of a signal transmission circuit according to a third embodiment of the present application;

fig. 7 is a schematic partial structure of a computing device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the specification. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.

Also, in the description of the present specification, "/" means or, unless otherwise indicated, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. Further, "plurality" means two or more than two.

Furthermore, in the description herein, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. The terms "mounted," "connected," and "coupled" are to be broadly interpreted, as referring to a fixed connection, a removable connection, an interference connection, or an integral connection, for example; the specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. PCIe signals transmitted by the interconnect between the PCIe card and the central processing unit (central processing unit, CPU) generally represent the highest level of interface technology for the server. Because PCIe signals are transmitted at very high rates and with very large high frequency content, transmission of PCIe signals on a printed circuit board (printed circuit board, PCB) needs to be severely constrained.

In order to ensure the flexibility and diversity of the server in the application process, the connector of the PCIe card is not generally arranged on the main board, in addition, the current server generally adopts the fifth generation PCIe technology and more, the PCIe signal transmission speed is as high as 32 Gbit per second, the transmission loss of the PCIe signal by the PCB wiring and the external cable is very large, the link loss requirement is higher and higher, and in order to reduce the loss, the main board and the PCIe card carrier board can be connected in a cable external mode. For example, a CPU and a male connector are arranged on the main board, the CPU is connected with the male connector through a main board wiring, one end of the adapter cable is provided with the female connector, and the other end of the adapter cable is provided with the PCIe card connector. The female connector is connected with a male connector on the main board, and a PCIe card connector at the other end of the patch cable is arranged on a PCIe card carrier plate. The patch cable may thus be routed out of the target connector (i.e., PCIe card connector).

Fig. 1 is a schematic diagram of a signal transmission circuit. The signal transmission circuit may include a motherboard (not shown), a patch cable, and a circuit board 160. Illustratively, as shown in fig. 1, the patch cable includes UBCDD connectors, cables 20 and CEM (card electromechanical) connectors, and illustratively, the CEM connector is a PCIe card connector, which may be a PCIe x16 standard interface, and the CEM connector may be fixedly mounted on the circuit board 160. One end of the cable 20 is connected to the UBCDD connector and the other end is connected to the CEM connector, such that the patch cable is a UBCDD-to-CEM cable.

Fig. 2 is a schematic perspective view of a CEM connector of the signal transmission circuit shown in fig. 1. As shown in fig. 2, the CEM connector includes a composite interface 10. The composite interface 10 includes a first interface 30, a second interface 40, an insulating body 50, and connecting wires (not shown). The first interface 30 and the second interface 40 are fixedly connected to the insulating body 50, and the connection wires are electrically connected between the first interface 30 and the second interface 40. The first interface 30 is a CEM connector interface, and is used for plugging an external plug-in card, such as a PCIe card, and the second interface 40 is used for communication connection with a PCIe card carrier board, such as a circuit board 160, and the insulating body 50 may be made of an insulating material such as plastic. The cable 20 includes a first portion of cable that is connected to the first interface 30 and a second portion of cable that is connected to the second interface 40.

Further, the first interface 30 may include a first insulator 31 provided with a socket 33 and a plurality of conductive terminals (not shown in the figure) embedded in the socket 33 of the first insulator 31 and spaced apart from each other. The conductive terminal may be a metal spring. The first insulator 31 is fixedly connected to the insulating body 50 to achieve a fixed connection between the first interface 30 and the insulating body 50. And, the first insulator 31 protrudes with respect to the insulating body 50. The plug-in interface 33 may be used for plugging an external plug-in card, such as a PCIe card, and the first insulator 31 may be made of an insulating material such as plastic.

In the patch cable shown in fig. 1 and 2, the CEM connector needs to be used with a circuit board 160 (e.g., PCIe card carrier board), for example, the circuit board 160 is used to secure the CEM connector, and the CEM connector needs to be communicatively connected to the circuit board 160. The following describes in detail with reference to fig. 3A and 3B.

Fig. 3A is a schematic view of a partial structure of the CEM connector of fig. 2 when mounted on a circuit board. As shown in fig. 3A, the first interface 30 of the CEM connector passes through the circuit board 160 and extends out of one side of the circuit board 160, the external plug card 180 is inserted into the plug interface 33, and the insulating body 50 is located on the other side of the circuit board 160, so as to realize the mating and fixing of the CEM connector by the circuit board 160. Also, the second interface 40 (not shown in FIG. 3A) may be electrically connected to contacts on the circuit board 160, thereby enabling a communicative connection with the circuit board 160.

Fig. 3B is a schematic top view of the CEM connector of fig. 2 mounted on a circuit board. As shown in fig. 3B, the signals in the CEM connector and circuit board 160 are transmitted as follows:

1) The first portion of the cable is electrically connected to the first interface 30 such that the motherboard can communicate with an external plug card 180 within the first interface 30 via the first portion of the cable. For example, the motherboard may send PCIe high speed signals to the external patch card 180 through the first portion of the cable, the first interface 30;

2) The second part of the cable is electrically connected with a second interface 40 (stray signal interface), an IIC (inter-integrated circuit) chip is further arranged on the circuit board, and the second interface 40 is electrically connected with the IIC chip through wiring on the circuit board. Illustratively, the second interface 40 includes a plurality of pins, wherein:

and a part of the pins are connected with the IIC chip through the circuit board, so that the main board can supply power to the circuit board and the IIC chip through the second part of cables, namely, the power supply signals are transmitted, and the main board can also communicate with the IIC chip. For example, the motherboard may transmit low-speed signals such as IIC signals to the IIC chip through the second portion of the cable, a portion of the pins of the second interface 40, and the circuit board 160. In addition, the IIC chip may further obtain information related to devices such as a memory and a temperature sensor on the circuit board 160, such as manufacturer information or card model information, according to a control instruction of the motherboard, and send the information to the motherboard through the circuit board, a part of pins of the second interface 40, a second part of cables, and UBCDD connectors.

Another part of the pins are respectively connected with the IIC chip and the first interface 30, so that the IIC chip can also communicate with the external socket card 180 in the first interface 30 through another part of the pins of the second interface 40. For example, the external socket card 180 may be a PCIe card, where an in-place signal of the PCIe card may be sent to the IIC chip through another part of the pins of the second interface 40 and the circuit board, and the IIC chip is sent to the motherboard through the circuit board, a part of the pins of the second interface 40, the second part of the cable, and the UBCDD connector.

That is, the IIC chip is connected to the second portion of the cable through a part of the plurality of pins of the second interface 40, and is connected to the first interface 30 through another part of the plurality of pins of the second interface 40.

Since the UBCDD-CEM cable shown in fig. 1 to 3B needs to be matched with the circuit board 160, for example, the circuit board 160 is matched with and fixed to the CEM connector, and meanwhile, the second interface 40 above the CEM connector can be used to transmit low-speed signals, for example, the motherboard transmits IIC signals and power supply to the IIC chip on the circuit board 160 through the second interface, for example, the IIC chip on the circuit board 160 transmits IIC signals and PCIe in-place signals to the motherboard, so that additional circuit board development is needed, and meanwhile, the CEM connector needs to be provided with the second interface for communication with the circuit board, which is complex in structure and large in volume, thereby resulting in high cost.

In view of this, the embodiment of the application provides a signal transmission circuit, in which the patch cable does not need to be matched with a circuit board, so that additional development of the circuit board can be avoided, and meanwhile, the structure of the connector for mounting the PCIe card of the patch cable is simplified, thereby reducing the cost, and the connector for mounting the PCIe card has smaller volume and more flexible fixing mode, and is beneficial to expanding the application range. Meanwhile, the device on the circuit board does not need to be provided with power or signals because the device does not depend on the circuit board, and cable signal resources can be simplified.

Fig. 4 is a schematic structural diagram of a signal transmission circuit according to a first embodiment of the present application. As shown in fig. 4, the signal transmission circuit includes a main board (not shown) and a patch cable. The patch cable comprises a first connector 1, a second connector 2 and a cable assembly 3. The first connector 1 is connected to the motherboard. In some examples, the connector is provided on the motherboard, one of the first connector 1 and the connector on the motherboard may be a male connector, and the other may be a female connector, the male connector and the female connector being capable of mating connection. In other examples, the first connector 1 may be directly disposed on the motherboard, i.e., the first connector 1 is a connector fixedly disposed on the motherboard. The second connector 2 is provided with a slot C, and the slot C is used for installing a PCIe card of the expansion bus of the high-speed serial computer. The first end of the cable assembly 3 is connected with the first connector 1, the second end of the cable assembly 3 is connected with a pin in the slot C of the second connector 2, and the cable assembly 3 is used for transmitting working signals so that a PCIe card installed in the second connector 2 can communicate with the motherboard. By "the second end of the cable assembly 3 is connected to the pin in the slot C of the second connector 2" is meant that the cable assembly 3 is not connected to the second interface 40 described above with reference to fig. 3A and 3B, but is connected to the pin in the slot C.

The operating signals may include a power signal, a low-speed signal, and a high-speed signal. The power signal is provided to slot C by the motherboard. The high speed signal may comprise a PCIe high speed signal. The low speed signals may include at least one of an IIC signal for indicating whether the PCIe card is electrically connected to slot C, a bit signal including a communication signal of the PCIe card with the motherboard 10, a clock signal, and a reset signal. For example, the communication signal may include a status signal of a PCIe card within slot C.

Further, the low-speed signals include a first low-speed signal and a second low-speed signal, the first low-speed signal is sent by the motherboard to the PCIe card in the socket C, and illustratively, the first low-speed signal may include an IIC signal, a clock signal, and a reset signal, where the IIC signal may be provided by a chip on the motherboard. The second low speed signal is sent to the motherboard by the PCIe card within slot C, and illustratively the second low speed signal may include an IIC signal, which may be provided by a chip on the PCIe card, an in-bit signal. The high-speed signals comprise first high-speed signals and second high-speed signals, wherein the first high-speed signals are sent to the slot C by the main board, and the second high-speed signals are sent to the main board by the PCIe card in the slot C. The first high speed signal and the second high speed signal may both be PCIe high speed signals.

In the patch cable of the embodiment of the application, since the second end of the cable assembly 3 is directly connected with the pin in the slot C of the second connector 2, the working signal sent by the motherboard can sequentially pass through the first connector 1, the cable assembly 3 and the pin in the slot C of the second connector 2 to reach the PCIe card in the slot C, the second connector 2 does not need to be matched with a circuit board for use, for example, the second connector 2 does not need to be fixed by the circuit board, other interfaces are not needed to be arranged on the second connector 2 for communication connection with the circuit board, the working signal does not need to reach the PCIe card after passing through the circuit board, additional development of the circuit board can be avoided, meanwhile, the structure of the second connector 2 is simplified, so that the cost is reduced, the second connector 2 has smaller volume, the fixing mode is more flexible, for example, the working signal is fixedly installed in the slot of a sheet metal part, or the working signal is fixedly installed in the interval space between two adjacent parts, and the working range is beneficial to be enlarged. In addition, the cable signal resource can be simplified because the device on the circuit board does not need to be provided with a power signal or other signals because the circuit board is not relied on.

The second connector 2 may be a PCIe standard connector, such as a CEM (card electro-mechanical) connector, and a PCIe card is mounted in the slot C of the second connector 2. The CEM connector may be a pcie x16 standard interface. In addition, the first connector 1 may be a double density unified bus connector UBCDD (unified bus connector, UBC, unified bus connector; double density, DD, double density) connector. The adapter cable of the embodiment of the application can be a UBCDD-to-CEM cable, so that the low-speed signals of the original IIC and the like can be directly supplied to the CEM connector through the cable without passing through a PCB; because the PCB is not relied on, the development cost of the PCB is saved, power supply or signals are not needed to be provided for devices on the PCB, cable signal resources can be simplified, meanwhile, the second interface 40 above the CEM connector in the related technology can be removed, the UBCDD-CEM cable structure design is simplified, the size is reduced, the PCB is not limited to the PCB for fixing the CEM connector, the fixing mode is more flexible, and the cost is reduced.

Illustratively, the cable assembly 3 includes a first set of cables 31 for transmitting power signals, a second set of cables 32 for transmitting low speed signals, and one or more third sets of cables 33 for transmitting high speed signals, the number of the third sets of cables 33 being the same as the number of the second connectors 2. Wherein the third set of cables 33 may be a bus, for example, an X16 bandwidth or an X8 bandwidth.

With continued reference to fig. 4, the number of first connectors 1 is one and the number of second connectors 2 is one; the number of the third group of cables 33 is one. The first ends of the first group of cables 31, the second group of cables 32 and the third group of cables 33 are connected to one first connector 1, and the second ends of the first group of cables 31, the second group of cables 32 and the third group of cables 33 are connected to pins in the slot C of one second connector 2.

Fig. 5 is a schematic structural diagram of a signal transmission circuit according to a second embodiment of the present application. As shown in fig. 5, the number of the first connectors 1 is one, the number of the second connectors 2 is plural, and the number of the first group cables 31, the number of the second group cables 32, and the number of the third group cables 33 are the same as the number of the second connectors 2. The term "plurality" herein may include two and more, and illustratively, in fig. 5, the term "plurality" is taken as two. The first ends of each of the plurality of first-group cables 31, the plurality of second-group cables 32, and the plurality of third-group cables 33 are connected to one first connector 1. The second ends of the first group of cables 31 are connected with the second connectors 2 in a one-to-one correspondence manner, the second ends of the second group of cables 32 are connected with the second connectors 2 in a one-to-one correspondence manner, and the second ends of the third group of cables 33 are connected with the second connectors 2 in a one-to-one correspondence manner.

Fig. 6 is a schematic structural diagram of a signal transmission circuit according to a third embodiment of the present application. As shown in fig. 6, the number of the first connectors 1 is one, the number of the second connectors 2 is plural, the second ends of the first group of cables 31 include a plurality of first sub-connection ends L1, the second ends of the second group of cables 32 include a plurality of second sub-connection ends L2, and the number of the third group of cables 33 is plural. The term "plurality" herein may include two and more, and illustratively, in fig. 6, the term "plurality" is taken as two. The first ends of the first group of cables 31, the second group of cables 32 and the plurality of third group of cables 33 are connected to one first connector 1, and each first sub-connection end L1 is connected to each second connector 2 in a one-to-one correspondence. Each second sub-connection terminal L2 is connected to each second connector 2 in a one-to-one correspondence. The second ends of each third group of cables 33 are connected to each second connector 2 in a one-to-one correspondence. Because the first group of cables 31 and the second group of cables 32 adopt the bifurcation cable structure, the number of cables can be reduced, the processing and the manufacturing are convenient, and meanwhile, the structure of the switching cable is simpler.

In the signal transmission circuit of the embodiment of the application shown in fig. 5 and 6, the switching cable does not need to be matched with the circuit board for use, does not depend on the PCB board for signal switching, does not need to manage the PCB board, and therefore, the development cost of the PCB board is saved. And because the PCB CEM connector is not dependent, a stray signal interface is not required to be arranged, the stray signal interface structure can be removed, thereby optimizing the structure of converting UBCD into a CEM cable, enabling the CEM connector to be smaller in size, more flexible in installation of the CEM connector and more in selection. Meanwhile, the device on the PCB is not required to be provided with power signals or other signals because the device does not depend on the PCB, so that cable signal resources can be simplified.

Fig. 7 is a schematic partial structure of a computing device according to an embodiment of the present application. As shown in fig. 7, the computing device includes a PCIe card (not shown) and the signal transmission circuit described above. The PCIe card is connected to the signal transmission circuit through the second connector 2 of the signal transmission circuit. Each PCIe card may have a gold finger, and the signal transmission circuit may include a motherboard 10 and a patch cable 20. Motherboard 10 includes a circuit board 101, processors 102 disposed on circuit board 101, and connectors (not shown in fig. 7 obscured by UBCDD connectors), each processor 102 being electrically connected to at least a portion of the connectors by traces on circuit board 101. The first connector 1 of each patch cable 20 is correspondingly connected with a connector of the motherboard 10, and each PCIe card is installed in the slot C of the second connector 2 of the patch cable 20.

Wherein the computing device may be a server and the processor 102 may be a CPU. In a server system, a CPU on a motherboard provides PCIe signals (i.e., PCIe resources) and only wires to connectors on the board. When PCIe peripheral devices such as PCIe cards need to be connected, connection is directly performed through a UBCDD-to-CEM cable (i.e., the patch cable 20), so that internal wiring of the PCB is reduced, and loss generated when signals are transmitted on the wiring can be reduced because loss of the internal wiring of the PCB is relatively high.

Also, the patch cable 20 may include a first connector 1, a second connector 2, and a cable assembly 3. The first connector 1 is a motherboard-side connector (i.e., a connector connected to a motherboard) of the patch cable 20, and may be, for example, a UBCDD connector. The second connector 2 may be a CEM connector, such that the patch cable is a UBCDD-to-CEM cable. The number of the first connectors 1 may be one, and the first connectors 1 may be capable of satisfying all signals of the CEM connector by signals such as high-speed signals, low-speed signals, and power signals.

In fig. 7, the computing device illustratively employs the patch cable shown in fig. 4, i.e., one patch cable 20 includes one first connector 1 and one second connector 2. The circuit board 101 of the main board 10 is provided with n+1 CPUs, i.e., CPUs 0, … …, CPU n. Each CPU may be connected to a UBCDD connector of patch cable 20 through a connector on the motherboard.

In other examples, the number of the first connectors 1 may be two or more. Also, the number of the second connectors 2 may be one or two or more. The cable assembly 3 may include a high-speed cable (i.e., a cable transmitting a high-speed signal, such as the third group of cables 33 mentioned above), a low-speed cable (i.e., a cable transmitting a low-speed signal, such as the second group of cables 32 mentioned above), and a power cable (i.e., a cable transmitting a power signal, such as the first group of cables 31 mentioned above), and the motherboard-side connector may be directly connected with the CEM connector through the cable assembly 3.

In summary, considering that PCIe signals (e.g., PCIe signals sent by a CPU on a motherboard) are transmitted to the CEM connector through PCB traces (including traces on the motherboard and/or traces on a PCIe card carrier board, or "PCB" in "PCB traces" includes the motherboard and/or PCIe card carrier board), PCIe signals have larger loss on the PCB traces, and PCIe high-speed trace distances will be limited (in order to reduce the loss, generally, the trace distances are set to be shorter), so that the PCIe connectors are directly connected through the patch cable at present, thereby omitting traces on the PCIe card carrier board and reducing the loss. However, in the above scheme, the CEM connector needs to be matched with the circuit board, which requires additional development of the circuit board, and meanwhile, the CEM connector needs to be provided with a second interface for communication with the circuit board, which results in complex structure, large volume and high cost of the CEM connector, and the PCIe card connector of the patch cable is fixed through the circuit board, so that the fixing mode is single, which is not beneficial to expanding the application range.

The embodiment of the application provides a signal transmission circuit and a computing device comprising the same. In the signal transmission circuit, the second end of the cable assembly of the adapter cable is connected with the pin in the slot of the second connector, and the second connector does not need to be matched with the circuit board for use, for example, the second connector does not need to be fixed by the circuit board, so that an interface in communication connection with the circuit board is not needed to be arranged on the second connector, the additional development of the circuit board can be avoided, meanwhile, the structure of the second connector is simplified, the cost is reduced, the second connector is small in size, the fixing mode is more flexible, and the application range is enlarged. Further, because the circuit board is not relied on, power or signals are not required to be provided for devices on the circuit board, and cable signal resources can be simplified.

The last explanation is: the above embodiments are only for illustrating the technical solution of the present application, but are not limited thereto; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (10)

1. The utility model provides a signal transmission circuit which characterized in that, includes mainboard and patch cord, wherein, the patch cord includes:

a first connector (1), the first connector (1) being for connection with the motherboard;

a second connector (2), wherein a slot (C) is arranged on the second connector (2), and the slot (C) is used for installing a high-speed serial computer expansion bus PCIe card;

the cable assembly (3), the first end of cable assembly (3) with first connector (1) is connected, the second end of cable assembly (3) with pin connection in slot (C) of second connector (2), cable assembly (3) are used for transmitting the working signal, so that install PCIe card in second connector (2) can with the mainboard communicates, wherein, the working signal includes power signal, low-speed signal and high-speed signal.

2. The signal transmission circuit according to claim 1, wherein the high speed signal comprises a PCIe high speed signal and the second connector (2) is a PCIe standard connector.

3. The signal transmission circuit according to claim 1 or 2, wherein the low-speed signal includes at least one of an IIC signal for indicating whether the PCIe card is electrically connected to the slot (C), an in-place signal including a communication signal of the PCIe card with the motherboard, a clock signal, and a reset signal.

4. A signal transmission circuit according to any one of claims 1-3, characterized in that:

the power signal is provided to the slot (C) by the motherboard;

the low-speed signals comprise a first low-speed signal and a second low-speed signal, wherein the first low-speed signal is sent to the PCIe card in the slot (C) by the main board, and the second low-speed signal is sent to the main board by the PCIe card in the slot (C);

the high-speed signals comprise a first high-speed signal and a second high-speed signal, the first high-speed signal is sent to the slot (C) by the main board, and the second high-speed signal is sent to the main board by a PCIe card in the slot (C).

5. The signal transmission circuit according to any one of claims 1-4, wherein the cable assembly (3) comprises a first set of cables (31), a second set of cables (32) and a third set of cables (33), the first set of cables (31) being used for transmitting the power supply signal, the second set of cables (32) being used for transmitting the low speed signal, the third set of cables (33) being used for transmitting the high speed signal, the number of the third set of cables (33) being the same as the number of the second connectors (2).

6. The signal transmission circuit according to claim 5, wherein the number of the first connectors (1) is one and the number of the second connectors (2) is one;

the first ends of the first group of cables (31), the second group of cables (32) and the third group of cables (33) are connected with one first connector (1), and the second ends of the first group of cables (31), the second group of cables (32) and the third group of cables (33) are connected with one second connector (2).

7. The signal transmission circuit according to claim 5, wherein the number of the first connectors (1) is one, the number of the second connectors (2) is a plurality, and the number of the first group cables (31), the number of the second group cables (32) and the number of the third group cables (33) are the same as the number of the second connectors (2);

the first ends of the first group of cables (31), the second group of cables (32) and the third group of cables (33) are connected with one first connector (1), the second ends of the first group of cables (31) are connected with the second connectors (2) in a one-to-one correspondence manner, the second ends of the second group of cables (32) are connected with the second connectors (2) in a one-to-one correspondence manner, and the second ends of the third group of cables (33) are connected with the second connectors (2) in a one-to-one correspondence manner.

8. The signal transmission circuit according to claim 5, wherein the number of first connectors (1) is one, the number of second connectors (2) is a plurality, the second ends of the first group of cables (31) comprise a plurality of first sub-connection ends (L1), the second ends of the second group of cables (32) comprise a plurality of second sub-connection ends (L2), and the number of the third group of cables (33) is a plurality;

the first ends of the first group of cables (31), the second group of cables (32) and the plurality of third group of cables (33) are connected with one first connector (1), each first sub-connecting end (L1) is connected with each second connector (2) in a one-to-one correspondence manner, each second sub-connecting end (L2) is connected with each second connector (2) in a one-to-one correspondence manner, and the second ends of the third group of cables (33) are connected with each second connector (2) in a one-to-one correspondence manner.

9. The signal transmission circuit according to any one of claims 1-8, wherein the first connector (1) is a double density unified bus connector.

10. A computing device, comprising:

the signal transmission circuit and PCIe card of any one of claims 1-9, said PCIe card being connected to said signal transmission circuit through said second connector (2) of said signal transmission circuit.