CN117178369A - Semiconductor device, electronic apparatus, and method of forming semiconductor device - Google Patents

Semiconductor device, electronic apparatus, and method of forming semiconductor device Download PDF

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Publication number
CN117178369A
CN117178369A CN202180097201.6A CN202180097201A CN117178369A CN 117178369 A CN117178369 A CN 117178369A CN 202180097201 A CN202180097201 A CN 202180097201A CN 117178369 A CN117178369 A CN 117178369A
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China
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semiconductor device
layer
substrate
nucleation layer
forming
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Chinese (zh)
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段焕涛
倪茹雪
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The embodiment of the application provides a semiconductor device, electronic equipment and a method for forming the semiconductor device, relates to the technical field of semiconductors, and is high in compatibility degree with the existing technology. The semiconductor device includes a substrate, which is a substrate including silicon, and a nucleation layer disposed on the substrate. Wherein the nucleation layer comprises a P-type impurity capable of binding hydrogen and the P-type impurity comprises an element in group I I, for example, may include magnesium, calcium, etc.; the substrate contains a first substance including a substance obtained by combining an element in group IIA with hydrogen, and the first substance may be, for example, a substance obtained by combining Al with hydrogen. The first substance is contained in the substrate, so that the formation of the P-type parasitic channel is restrained.

Description

Semiconductor device, electronic apparatus, and method of forming semiconductor device Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device, an electronic device including the semiconductor device, and a method of forming the semiconductor device.
Background
Semiconductor devices made of compound semiconductor materials, such as Gallium Nitride (GaN) -based high electron mobility transistors (High Electron Mobility Transistor, HEMT), have been widely used in the fields of high-power radio frequency devices, high-voltage-resistant switching devices, and the like, for example, in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment, and the like, due to their high breakdown voltage and high electron mobility characteristics.
However, the performance of current semiconductor devices based on compound semiconductor materials is not very ideal, such as output power, switching speed, power gain and efficiency, and further optimization is required.
Disclosure of Invention
The application provides a semiconductor device, electronic equipment and a method for forming the semiconductor device, and mainly aims to provide a semiconductor device with better performance.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:
in a first aspect, the present application provides a semiconductor device that may be used in a radio frequency device, or in a charging device, or in other devices. The semiconductor device includes: a substrate and a forming layer disposed on the substrate, the substrate being a substrate comprising silicon, where the forming layer may be, for example, a silicon film formed of
The group IIIA nitride is formed to form a layer including a nucleation layer, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. Wherein the nucleation layer comprises a P-type impurity capable of binding hydrogen, the P-type impurity comprising an element of group II, such as may include magnesium, calcium, etc.; the substrate contains a first substance including a substance obtained by combining an element in group IIIA with hydrogen, and the first substance may be, for example, a substance obtained by combining Al with hydrogen.
In a semiconductor device including a nucleation layer, for example, the nucleation layer includes a group IIIA nitride, and thus, a group IIIA substance in the nucleation layer is easily diffused into a substrate, for example, aluminum (Al), and thus a P-type parasitic channel is easily formed as an acceptor impurity in the substrate including a silicon material.
In the semiconductor device provided in the embodiment of the application, the nucleation layer contains P-type impurities, for example, magnesium (Mg), and the P-type impurities can be combined with the reaction gas hydrogen gas to form a complex in the formation process of the semiconductor device, that is, the formed complex stabilizes a hydrogen substance in the nucleation layer, and then, in the formation process or annealing process of the rest of the semiconductor device, the complex formed by the P-type impurities and the hydrogen breaks chemical bonds between the P-type impurities and the hydrogen due to high temperature, so that the hydrogen substance in a free state can diffuse into the substrate, and can be combined with acceptor impurities diffused into the substrate as donor impurities to passivate acceptor impurities in the substrate, thereby inhibiting the formation of P-type parasitic channels, or even if the P-type parasitic channels are formed, the conductivity of the formed P-type parasitic channels is low, and the performance of the semiconductor device is not greatly affected.
In a possible implementation manner of the first aspect, the P-type impurity includes an element in group IIA.
The group IIA element is selected as the P-type impurity because the group IIA element is easily combined with a hydrogen substance to form a complex, for example, one or a combination of at least two of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) may Be selected.
In addition, the P-type impurity may be one or a combination of at least two of zinc (Zn), carbon (C), mercury (Hg), and cadmium (Cd).
In a possible implementation manner of the first aspect, the P-type impurity includes magnesium.
Because Mg in P-type impurities has a small ionization energy compared to other P-type impurities, is easy to dope, and also is easy to combine with hydrogen species to form a complex.
In addition, the ionization energy of magnesium entering the nucleation layer is higher than that of IIIA group substances in the nucleation layer, so that holes generated by Mg ionization are much lower than the concentration of actual Mg doping, mg is taken as acceptor impurities, the nucleation layer can be in an N type due to dislocation, vacancy and impurities, and then the holes and electrons generated by magnesium ionization are compensated, so that a conductive channel is not introduced into the nucleation layer.
In a possible implementation manner of the first aspect, the concentration of the P-type impurity may be selected as: less than or equal to 1X 10 22 cm -3 。
To achieve a high hole concentration P-type material, a high concentration of P-type impurity doping, such as a high concentration of Mg doping, is required. While Mg is limited in solubility in group IIIA nitride materials (e.g., gaN), high incorporation cannot be achieved. When the doping concentration reaches a certain degree, the impurity concentration of Mg is increased, and the Mg can be combined with the nitrogen of the reaction gas to form Mg 3 N 2 But not enter the GaN lattice, thereby affecting the crystal quality of the GaN material. And when the Mg doping concentration is large, mg atoms will be at interstitial sites between lattices (Mg at interstitial sites between lattices is called Mgi) instead of substitutional Ga atoms (Mg is substituted for Ga and MgGa substitutional atoms), mgi will be in combination with a large number of N vacancies (V) N ) Composition Complex (Mgi-V) N ) The complex exhibits donor properties, resulting in a self-compensating effect of Mg atoms.
Therefore, the concentration of the P-type impurity is required and cannot be too small, otherwise, the formation of the P-type parasitic channel cannot be suppressed, nor too large, because the quality of the group IIIA nitride nucleation layer is affected and even the performance of the semiconductor device is deteriorated.
In a possible implementation manner of the first aspect, further, the concentration of the P-type impurity is: less than or equal to 1X 10 21 cm -3 。
In a possible implementation manner of the first aspect, when the P-type impurity selects magnesium (Mg), a concentration of magnesium may be selected as: 1X 10 18 cm -3 Up to 1X 10 21 cm -3 。
In a possible implementation manner of the first aspect, the nucleation layer includes a second substance, where the second substance includes a substance obtained by combining an element in group II with hydrogen.
The reason for the presence of the second substance is: during the annealing process, chemical bonds present in the second species of the nucleation layer are not completely broken, and a portion remains in the nucleation layer.
In a possible implementation manner of the first aspect, the first substance is located in a region of the substrate close to the nucleation layer.
In a possible implementation manner of the first aspect, the nucleation layer includes an aluminum nitride AlN material.
That is, a P-type impurity capable of binding hydrogen is doped in a group IIIA nitride nucleation layer comprising an aluminum nitride AlN material. The lattice arrangement in the group IIIA nitride nucleation layer containing the aluminum nitride AlN material is not very regular, and the purpose of arranging the group IIIA nitride nucleation layer is to enable the lattice arrangement of the channel layer grown on the group IIIA nitride nucleation layer to be more regular, so that the performance of the channel layer is better. In the embodiment of the application, the P-type impurities are doped in the IIIA nitride nucleation layer with a not very regular lattice, so that the damage to the lattice arrangement in the IIIA nitride nucleation layer is not very serious, and the performance of the IIIA nitride nucleation layer is not very influenced. Also, the aluminum species in the aluminum nitride nucleation layer diffuses into the substrate as acceptor impurities, and aluminum combines readily with the free hydrogen species to form a stable complex.
In a possible implementation manner of the first aspect, the channel layer includes a gallium nitride GaN material.
It will be appreciated that the group IIIA nitride nucleation layer comprising an aluminum nitride AlN material may ensure a more ordered lattice arrangement in the group IIIA nitride channel layer comprising a gallium nitride GaN material, increasing the density and mobility of the two-dimensional electron gas (two-dimensional electron gas,2 DEG) in the group IIIA nitride channel layer.
In a possible implementation manner of the first aspect, the barrier layer includes an aluminum gallium nitride AlGaN material.
For example, a group IIIA nitride barrier layer is disposed on top of the group IIIA nitride channel layer, the group IIIA nitride barrier layer being adapted to cooperate with the group IIIA nitride channel layer to generate a 2DEG by polarization at a region where the group IIIA nitride channel layer meets the group IIIA nitride barrier layer, thereby conducting current.
In a possible implementation manner of the first aspect, the semiconductor device further includes: a transition layer disposed between the nucleation layer and the channel layer, where the transition layer may also include a group IIIA nitride.
In a possible implementation manner of the first aspect, the transition layer is a transition layer structure with gradually changed composition (compositionally graded).
In a second aspect, the present application also provides a method of forming a semiconductor device, the method of forming a semiconductor device comprising:
doping P-type impurities in the IIIA nitride, wherein the P-type impurities comprise elements in group II, and forming a nucleation layer on a substrate containing silicon under the condition that the reaction gas comprises hydrogen so that the nucleation layer is doped with the P-type impurities;
and annealing the structure comprising the substrate and the nucleation layer to obtain the semiconductor device, wherein the substrate comprises a first substance, and the first substance comprises a substance obtained by combining an element in IIIA group with hydrogen.
In the method for forming the semiconductor device, the P-type impurity is doped in the nucleation layer, and the carrier gas of the organic metal reaction source for forming the nucleation layer is hydrogen. In this way, the P-type impurity is able to combine with hydrogen to form a complex, i.e., to stabilize the hydrogen in the formed complex; and then annealing the semiconductor device, wherein in the annealing process, annealing treatment is generally carried out in nitrogen atmosphere, so that chemical bond rupture between the P-type impurity and hydrogen occurs in the complex containing the hydrogen substance, the free hydrogen substance can be diffused into the substrate and used as donor impurity to be combined with acceptor impurity diffused into the substrate so as to passivate the acceptor impurity in the substrate, therefore, a P-type parasitic channel is basically not formed in the semiconductor device formed by adopting the method, and even if the P-type parasitic channel is formed, the conductivity of the formed P-type parasitic channel is very low.
Also, by doping the material forming the nucleation layer with a P-type impurity to dope the nucleation layer with the P-type impurity, after the chemical bond rupture of the complex obtained by combining the P-type impurity with hydrogen, hydrogen can rapidly enter the substrate along a short path to suppress the formation of a P-type parasitic channel.
In addition, the P-type impurities enter the nucleation layer by doping the P-type impurities in the IIIA nitride material instead of ion implantation and the like, and the ion implantation method is to take out at least part of the IIIA nitride forming layer from the reaction chamber and then carry out ion implantation process.
In a possible implementation manner of the second aspect, when the group IIIA nitride is doped with a P-type impurity, the P-type impurity contains an element in group IIA. For example, one or a combination of at least two of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) may Be selected.
In a possible implementation manner of the second aspect, when doping P-type impurities in the group IIIA nitride, the concentration of the doped P-type impurities is: less than or equal to 1X 10 22 cm -3 。
The P-type impurity with the concentration can inhibit the formation of a P-type parasitic channel and does not influence the quality of the IIIA nitride nucleation layer.
In a possible implementation manner of the second aspect, when forming a nucleation layer on a surface of a substrate, the method includes: magnesium species (e.g., magnesium-dicyclopentadiene) are doped in the process for forming the nucleation layer to dope the nucleation layer with magnesium as a P-type impurity capable of combining with hydrogen.
Because Mg in P-type impurities has a small ionization energy compared to other P-type impurities, is easy to dope, and also is easy to combine with hydrogen species to form a complex.
In a possible implementation manner of the second aspect, when the material for forming the nucleation layer is doped with a magnesium substance, the concentration of magnesium is: 1X 10 18 cm -3 Up to 1X 10 21 cm -3 。
In a possible implementation manner of the second aspect, when annealing a structure including the substrate and the nucleation layer, the annealing is performed in an atmosphere including nitrogen.
It is understood that when annealing is performed in an atmosphere of nitrogen gas without hydrogen gas, the chemical bond of the complex obtained by combining the P-type impurity with hydrogen is continuously broken, so that the hydrogen species is in a free state.
In a possible implementation manner of the second aspect, after forming the nucleation layer on the substrate, before performing the annealing treatment, the method further includes: forming a channel layer on the nucleation layer; a barrier layer is formed on the I channel layer.
Thus, a semiconductor device including a nucleation layer, a channel layer, and a barrier layer is formed.
In a third aspect, the present application further provides an electronic apparatus, including a circuit board and the semiconductor device in any implementation manner of the first aspect or the semiconductor device manufactured in any implementation manner of the second aspect, where the circuit board is electrically connected to the semiconductor device.
The electronic device provided by the embodiment of the application comprises the semiconductor device manufactured by the embodiment of the first aspect or the embodiment of the second aspect, so that the electronic device provided by the embodiment of the application and the semiconductor device of the technical scheme can solve the same technical problems and achieve the same expected effects.
Drawings
Fig. 1 is a schematic diagram of a part of a base station;
FIG. 2 is an exploded view of a part of the structure of a mobile phone;
fig. 3 is a schematic diagram of a part of the structure of some electronic devices such as a base station or a mobile phone;
fig. 4 is a schematic structural view of a semiconductor device;
fig. 5 is a schematic structural view of another semiconductor device;
FIG. 6 illustrates a schematic diagram of the formation of a P-type parasitic channel in the structure of FIG. 5;
fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic structural view of a semiconductor device according to an embodiment of the present application;
fig. 9 is a flow chart of a method of forming a semiconductor device according to an embodiment of the present application;
FIG. 10 is a schematic diagram of suppressing P-type parasitic channel formation according to an embodiment of the present application;
fig. 11 is a flow chart of a method of forming a semiconductor device according to an embodiment of the present application;
fig. 12 is a schematic diagram of a structure corresponding to a method for manufacturing a semiconductor device according to an embodiment of the present application after each step is completed;
fig. 13 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
Reference numerals:
11-a middle frame; 110-frame; 111-carrier plates; 12-a rear shell; 13-a display screen; 01-a circuit board; 021-semiconductor device; 022-electrical connection structure; 023-a package substrate; 03-another electrical connection structure;
1-a substrate; a group 2-IIIA nitride forming layer; 3-source; 4-grid; 5-drain electrode; 21-a nucleation layer; 22-a transition layer; 23-a channel layer; 24-an interposer; 25-barrier layers; 26-cap layer.
Detailed Description
Embodiments of the present application provide an electronic device that may include a communication device (e.g., a base station, a cell phone), a wireless charging device, a medical device, a radar, a navigation device, a Radio Frequency (RF) plasma lighting device, an RF induction and microwave heating device, and so forth. The embodiment of the application does not limit the specific form of the electronic device.
In the above electronic devices, basically, the electronic devices include semiconductor devices, for example, a Power Amplifier (PA), where the PA mainly amplifies a radio frequency signal, and fig. 1 shows a simple schematic structure of a base station, which includes a control unit, where the control unit includes a radio transceiver, an antenna, a related signal processing circuit, and the like, and the control unit mainly includes four components: cell controllers, voice channel controllers, signaling channel controllers, and multi-way interfaces for expansion. The control unit of a base station generally controls several base transceiver stations, and is responsible for all mobile communication interface management, mainly allocation, release and management of radio channels, etc., by remote commands of the transceiver stations and the mobile stations.
With continued reference to fig. 1, the base station further includes a transmission unit connected to the core network, and control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and the control unit processes the services.
Referring to fig. 1, the base station further includes a baseband unit and a Radio Frequency (RF) unit, where the baseband unit mainly performs functions of baseband modulation and demodulation, radio resource allocation, call processing, power control, soft handoff, and the like. The RF unit mainly completes conversion between an air radio frequency channel and a baseband digital channel, amplifies signals by a Power Amplifier (PA), sends the signals to an antenna through a radio frequency feeder line for transmission, and terminal equipment such as a mobile phone (mobile phone), a tablet personal computer (pad) and the like receives radio waves transmitted by the antenna through a wireless channel, and demodulates signals belonging to the user.
With continued reference to fig. 1, the base station further includes a power supply unit, which may be used to supply power to the transmission unit, the baseband unit, the control unit, and other structures.
Fig. 2 shows a block diagram of another electronic device, such as a mobile phone, which may include a center 11, a rear case 12, and a display 13. The middle frame 11 includes a carrying board 111 for carrying the display 13, and a frame 110 surrounding the carrying board 111 for a circle, wherein the carrying board 111 carries an RF unit and a PA device, and the PA device amplifies a signal output by the RF unit and feeds the amplified signal to an antenna in the mobile phone (for example, the antenna may be disposed along an edge of the frame 110) to send and receive the signal.
In some embodiments, a device formed of Laterally Diffused Metal Oxide Semiconductor (LDMOS) may be employed as PA, or a device formed of gallium arsenide (GaAs) may be employed as PA.
With the development of the fourth generation mobile communication technology (4rd generation of wireless communications technologies,4G) to the fifth generation mobile communication technology (5rd generation of wireless communications technologies,5G), the requirement on the function of amplifying radio frequency signals of the PA is also increasing, for example, compared with 4G network communication, the communication frequency band of 5G is shifted to a high frequency band, for example, to 3GHz to 5 GHz.
Gallium arsenide (GaAs) devices have the prominent disadvantage of lower power (e.g., power typically below 50W) and LDMOS devices have the prominent disadvantage of limited operating frequencies (operating frequencies typically below 3 GHz). Therefore, gallium arsenide (GaAs) devices and LDMOS cannot meet the requirements of a 5G communication network, but gallium nitride (GaN) radio frequency power devices embody the high frequency performance of the gallium arsenide devices, and meanwhile, the power processing capability of the LDMOS devices is combined, so that the requirements of 5G high communication frequency bands, high power and the like can be met, and the application range of the gallium nitride (GaN) devices is wider and wider.
As shown in fig. 3, the semiconductor device 021 of the above-described apparatus is carried on a package substrate 023, and the semiconductor device 021 is provided on the package substrate 023 by an electrical connection structure (e.g., a metal layer) 022 so that the semiconductor device 021 can be signal-interconnected with other electronic devices on the package substrate 023. The package substrate 023 is further disposed on the circuit board 01, such as a printed circuit board (printed circuit board, PCB), by another electrical connection 03, where the other electrical connection 03 may be a Ball Grid Array (BGA) or other electrical connection.
The semiconductor device 021 shown in fig. 3 may include a structure as shown in fig. 4, and fig. 4 is a sectional structure diagram of the semiconductor device 021, the semiconductor device 021 including: the semiconductor device includes a substrate, a GaN layer and an aluminum gallium nitride (AlGaN) layer grown on the substrate, and a source, a gate and a drain disposed over the AlGaN layer.
During the growth of the structure shown in fig. 4, the following phenomenon occurs. For example, one phenomenon is: at high temperature, silicon (Si) in the substrate is easy to react with gallium (Ga) (which can be called back melting etching) to form silicon-gallium eutectic alloy, so that pits appear on the surfaces of the GaN layer and the AlGaN layer or holes appear in the GaN layer and the AlGaN layer; another phenomenon is: there is a large lattice mismatch and thermal mismatch between Si and GaN in the substrate, which creates tensile stress in the GaN layer, forming a large number of lattice threading dislocations that, if continued to extend toward the surface of the AlGaN layer, crack the surface of the AlGaN layer.
In order to avoid the two phenomena, as shown in fig. 5, fig. 5 is a cross-sectional structure diagram of another semiconductor device 021, and in combination with fig. 5, an aluminum nitride (AlN) layer is generally grown before a GaN layer structure is grown on a substrate, where the AlN layer serves as a barrier layer to prevent the non-return melt etching, so as to avoid the formation of hole pits, and on the other hand, to alleviate lattice mismatch and thermal mismatch between the substrate and GaN.
However, as shown in fig. 6, in the semiconductor device 021 with an AlN layer interposed, aluminum (Al) in the AlN layer is easily diffused into a silicon substrate, and acceptor impurities (which may also be called P-type impurities) exist within a certain range below the substrate surface to form P-type parasitic channels (as shown by the dotted line boxes in fig. 3).
In the above-described semiconductor device, it is desirable to mitigate the effect of the parasitic channel, because the parasitic channel may significantly increase the parasitic loss of the semiconductor device, so when the effect of the parasitic channel in the semiconductor device is mitigated, or the formation of such a parasitic channel is suppressed or prevented, the parasitic loss in the resulting semiconductor device may be significantly reduced, which may result in an improvement in the performance of the semiconductor device, such as the semiconductor device having higher output power, power gain, efficiency, and other advantages. Also, in some power switching devices, lower turn-on shifts, turn-on degradation, etc. may be exhibited.
The embodiment of the application provides a semiconductor device which can inhibit the formation of a P-type parasitic channel and further can improve the performance of the semiconductor device.
The semiconductor device of the present application will be described in detail with reference to the accompanying drawings.
Referring to fig. 7, fig. 7 is a cross-sectional view of a semiconductor device 021, the semiconductor device 021 comprising: substrate 1, group IIIA nitride forming layer 2 disposed on surface 101 of substrate 1, and Source (Source) 3, gate (Gate) 4 and Drain (Drain) disposed on a surface of group IIIA nitride forming layer 2 remote from substrate 1
5。
In alternative embodiments, a metal-organic chemical vapor deposition (metal-organic chemical vapor deposition, MOCVD) or molecular beam epitaxy (molecular beam epitaxy, MBE) may be used as a growth technique to grow the group IIIA nitride forming layer 2 on the substrate 1.
The substrate 1 described above may comprise silicon and it may be explained as such that the substrate 1 comprising silicon, as in fig. 7, the surface 101 of the substrate 1 may be a silicon surface. For example, in some embodiments, surface 101 may correspond to a surface of a silicon wafer. In other embodiments, surface 101 may correspond to a silicon surface of a composite substrate (e.g., including a silicon layer and one or more underlying layers disposed below the silicon layer). In other embodiments, surface 101 may correspond to a surface of a silicon portion of a silicon-on-insulator substrate. In still other embodiments, surface 101 may correspond to a surface of a silicon substrate on sapphire. In still other embodiments, surface 101 may correspond to a silicon surface of an oxygen-implanted isolation substrate.
In addition, the substrate 1 may be a high-resistance substrate containing silicon, for example, the high-resistance substrate containing silicon may be a substrate structure having a resistivity of 1000 Ω·cm or more, or may be a substrate structure having a resistivity of 2000 Ω·cm or more, or may be a substrate structure having a resistivity of 5000 Ω·cm or more.
The use of the high resistance silicon-containing substrates described above is particularly useful in devices operating at high frequencies (e.g., RF devices), for example, where high resistivity can reduce substrate loss and optimize semiconductor device performance.
It is understood that group IIIA nitride forming layer 2 shown in fig. 7 is made of any group IIIA nitride material, and that group IIIA nitride forming layer 2 is made of any group IIIA element nitride compound. For example, the group IIIA nitride material may include one or a combination of at least two of Boron Nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), thallium nitride (TIN), and aluminum gallium nitride (AlGaN), or may include any alloy formed from group IIIA elements and group VA elements, such as indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), gallium arsenic phosphorus nitride (GaAsPbN), aluminum indium gallium arsenic phosphorus nitride (AlInGaAsPbN), and the like.
The following description will be made of the structure that can be achieved by the group IIIA nitride forming layer 2, for example, as shown in fig. 7, a structure of the group IIIA nitride forming layer 2 is given, and of course, the group IIIA nitride forming layer 2 of the present application is not limited to the structure shown in fig. 7, and at least one other structure may be added to the structure shown in fig. 7 or some structures may be removed from the structure shown in fig. 7.
Taking fig. 7 as an example for illustration, the group IIIA nitride forming layer 2 includes a nucleation layer 21, which nucleation layer 21 may be formed on the surface 101 of the substrate 1, i.e. may be directly covered on the surface 101 of the substrate 1.
The purpose of the nucleation layer 21 is to: in some cases, it may be difficult to heteroepitaxially grow a group IIIA nitride material (e.g., gallium nitride or other group IIIA nitride) directly on substrate 1 by forming nucleation layer 21 on substrate 1 and then growing the remaining group IIIA nitride material (e.g., gallium nitride) on nucleation layer 21, such that in some examples nucleation layer 21 may be utilized to mitigate differences in the coefficient of thermal expansion of the group IIIA nitride material grown above nucleation layer 21 from the coefficient of thermal expansion of substrate 1 below nucleation layer 21; in other examples, nucleation layer 21 may be utilized to mitigate the difference in crystal lattice of group IIIA nitride material grown above nucleation layer 21 from the crystal lattice of substrate 1 below nucleation layer 21, as will also be appreciated that the lattice or thermal mismatch of substrate 1 and gallium nitride may be mitigated by nucleation layer 21 to provide a more orderly growth of the crystal lattice of gallium nitride or other group IIIA nitride.
The nucleation layer 21 may comprise an aluminum nitride (AlN) material. The aluminum nitride (AlN) material is understood to mean aluminum nitride (AlN) and any alloy thereof, such as aluminum gallium nitride (AlGaN), aluminum indium nitride
(AlInN), aluminum indium gallium nitride (AlInGaN), aluminum indium gallium arsenide phosphide (AlInGaAsPbN), and the like. Among these aluminum nitride (AlN) alloys, aluminum has a high concentration and may contain at least one of gallium and indium in a small amount, or gallium and indium are not included, that is, the alloy concentration is relatively small with respect to the aluminum concentration.
The nucleation layer 21 may comprise a one-layer structure or at least two-layer structure. When the nucleation layer 21 comprises at least two layers, these multiple layers may be made of the same material or of different materials. In addition, when the nucleation layer 21 includes at least two layers, these multilayer structures may be formed using different semiconductor growth conditions. These differences in semiconductor growth conditions may include differences in growth temperature, growth pressure, or reactant flow rates, among others.
With continued reference to fig. 7, the group IIIA nitride forming layer 2 further includes a transition layer 22, and the transition layer 22 may be formed on a side of the nucleation layer 21 remote from the substrate 1, that is, on the nucleation layer 21.
In some alternative embodiments, the transition layer 22 is formed of a compositionally graded (compositionally graded) group IIIA nitride material, e.g., the transition layer 22 may comprise AlxGa (1-x) N, where x may decrease gradually in the growth direction (i.e., in the P direction away from the substrate 1 as shown in fig. 7), e.g., x may decrease from a value of 1 to a value of 0.
The compositionally graded transition layer 22 may be graded according to the exemplary rules described below.
For example, x in the composition of AlxGa (1-x) N continuously tapers from a value of 1 at the surface of the lower surface 102 of the transition layer 22 to a value of 0 at the upper surface 103 of the transition layer 22.
For another example, x in the composition of AlxGa (1-x) N discontinuously tapers from a value of 1 at the surface of the lower surface 102 of the transition layer 22 to a value of 0 at the upper surface 103 of the transition layer 22. For example, alN, al is used from the surface of the lower surface 102 of the transition layer 22 to the upper surface 103 of the transition layer 22 0.6 Ga 0.4 N and Al 0.4 Ga 0.6 N and Al 0.2 Ga 0.8 N is discontinuously graded.
For another example, x in the composition of AlxGa (1-x) N tapers parabolic from a value of 1 at the surface of the lower surface 102 of the transition layer 22 to a value of 0 at the surface of the upper surface 103 of the transition layer 22; or in other continuous or discontinuous gradual variations.
Additionally, in some alternative embodiments, a gallium nitride alloy such as AlxInyGa (1-x-y) N, inyGa (1-y) N may be selected for formation. The concentration of the alloying element, e.g., at least one of Ga, al, in, varies along the thickness of the transition layer. By way of example, at least one of x and y may be varied when the transition layer has an AlxInyGa (1-y) N composition. As yet another example, in certain embodiments of the transition layer InyGa (1-y) N composition, y may be varied.
With continued reference to fig. 7, the group IIIA nitride forming layer 2 further includes a channel layer 23, and the channel layer 23 may be formed on a side of the transition layer 22 remote from the nucleation layer 21, that is, on the transition layer 22.
The channel layer 23 may include a gallium nitride (GaN) material. As shown in fig. 7, when the upper surface 103 of the transition layer 22 is made of GaN material and the channel layer 23 is also made of GaN material, the transition layer 22 of GaN material is generally doped (for example, doped with carbon or iron) to suppress leakage, but the channel layer 23 of GaN material is used for current, and a high-quality low-impurity GaN epitaxial layer is required.
With continued reference to fig. 7, the group IIIA nitride forming layer 2 further includes an insertion layer 24, and the insertion layer 24 may be formed on a side of the channel layer 23 remote from the transition layer 22, that is, on the channel layer 23.
The intercalating layer 24 may comprise an AlN material, may produce a higher concentration of two-dimensional electron gas by the polarizing effect of the AlGaN, alN, gaN structure, and may reduce the penetration of the two-dimensional electron gas into the barrier layer, and may reduce disordered scattering of the alloy by the intercalating layer 24, thereby improving mobility, which may be beneficial for improving the output characteristics of the device.
With continued reference to fig. 7, the group IIIA nitride forming layer 2 further includes a barrier layer 25, and the barrier layer 25 may be formed on a side of the insertion layer 24 away from the channel layer 23, that is, on the insertion layer 24.
The barrier layer 25 may include an AlGaN material, and may include at least one of AlInN or AlInGaN in combination with AlGaN, wherein the aluminum content in the barrier layer 25 is different from the aluminum content in the transition layer 22 and the channel layer 23.
The barrier layer 25 is used in cooperation with the channel layer 23 to generate two-dimensional electron gas (two-dimensional electron gas,2 DEG) by polarization between the channel layer 23 and the barrier layer 25, thereby conducting current.
With continued reference to fig. 7, the group IIIA nitride forming layer 2 further includes a cap layer 26, and the cap layer 26 may be formed on a side of the barrier layer 25 remote from the interposer 24, i.e., formed over the barrier layer 25.
In some alternative embodiments, cap layer 26 comprises a GaN material, and in the case where the cladding layer comprises GaN, the resulting surface morphology may be smoother and less surface defects relative to a surface formed in the absence of the cladding layer. In addition, the GaN material is adopted to stop the growth of the epitaxial layer, and the subsequent chemical treatment of the surface of the epitaxial layer is facilitated.
In the above-described semiconductor device 021, as shown in fig. 8, fig. 8 shows the microstructure in the nucleation layer 21 and the substrate 1, and at least one species including a species obtained by combining an element in group IIIA with hydrogen is contained in the region of the substrate 1 near the nucleation layer 21, as shown in a circle structure in the substrate 1 in fig. 8, a P-type parasitic channel is not formed due to the presence of the species, and in addition, a P-type impurity containing a group II element is contained in the nucleation layer 21, as shown in a black circle in fig. 8, the P-type impurity containing a group II element can be combined with hydrogen.
How the P-type parasitic channel is suppressed is explained below by describing the formation method of the structure shown in fig. 8.
Fig. 9 is a process flow diagram of a method of forming the semiconductor device shown in fig. 8, and fig. 10 is a cross-sectional view of the semiconductor device after each step of the process flow for manufacturing the semiconductor device is completed.
Referring to step S1 of fig. 9 and the structure of (a) of fig. 10, fig. 10 (a) is the structure after step S1 is completed, and step S1 includes: a P-type impurity is doped in the group IIIA nitride, the P-type impurity containing an element in group II, and a nucleation layer 21 of the group IIIA nitride is formed on the substrate 1 containing silicon in a case where the reaction gas includes hydrogen gas, so that the nucleation layer 21 of the group IIIA nitride is doped with the P-type impurity.
Step S1 is explained in detail below in connection with fig. 10.
In fig. 10, taking Mg as an example of the P-type impurity, when forming the nucleation layer 21 of group IIIA nitride on the substrate 1 containing silicon, at least one of group II is doped in the group IIIA nitride material for forming the nucleation layer 21 of group IIIA nitride, and the reaction gas for growing the nucleation layer 21 of group IIIA nitride includes hydrogen, at least two phenomena occur during the growth, one phenomenon being that the group IIIA substance in group IIIA nitride diffuses into the substrate 1 containing silicon as shown in (a) of fig. 10, for example, that Al diffuses toward the substrate 1 as an acceptor, and thus, a P-type parasitic channel is formed in the region of the substrate 1 near the nucleation layer 21 of group IIIA nitride, and the region with black dots as shown in (a) of fig. 10 represents the P-type parasitic channel; another phenomenon is that, as shown in (a) of fig. 10, P-type impurity Mg is combined with H to form a complex, which may be represented by Mg-H.
Fig. 10 is an illustration of P-type impurities as Mg, but at least one of group II may Be used in addition to Mg, for example, one or a combination of at least two of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba) in group IIA; for another example, one or a combination of at least two of zinc (Zn), carbon (C), mercury (Hg), cadmium (Cd) in group IIB may be employed; for another example, a combination of at least two of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), carbon (C), mercury (Hg), and cadmium (Cd) may Be employed.
In some alternative embodiments, the material forming nucleation layer 21 is doped with Mg impurities, for example, may be doped with a magnesium-bis (C 10 H 10 Mg), and the like.
Referring to step S2 of fig. 9 and the structure of (b) of fig. 10, fig. 10 (b) is the structure after step S2 is completed, and step S2 includes: the structure including the nucleation layer 21 of the group IIIA nitride and the substrate 1 is annealed to produce a semiconductor device, and a first substance is included in a region of the substrate 1 near the nucleation layer 21 of the group IIIA nitride, the first substance including a substance obtained by combining a substance in the group IIIA with hydrogen.
Step S2 is explained in detail below in connection with fig. 10.
After step S1 shown in fig. 10 (a) is completed, a P-type parasitic channel is formed in the region of the substrate 1 near the nucleation layer 21 of the group IIIA nitride, and a substance formed by combining at least one of group II with hydrogen, for example, a complex formed by combining magnesium with hydrogen, is contained in the region of the nucleation layer 21 of the group IIIA nitride near the substrate 1.
Upon completion of step S1 and further step S2, as shown in fig. 10 (b), in the annealing process, a complex formed by P-type impurities and hydrogen breaks down the chemical bond between P-type impurities and hydrogen, for example, the chemical bond between Mg and H in mg—h complex shown in fig. 10 (b) is broken down, and further, H becomes free, so that the hydrogen species in free state diffuses into the substrate 1, and combines with acceptor impurities (for example, al) diffused into the substrate as donor impurities to passivate acceptor impurities in the substrate, and thus, P-type parasitic channels are broken down, or even if P-type parasitic channels are formed, the conductivity of the formed P-type parasitic channels is low, and the performance of the semiconductor device is not greatly affected.
A P-type impurity containing at least one of group II is formed in the nucleation layer 21 because the lattice arrangement is not very uniform in the nucleation layer 21, the purpose of which is to make the lattice arrangement of the channel layer grown thereon more uniform and the channel layer performance is better. In the embodiment of the present application, the P-type impurity containing at least one of group II is doped in the nucleation layer 21 whose lattice is not very ordered, so that the damage to the lattice arrangement in the nucleation layer 21 is not very serious, and the performance of the nucleation layer 21 is not very affected. In addition, after the doped P-type impurity located in the nucleation layer 21 is combined with hydrogen to form a complex, the free hydrogen species diffuses into the substrate 1 quickly after the chemical bond is broken at high temperature, shortening the diffusion path of the hydrogen species, and it can be understood that more hydrogen species diffuses into the substrate per unit time to passivate acceptor impurities in the substrate and suppress the formation of P-type parasitic channels.
In addition, since the transition layer 22 on the nucleation layer 21 is of n-type or high-resistance type as shown in fig. 7, the diffusion coefficient of the hydrogen species in the substrate 1 containing silicon is much higher than that in the n-type or high-resistance nitride, and thus the hydrogen species diffuses toward the substrate 1 containing silicon to deactivate the acceptor impurities.
Based on the above description, in the formation of the semiconductor device, a P-type impurity containing at least one of group II is doped in the group IIIA nitride, and the P-type impurity is combined with a reaction gas hydrogen gas to form a complex to stabilize hydrogen in the complex, and then an annealing process is performed, in which chemical bonds in the complex are broken, hydrogen species are released in a free state, and the free hydrogen species may diffuse into the substrate 1 to passivate acceptor impurities that may form P-type parasitic channels, thereby suppressing the formation of the P-type parasitic channels.
Also, in some alternative embodiments, the hydrogen species may be implanted into the substrate 1 containing silicon by ion implantation, which may be performed by taking at least part of the group IIIA nitride forming layer 2 on the substrate 1 out of the reaction chamber after it is completed, and implanting the hydrogen species, which is liable to cause contamination and affect the performance of the semiconductor device.
In contrast, in the method for forming a semiconductor device according to the embodiment of the present application, the nucleation layer 21 is not required to be removed from the reaction chamber before the nucleation layer 21 is formed, but the formation of the nucleation layer 21 is completed in the reaction chamber all the time.
When a hydrogen species is implanted by ion implantation, ions are accelerated into an ion beam having a predetermined energy and then directed to the surface of a semiconductor substrate. The energetic ions in the ion beam are incorporated into the semiconductor material and are embedded into the crystal lattice of the semiconductor material, i.e., the ion implantation introduces a greater capability than the approach of the present application, potentially damaging the lattice arrangement.
In some alternative embodiments, mg may be selected to be doped as a P-type impurity in nucleation layer 21 because Mg is less ionized than other P-type impurities in the P-type impurity, is easily doped, and also easily combines with hydrogen species to form a complex.
In addition, since magnesium entering the nucleation layer 21 has a higher ionization energy than the group IIIA substance such as Al in the nucleation layer 21, holes generated by Mg ionization are much lower than the concentration of Mg doping actually, mg is an acceptor impurity, and N-type is present in the nucleation layer 21 due to the existence of dislocation, vacancy and impurity, so that the holes generated by Mg ionization compensate with electrons and thus a conductive path is not introduced into the nucleation layer 21.
When doping the group IIIA nitride forming layer with a P-type impurity containing at least one of group II, the concentration of the P-type impurity may be selected as: less than or equal to 1X 10 22 cm -3 。
Taking Mg as an example of doping impurity, high concentration is required in order to realize a P-type material with high hole concentrationA high degree of P-type impurity doping, such as Mg doping, is required. While Mg is limited in solubility in group IIIA nitride materials (e.g., gaN), high incorporation cannot be achieved. When the doping concentration reaches a certain degree, the impurity concentration of Mg is increased, and the Mg can be combined with the nitrogen of the reaction gas to form Mg 3 N 2 But not enter the GaN lattice, thereby affecting the crystal quality of the GaN material. And when the Mg doping concentration is large, mg atoms will be at interstitial sites between lattices (Mg at interstitial sites between lattices is called Mgi) instead of substitutional Ga atoms (Mg is substituted for Ga and MgGa substitutional atoms), mgi will be in combination with a large number of N vacancies (V) N ) A complex (Mgi-VN) is composed which exhibits donor properties, resulting in a self-compensating effect of the Mg atom.
Therefore, the concentration of the P-type impurity is required and cannot be too small, otherwise, the formation of the P-type parasitic channel cannot be suppressed, nor too large, because the quality of the group IIIA nitride formation layer is affected and even the performance of the semiconductor device is deteriorated.
In an alternative embodiment, when Mg is selected as the doping impurity, the concentration of magnesium may be selected as: 1X 10 18 cm -3 Up to 1X 10 21 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Alternatively, the concentration of magnesium may be selected as: 5X 10 18 cm -3 Up to 1X 10 21 cm -3 。
A method for manufacturing a semiconductor device including a specific layer structure forming method of the group IIIA nitride forming layer 2 is given below.
Fig. 11 is a process flow diagram of a method of forming the semiconductor device, and fig. 12 is a cross-sectional view of the semiconductor device after each step of the process flow for manufacturing the semiconductor device is completed.
As in step S01 in fig. 11, and (a) in fig. 12, fig. 12 (a) is a structural diagram after step S01 in fig. 11 is performed.
As in step S01 of fig. 11 and (a) of fig. 12, growth of Mg-doped nucleation layer 2 is performed on substrate 1 containing silicon.
The structure of the substrate 1 containing silicon is already explained above and will not be described here again.
In growing the Mg doped nucleation layer 21, the reaction gases include ammonia, hydrogen, and the reactants include trimethylaluminum (trimethyl aluminium), magnesium-bis-cyclopentadienyl, to name a few; the reaction temperature is around 1100 c and the thickness of the finally formed nucleation layer 21 is about 50nm to 500nm, which may be 300nm, for example.
In alternative embodiments, mg doping may be performed during the entire growth of the nucleation layer 21, for example, magnesium-half-oxide doping may be performed during the front-end growth of the nucleation layer 21, and Mg doping may be performed during the back-end growth without further doping, for example, magnesium-half-oxide doping may be performed before the nucleation layer 21 having a thickness of 100nm, and magnesium-half-oxide doping may not be performed during the formation of the nucleation layer having a thickness of 200 nm.
In some alternative embodiments, when doping Mg doping, the Mg doping may be chosen to be 5 x 10 19 cm -3 . Also, here 5X 10 19 cm -3 Is but one exemplary alternative concentration value.
The substrate 1 may also be subjected to an oxidation treatment prior to growing the nucleation layer 21 on the substrate 1, for example, the substrate 1 may be placed in a growth chamber and subjected to a high temperature surface cleaning with hydrofluoric acid to remove the oxide layer on the surface of the substrate 1. When the deoxidation treatment is carried out, the atmosphere can comprise hydrogen, the temperature is 1100 ℃, and the time is about 5 min.
The above reaction temperatures and reaction times are merely exemplary, and the substrate 1 may be chemically cleaned at other suitable reaction temperatures and reaction times.
During the growth of the nucleation layer 21, al gradually diffuses into the substrate 1, and when the substrate 1 is a high-resistance silicon substrate, al is substantially in the region of the substrate 1 near the nucleation layer 21, and Al acts as an acceptor impurity, forming a P-type parasitic channel in the substrate 1.
Also, mg doping in the nucleation layer 21 is combined with hydrogen in the reaction gas, and exists in the nucleation layer 21 in the form of a complex.
After step S01 in fig. 11 is completed, step S02 in fig. 11 is performed, and (b) in fig. 12 is a structural diagram after step S02 in fig. 11 is performed.
As in step S02 of fig. 11 and (b) of fig. 12, the growth of the transition layer 22 is performed.
In growing the transition layer 22, the reaction gases include ammonia, hydrogen, and the reactants include trimethylaluminum (trimethyl aluminium), trimethylgallium (trimethyl gallium), as examples; the reaction temperature is about 1100 ℃. The thickness of the final shaped transition layer 22 is about 100nm to 5000nm, which may be 1000nm, for example.
The transition layer 22 is a multi-layered AlxGa (1-x) N structure, and the multi-layered AlxGa (1-x) N structure may be referred to as a first-layered AlxGa (1-x) N structure, a second-layered AlxGa (1-x) N structure, a third-layered AlxGa (1-x) N structure, or the like, in a direction away from the substrate 1, for example, when having a three-layered structure, x is 0.8 in the first-layered AlxGa (1-x) N structure, x is 0.5 in the second-layered AlxGa (1-x) N structure, and x is 0.2 in the third-layered AlxGa (1-x) N structure. In the three-layer AlxGa (1-x) N structure, the thickness for each layer can be chosen as: the first layer of AlxGa (1-x) N structure has a thickness of 330nm, the second layer of AlxGa (1-x) N structure has a thickness of 330nm, and the third layer of AlxGa (1-x) N structure has a thickness of 340nm, however, these composition data and thickness data are only illustrative.
After step S02 in fig. 11 is completed, step S03 in fig. 11 is performed, and (c) in fig. 12 is a structural diagram after step S03 in fig. 11 is performed.
As in step S03 of fig. 11 and (c) of fig. 12, the channel layer 23 is grown.
In growing the channel layer 23, the reaction gas includes ammonia, hydrogen, and the reactant includes trimethylgallium (trimethyl gallium), for example; the reaction temperature was about 1050 ℃. The channel layer 23 is formed to have a thickness of substantially 100nm to 500nm.
After step S03 in fig. 11 is completed, step S04 in fig. 11 is performed, and (d) in fig. 12 is a structural diagram after step S04 in fig. 13 is performed.
As in step S04 of fig. 11 and (d) of fig. 12, growth of the insertion layer 24 is performed.
In growing the interposer 24, the reaction gas includes ammonia, hydrogen, and the reactant includes trimethylaluminum, for example; the reaction temperature was about 1050 ℃. The channel layer 23 is formed to have a thickness of substantially 0.2nm to 2nm, for example, may be 0.7nm.
After step S04 in fig. 11 is completed, step S05 in fig. 11 is performed, and (e) in fig. 12 is a structural diagram after step S05 in fig. 11 is performed.
As in step S05 of fig. 11 and (e) of fig. 12, the barrier layer 25 is grown.
In performing the growth of the barrier layer 25, the reaction gas includes ammonia, hydrogen, and the reactant includes trimethylaluminum, trimethylgallium. The reaction temperature was about 1050 ℃. The thickness of the barrier layer 25 formed is substantially 10nm to 60nm, for example, 30nm may be used.
The barrier layer 25 is formed in an AlxGa (1-x) N structure, where x may be about 0.2.
After step S05 in fig. 11 is completed, step S06 in fig. 11 is performed, and (f) in fig. 12 is a structural diagram after step S06 in fig. 11 is performed.
As in step S06 of fig. 11 and (f) of fig. 12, the growth of the cap layer 26 is performed.
In performing the cap layer 26 growth, the reactant gases include ammonia, hydrogen, and the reactants include trimethylgallium. The reaction temperature was about 1050 ℃. The cap layer 26 is formed to have a thickness of substantially 0.1nm to 10nm, for example, may be 1nm.
When any of the above-described structures of the transition layer 22, the channel layer 23, the insertion layer 24, the barrier layer 25, or the cap layer 26 is grown, the Mg impurity in the nucleation layer 21 is continuously bonded with hydrogen gas and the chemical bonds are broken, but the number of bonds is relatively larger than the number of breaks.
After step S06 in fig. 11 is completed, step S07 in fig. 11 is performed.
As shown in step S07 of fig. 11, an annealing treatment is performed.
After the growth of the above-mentioned transition layer 22, channel layer 23, insertion layer 24, barrier layer 25 and cap layer 26 is completed, the structure of the substrate 1 and epitaxial layer 2 containing silicon may be removed from the growth chamber, and an annealing treatment may be performed by using a tube furnace, where the annealing atmosphere includes nitrogen gas at a temperature of 600 ℃ to 900 ℃, such as about 800 ℃, and the annealing time is 1min to 180min, such as about 45 min. Of course, the annealing treatment may be performed in an annealing furnace in an atmosphere of a gas not containing hydrogen, for example, nitrogen, air, argon or a mixed gas thereof, at a reaction temperature of 600 ℃ to 1000 ℃ for a reaction time of 1min to 180min.
In the annealing process, since the annealing process is performed in an atmosphere not containing hydrogen, chemical bonds in a complex formed by Mg impurities in the nucleation layer 21 and hydrogen are broken, and the hydrogen species are present in a free form, so that the free hydrogen diffuses into the substrate 1, and the donor impurities are combined with acceptor impurities in the substrate 1, thereby breaking the P-type parasitic channel formed previously.
After step S07 in fig. 11 is completed, step S08 in fig. 11 and (g) in fig. 12 are performed.
As in step S08 of fig. 11 and (g) of fig. 12, a source electrode, a gate electrode, and a drain electrode are formed to form a semiconductor device.
The structure shown in fig. 13 is a structure diagram of a semiconductor device manufactured by the above method, and in the finally formed semiconductor device 021, not only at least one substance including a substance obtained by bonding an element in group IIIA to hydrogen in a region of the substrate 1 near the nucleation layer 21 is contained, as shown by a circle structure in the substrate 1 in fig. 13, but also at least one P-type impurity in group II is contained in the nucleation layer 21, as shown by a black circle in fig. 13, and of course, there is a possibility that a substance obtained by bonding an element in group II to hydrogen, such as complexation of magnesium to hydrogen, is present in the nucleation layer 21 because there is a possibility that the substance in group II bonded to hydrogen in the nucleation layer 21 is not completely broken in the annealing process described above, and further, the structure shown in fig. 13 is generated.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (20)

  1. A semiconductor device, comprising:
    a substrate comprising silicon;
    a nucleation layer disposed on the substrate;
    a channel layer disposed on the nucleation layer;
    a barrier layer disposed on the channel layer;
    wherein the nucleation layer comprises a P-type impurity, and the P-type impurity comprises an element in group II;
    the substrate contains a first substance, wherein the first substance comprises a substance obtained by combining an element in a IIIA group with hydrogen.
  2. The semiconductor device of claim 1, wherein the P-type impurity comprises an element from group IIA.
  3. The semiconductor device according to claim 1 or 2, wherein the concentration of the P-type impurity is: less than or equal to 1X 10 22 cm -3 。
  4. The semiconductor device of any of claims 1-3, wherein the P-type impurity comprises magnesium.
  5. The semiconductor device according to claim 4, characterized in thatThe concentration of magnesium is as follows: 1X 10 18 cm -3 Up to 1X 10 21 cm -3 。
  6. The semiconductor device according to any one of claims 1 to 5, wherein the nucleation layer contains a second substance including a substance obtained by combining an element in group II with hydrogen.
  7. The semiconductor device according to any one of claims 1 to 6, wherein the first substance is located in a region of the substrate near the nucleation layer.
  8. The semiconductor device of any of claims 1-7, wherein the nucleation layer comprises an aluminum nitride AlN material.
  9. The semiconductor device of any one of claims 1-8, wherein the channel layer comprises a gallium nitride GaN material.
  10. The semiconductor device of any one of claims 1-9, wherein the barrier layer comprises an aluminum gallium nitride AlGaN material.
  11. The semiconductor device according to any one of claims 1 to 10, further comprising:
    and a transition layer between the nucleation layer and the channel layer.
  12. A method of forming a semiconductor device, comprising:
    doping a P-type impurity in the group IIIA nitride, wherein the P-type impurity contains an element in group II, and forming a nucleation layer on a substrate containing silicon in the case that a reaction gas contains hydrogen, so that the P-type impurity is doped in the nucleation layer;
    and annealing the structure comprising the substrate and the nucleation layer to obtain the semiconductor device, wherein the substrate comprises a first substance, and the first substance comprises a substance obtained by combining elements in the IIIA group with hydrogen.
  13. The method of forming a semiconductor device of claim 12, wherein the P-type impurity comprises a group IIA element when the P-type impurity is doped in the group IIIA nitride.
  14. The method of forming a semiconductor device according to claim 12 or 13, wherein when doping the P-type impurity in the group IIIA nitride, the concentration of the doped P-type impurity is: less than or equal to 1X 10 22 cm -3 。
  15. The method of forming a semiconductor device according to any one of claims 12 to 14, characterized by comprising, when forming the nucleation layer on the substrate:
    a magnesium species is doped in the material used to form the nucleation layer to have P-type impurity magnesium in the nucleation layer that is capable of binding hydrogen.
  16. The method for forming a semiconductor device according to claim 15, wherein when the magnesium species is doped in a material for forming the nucleation layer, a concentration of the magnesium is: 1X 10 18 cm -3 Up to 1X 10 21 cm -3 。
  17. The method of forming a semiconductor device according to claim 15 or 16, wherein the magnesium impurity comprises magnesium dicyclopentadiene.
  18. The method of forming a semiconductor device according to any one of claims 12 to 17, characterized by, when the annealing treatment is performed on a structure including the substrate and the nucleation layer, comprising:
    The annealing treatment is performed in an atmosphere including nitrogen.
  19. The method of forming a semiconductor device according to any one of claims 12 to 18, wherein after forming the nucleation layer on the substrate, before performing the annealing treatment, the method further comprises:
    forming a channel layer on the nucleation layer;
    a barrier layer is formed on the channel layer.
  20. An electronic device, comprising:
    a circuit board;
    a semiconductor device according to any one of claims 1 to 11, or a semiconductor device manufactured by a method of forming a semiconductor device according to any one of claims 12 to 19; the circuit board is electrically connected with the semiconductor device.
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