CN117176832A - Exchange chip and control method - Google Patents
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- CN117176832A CN117176832A CN202311215257.4A CN202311215257A CN117176832A CN 117176832 A CN117176832 A CN 117176832A CN 202311215257 A CN202311215257 A CN 202311215257A CN 117176832 A CN117176832 A CN 117176832A
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Abstract
The embodiment of the application discloses an exchange chip and a control method, wherein the exchange chip comprises a serializer, a mapping circuit and a protocol controller group; the protocol controller group comprises at least two protocol controllers; the serializer is used for sending the mapping parameters to the mapping circuit; the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters, the target protocol controller is one of at least two protocol controllers, and the target protocol controller is determined based on the mapping parameters; the target protocol controller is for communicating with the serializer. The mapping relation between the serializer and the target protocol controller is determined through the mapping circuit, so that mapping between the serializer and the target protocol controller can be realized, namely, switching between the serializer and a plurality of protocol controllers can be realized through the mapping circuit based on different mapping parameters, and the chip cost is reduced.
Description
Technical Field
The application relates to the technical field of chips, in particular to an exchange chip and a control method.
Background
At present, the exchange chip can realize different functions through software definition and is applied to different scenes. Different functions may exist for different communication protocols, such as the packet switched interconnect protocol RapidIO protocol, the ethernet protocol, etc.
In the related art, mapping and communication between the serializer and the single protocol controller are generally implemented through a single protocol exchange chip, but when multiple different functions, that is, multiple communication protocols are required, multiple exchange chips are required, thereby increasing chip cost.
Disclosure of Invention
Based on the above problems, the present application provides an exchange chip and a control method, so as to reduce the chip cost.
The embodiment of the application discloses the following technical scheme:
in a first aspect, an embodiment of the present application provides an exchange chip, the chip including: a serializer, a mapping circuit and a protocol controller group; wherein, the first end and the second end of the mapping circuit are respectively connected with the mapping circuit and the protocol controller group; the protocol controller group comprises at least two protocol controllers;
the serializer is used for sending the mapping parameters to the mapping circuit;
the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is a protocol controller in the at least two protocol controllers; the target protocol controller is determined based on the mapping parameters;
the target protocol controller is configured to communicate with the serializer based on the mapping relationship.
Optionally, the mapping circuit includes a primary mapping circuit and a secondary mapping circuit; the first end and the second end of the primary mapping circuit are respectively connected with the serializer and the secondary mapping circuit; the first end and the second end of the second-level mapping circuit are respectively connected with the first-level mapping circuit and the protocol controller group; the mapping parameters comprise protocol configuration parameters and channel mode parameters;
the first-level mapping circuit is used for receiving the mapping parameters; and is configured to determine a target protocol controller from the protocol controller group according to a protocol configuration parameter in the mapping parameters;
the second-level mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters.
Optionally, the first-level mapping circuit is specifically configured to parse a protocol configuration parameter in the mapping parameters to obtain a first-level parsing result; and is configured to determine a target protocol controller based on the primary resolution result.
Optionally, the second-level mapping circuit is specifically configured to parse a channel mode parameter in the mapping parameters to obtain a second-level parsing result; and determining a mapping relationship between the data transmission channel of the serializer and the port of the target protocol controller based on the secondary analysis result.
Optionally, when the protocol controller group includes a fibre channel FC protocol controller, and the mapping parameter indicates a parameter with the FC protocol controller; the mapping circuit comprises a first-stage mapping circuit;
the first-level mapping circuit is used for analyzing the mapping parameters to obtain a first-level analysis result; and determining an interface of the FC protocol controller based on the primary analysis result.
Optionally, when the protocol controller group includes a PCIE protocol controller of a high-speed serial computer expansion bus standard, the mapping parameter indicates a parameter of the PCIE protocol controller; the mapping parameters comprise protocol configuration parameters and channel mode parameters; the mapping circuit comprises a first-level mapping circuit and a second-level mapping circuit;
the first-level mapping circuit is used for receiving the mapping parameters and analyzing protocol configuration parameters in the mapping parameters to obtain a first-level analysis result; and is used for determining a PCIE interface based on the primary parsing result; the PCIE interface is an interface of the PCIE controller;
the secondary mapping circuit is used for analyzing the channel configuration parameters in the mapping parameters to obtain a secondary mapping result; and determining a mapping relationship between the PCIE interface and a port of the PCIE controller based on the second-level mapping result.
In a second aspect, an embodiment of the present application provides an exchange chip, the chip including: n serializers, n mapping circuits, n protocol controller groups and n-1 high-speed serial computer expansion bus standard PCIE protocol controllers; n is an integer greater than or equal to 2; the protocol controller group comprises at least one protocol controller;
wherein, the n serializers and the n mapping circuits have corresponding relations; each serializer of the n serializers is connected with a corresponding mapping circuit; the n mapping circuits have corresponding relations with the n protocol controller groups; each mapping circuit in the n mapping circuits is connected with a corresponding protocol controller group; the n-1 PCIE protocol controllers are connected with two corresponding adjacent mapping circuits;
the serializer is used for sending the mapping parameters to the mapping circuit;
the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is a protocol controller in the at least two protocol controllers or the PCIE protocol controller; the target protocol controller is determined based on the mapping parameters;
the target protocol controller is configured to communicate with the serializer based on the mapping relationship.
In a third aspect, an embodiment of the present application provides a method for controlling an exchange chip, where the exchange chip includes a serializer, a mapping circuit and a protocol controller group; wherein, the first end and the second end of the mapping circuit are respectively connected with the mapping circuit and the protocol controller group; the protocol controller group comprises at least two protocol controllers;
the control method comprises the following steps:
receiving mapping parameters; the mapping parameters are obtained through the serializer;
determining a mapping relation between the serializer and the target protocol controller based on the mapping parameter; the target protocol controller is a protocol controller of the at least two protocol controllers.
In a fourth aspect, an embodiment of the present application provides a computer apparatus, including: the control method of the switch chip according to the third aspect is implemented when the processor executes the computer program.
In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which instructions are stored, which when executed on a terminal device, cause the terminal device to execute the control method of the switch chip according to the third aspect.
Compared with the prior art, the application has the following beneficial effects:
the exchange chip provided by the embodiment of the application comprises a serializer, a mapping circuit and a protocol controller group; the protocol controller group comprises at least two protocol controllers; the serializer is used for sending the mapping parameters to the mapping circuit; the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters, the target protocol controller is one of at least two protocol controllers, and the target protocol controller is determined based on the mapping parameters; the target protocol controller is for communicating with the serializer. The mapping relation between the serializer and the target protocol controller is determined through the mapping circuit, so that mapping between the serializer and the target protocol controller can be realized, namely, switching between the serializer and a plurality of protocol controllers can be realized through the mapping circuit based on different mapping parameters, and the chip cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an exchange chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another switch chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an exchange chip according to an embodiment of the present application;
fig. 4 is a schematic diagram of a mapping relationship based on an ethernet protocol according to an embodiment of the present application;
fig. 5 is a schematic diagram of a mapping relationship based on an SRIO protocol according to an embodiment of the present application;
fig. 6 is a schematic diagram of a mapping relationship based on PCIE protocol according to an embodiment of the present application;
fig. 7 is a flowchart of a control method of an exchange chip according to an embodiment of the present application.
Detailed Description
As described above, in research on the switch chip, it is found that, at present, the switch chip can implement different functions through software definition and is applied to different scenes. Different functions may exist for different communication protocols, such as the packet switched interconnect protocol RapidIO protocol, the ethernet protocol, etc.
In the related art, mapping and communication between the serializer and the single protocol controller are generally implemented through a single protocol exchange chip, but when multiple different functions, that is, multiple communication protocols are required, multiple exchange chips are required, thereby increasing chip cost.
In order to solve the above problems, an embodiment of the present application provides an exchange chip and a control method. The exchange chip comprises a serializer, a mapping circuit and a protocol controller group; the protocol controller group comprises at least two protocol controllers; the serializer is used for sending the mapping parameters to the mapping circuit; the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters, the target protocol controller is one of at least two protocol controllers, and the target protocol controller is determined based on the mapping parameters; the target protocol controller is for communicating with the serializer.
Therefore, the mapping relation between the serializer and the target protocol controller is determined through the mapping circuit, the mapping between the serializer and the target protocol controller can be realized, namely, the switching between the serializer and a plurality of protocol controllers can be realized through the mapping circuit based on different mapping parameters, and the chip cost is reduced.
In order to make the present application better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, the structure of an exchange chip according to an embodiment of the present application is shown.
Referring to fig. 1, an exchange chip 100 provided in an embodiment of the present application may include:
a serializer 101, a mapping circuit 102 and a protocol controller group 103; wherein, a first end and a second end of the mapping circuit 102 are respectively connected with the mapping circuit 102 and the protocol controller group 103; the protocol controller group 103 includes at least two protocol controllers.
The protocol controller group means a set comprising at least two protocol controllers, and the protocol controller group may include at least two of a fibre channel FC protocol controller, a high-speed serial computer expansion bus standard PCIE protocol controller, an ethernet protocol controller, and a serial communication protocol SRIO protocol controller, including but not limited to the foregoing four protocols, which are not specifically limited herein.
The FC protocol (fibre channel protocol) is a standard protocol cluster of fibre channel, and the FC protocol network has a high bandwidth, low latency, low dislocation rate, flexible topology.
PCI-Express (peripheral component interconnect express), PCIE for short, is a high-speed serial computer expansion bus standard, and is mainly used for expanding the data throughput of a computer system bus and improving the communication speed of equipment.
An ethernet protocol for implementing data transmission and address encapsulation (MAC) of the link layer.
The SRIO (Serial RapidIO) protocol is a protocol for high-speed serial communication, and is intended to connect chips such as Digital Signal Processors (DSPs), network processors, FPGAs, and the like, as well as interconnections therebetween. The SRIO protocol has the characteristics of low delay, high bandwidth (supporting the data transmission rate of 1.25Gbps to 25 Gbps), high reliability and the like.
The serializer 101 is configured to send mapping parameters to the mapping circuit 102.
A Serializer (Serializer/Deserializer, serDes) is a "physical device" that converts parallel data into serial data for transmission, and converts received serial data into parallel data.
The mapping parameter means a parameter including a protocol controller in communication with the serializer, and as one possible implementation, the mapping parameter may be obtained based on data to be transmitted, which is not particularly limited herein.
The mapping circuit 102 is configured to determine a mapping relationship between the serializer 101 and a target protocol controller based on the mapping parameter; the target protocol controller is a protocol controller in the at least two protocol controllers; the target protocol controller is determined based on the mapping parameters.
Mapping circuitry means circuitry for determining a target protocol controller in communication with the serializer and determining a mapping relationship between the serializer and the target protocol controller. The mapping relationship means a relationship between the data channels of the serializer and the ports of the target protocol controller, and as an example, assuming that the data channels of the serializer are a1 to a8 and the ports of the target protocol controller are b1 and b2, the mapping relationship between the data channels of the serializer and the ports of the target protocol controller is a1 to a4 corresponding to b1 and a5 to a8 corresponding to b2.
It should be understood that the mapping parameters include parameters related to the target protocol controller, and the mapping circuit determines the target protocol controller from at least two protocol controllers in the protocol controller group through the mapping parameters, and determines a mapping relationship between the serializer and the target protocol controller through the mapping parameters, so as to facilitate subsequent communication.
The target protocol controller is configured to communicate with the serializer 101 based on the mapping relationship.
It should be appreciated that when the mapping circuit determines the target protocol controller and the mapping relationship between the serializer and the target protocol controller, the target protocol controller may perform communication, data interaction, etc. with the serializer 101 based on the mapping relationship.
In the embodiment of the application, the mapping relation between the serializer and the target protocol controller is determined by the mapping circuit, so that the mapping between the serializer and the target protocol controller can be realized, namely, the switching between the serializer and a plurality of protocol controllers can be realized by the mapping circuit based on different mapping parameters, and the chip cost is reduced.
Based on the switch chip provided in the foregoing embodiment, to further illustrate the mapping circuit 102, in some possible implementation manners, the mapping circuit 102 may include: a primary mapping circuit and a secondary mapping circuit.
Wherein a first end and a second end of the primary mapping circuit are respectively connected with the serializer 101 and the secondary mapping circuit; the first end and the second end of the second-level mapping circuit are respectively connected with the first-level mapping circuit and the protocol controller group 103; the mapping parameters include protocol configuration parameters and channel mode parameters.
The protocol configuration parameter means a configuration parameter related to a protocol corresponding to a protocol controller in communication with the serializer; the channel mode parameter means a mode between a data channel of the serializer and a port of a corresponding protocol controller.
It should be understood that, in the embodiment of the present application, the target controller, and the mapping relationship between the serializer and the target controller need to be determined, so that the mapping relationship may be split into two mappings, where the first mapping may be used to determine the target controller from a plurality of protocol controllers, that is, determine, through a primary mapping circuit, the target protocol controller from the protocol controller group 103 according to the protocol configuration parameters; the second mapping determines the mapping relationship between the serializer and the protocol controller, that is, the mapping relationship between the serializer 101 and the target protocol controller is determined according to the channel mode parameter through the second mapping circuit.
In some possible implementations, the first-level mapping circuit is specifically configured to parse a protocol configuration parameter in the mapping parameters to obtain a first-level parsing result; and is configured to determine a target protocol controller based on the primary resolution result.
It should be appreciated that the target protocol controller may be determined based on the primary parsing result, while the target interface of the target protocol controller may be determined so that the serializer establishes a connection with the target interface of the target protocol controller.
Wherein, the interface means the connection part of the protocol controller and the serializer, and is a transfer station for exchanging information between the CPU of the protocol controller and the outside; a port means a register in the interface for exchanging data with other software.
It should be noted that, the protocol configuration parameters include parameters related to the protocol of the protocol controller to be communicated by the serializer, so that by analyzing the protocol configuration parameters, a first-level mapping result can be obtained, and the access switching between the serializer and the protocol controller in the protocol controller group is configured based on the mapping relationship, so as to determine the target protocol controller.
As an example, assuming that the protocol controller group includes three protocol controllers a, B, and C, it may be preset that none of the serializer and the protocol controllers a, B, and C establish a path, and the primary mapping result may include a=0, b=1, and c=0, the primary mapping result may indicate that the serializer and the protocol controller B establish a path, and then, based on the primary mapping result, the protocol controller B is determined to be the target protocol controller.
In some possible implementation manners, the second-level mapping circuit is specifically configured to parse a channel mode parameter in the mapping parameters to obtain a second-level parsing result; and is configured to determine a mapping relationship between the data transmission channel of the serializer 101 and the port of the target protocol controller based on the secondary parsing result.
It should be understood that the channel mode parameter includes a channel mode corresponding to the target protocol controller, since the serializer may include a plurality of data transmission channels and the protocol controller further includes a plurality of ports, in order to ensure normal communication between the serializer 101 and the target protocol controller, it is necessary to determine a mapping relationship between the data channels of the serializer 101 and the ports of the target protocol controller, that is, to determine a channel mode corresponding to the target controller through the channel mode parameter, and to determine a mapping relationship between the plurality of data channels of the serializer and the ports of the target protocol controller based on the channel mode.
Based on the exchange chip provided in the foregoing embodiment, because the functions or configurations of different protocol controllers are different, in a possible implementation manner, when the protocol controller group 103 includes a fibre channel FC protocol controller, the mapping parameter indicates a parameter with the FC protocol controller; the mapping circuit comprises a first-stage mapping circuit;
the first-level mapping circuit is used for analyzing the mapping parameters to obtain a first-level analysis result; and determining an interface of the FC protocol controller based on the primary analysis result.
It should be noted that, because the FC protocol controller does not have a mapping relationship between the serializer and the ports of the protocol controller, the serializer and the FC protocol controller can be connected and communicate only by determining that the target protocol controller is the FC protocol controller through the primary mapping circuit.
Based on the switch chip provided in the foregoing embodiment, in a possible implementation manner, when the protocol controller group 103 includes a PCIE protocol controller of a high-speed serial computer expansion bus standard, the mapping parameter indicates a parameter of the PCIE protocol controller; the mapping parameters comprise protocol configuration parameters and channel mode parameters; the mapping circuit comprises a first-level mapping circuit and a second-level mapping circuit;
the first-level mapping circuit is used for receiving the mapping parameters and analyzing protocol configuration parameters in the mapping parameters to obtain a first-level analysis result; and is used for determining a PCIE interface based on the primary parsing result; the PCIE interface is an interface of the PCIE controller.
The secondary mapping circuit is used for analyzing the channel configuration parameters in the mapping parameters to obtain a secondary mapping result; and determining a mapping relationship between the PCIE interface and a port of the PCIE controller based on the second-level mapping result.
It should be noted that, the data channels of the serializer are in one-to-one correspondence with the interfaces of the PCIE protocol controller, so that the PCIE interface of the PCIE protocol controller can be determined through the primary mapping circuit; meanwhile, the ports of the PCIE interface and the PCIE protocol controller are not in one-to-one correspondence, so that a mapping relationship between the PCIE interface and the ports of the PCIE protocol controller is determined through a two-stage mapping circuit, so that communication between the serializer and the PCIE protocol controller is realized.
Referring to fig. 2, a schematic diagram of another switching chip according to an embodiment of the present application is shown.
Because the PCIE protocol controller supports binding of 16 data channels, when the switch chip is designed, two serializers may be bound with one PCIE protocol controller, that is, two neighboring serializers share one PCIE protocol controller, but communication between two serializers and the PCIE protocol controller does not affect each other.
Referring to fig. 2, an exchange chip 200 provided in an embodiment of the present application may include: n serializers 101, n mapping circuits 102, n protocol controller groups 201 and n-1 high-speed serial computer expansion bus standard PCIE protocol controllers 202; n is an integer greater than or equal to 2; the protocol controller group 103 includes at least one protocol controller;
wherein, the n serializers 101 and the n mapping circuits 102 have a corresponding relationship; each serializer 101 of the n serializers 101 is connected with a corresponding mapping circuit 102; the n mapping circuits 102 have a corresponding relationship with the n protocol controller groups 201; each mapping circuit 102 of the n mapping circuits 102 is connected to a corresponding one of the protocol controller groups 201; the n-1 PCIE protocol controllers 202 are connected to two corresponding adjacent mapping circuits 102.
It should be noted that, in the switch chip 200 provided in the embodiment of the present application, the same modules or devices as those in the switch chip 100 provided in the embodiment described above are denoted by the reference numerals in the switch chip 100 provided in the embodiment described above.
It should be noted that, the protocol controller set 201 provided in the embodiment of the present application may be the same as or different from the protocol controller set 103 provided in the embodiment described above, and thus different reference numerals are used. As an example, assuming that the protocol controller included in the protocol controller group 201 is the same as the protocol controller included in the protocol controller group 103, the protocol controller group 201 is the same as the protocol controller group 103; otherwise, the values are different.
The serializer 101 is configured to send mapping parameters to the mapping circuit 102.
The mapping circuit 102 is configured to determine a mapping relationship between the serializer 101 and a target protocol controller based on the mapping parameter; the target protocol controller is a protocol controller of the at least two protocol controllers or the PCIE protocol controller 202; the target protocol controller is determined based on the mapping parameters.
The target protocol controller is configured to communicate with the serializer based on the mapping relationship.
In the embodiment of the application, in the design of the exchange chip, two adjacent serializers share one PCIE protocol controller, so that the chip cost can be reduced, and the utilization rate of the PCIE protocol controller can be improved.
Referring to fig. 3, a schematic diagram of an exchange chip according to an embodiment of the present application is shown.
Referring to fig. 3, the switch chip provided in the embodiment of the present application may include 6 groups, each group corresponds to one serializer, where each serializer may include 8 data channels, which are respectively lane0 to lane7; a first-level mapping circuit; an MPPG (Multi-protocol prot group, multi-protocol exchange physical Port group), wherein the MPPG comprises an Ethernet protocol controller and a corresponding two-level Ethernet mapping circuit, an FC protocol controller, an SRIO protocol controller and a corresponding two-level SRIO mapping circuit; every two groups correspond to two serializers and one PPG (PCIE port group), where the PPG includes a PCIE interface, a two-level PCIE mapping circuit, and a PCIE controller.
It should be noted that, in the embodiment of the present application, fig. 3 only shows the connection relationship between any two adjacent groups of the 6 groups, and other groups have the same or similar structure and connection relationship as those shown in fig. 3, and are not described herein.
It should be noted that, the mapping parameters include a protocol configuration parameter and a channel mode parameter, the protocol configuration parameter may be represented by BCFG [1:0], and the channel mode parameter may be represented by path_mode [3:0].
Referring to fig. 3, the first-stage mapping circuit is located at the first stage of the mapping circuit, and mainly realizes clock reset and data and control signal and status signal channel switching between the serializer and the four protocol controllers according to protocol configuration parameters, wherein the switching basis is BCFG [1:0].
In some possible implementations, the processing of the protocol configuration parameter BCFG [1:0] by the primary mapping circuit may include the following four cases:
in the first case, in the transmission direction of the serializer, when BCFG [1:0] = 00, the clock reset, data, control signal and status signal outputted from the serializer are connected to the interface of the ethernet protocol controller; otherwise, clock gating is performed, and the clock reset, data, control signals and status signals are connected with 0.
Among them, clock Gating (Clock Gating) is a technique that turns off the Clock when some parts of the digital IC design are not needed.
In the second case, in the transmission direction of the serializer, when BCFG [1:0] = 01, the clock reset, data, control signals and status signals output by the serializer are connected to the interface of the SRIO protocol controller; otherwise, clock gating is performed, and the clock reset, data, control signals and status signals are connected with 0.
In the third case, in the serializer transmission direction, when BCFG [1:0] = 10, the clock reset, data, control signal and status signal outputted from the serializer are connected to the interface of the FC protocol controller; otherwise, clock gating is performed, and the clock reset, data, control signals and status signals are connected with 0.
In the first case, in the direction of the serializer transmission, when BCFG [1:0] = 11, the clock reset, data, control signals and status signals output by the serializer are connected to the interface of the PCIE protocol controller, otherwise, the clock is gated, and the clock reset, data, control signals and status signals are connected to 0.
It should be appreciated that when clock reset, data, control signals and status signals are coupled to the interfaces of the target protocol controller according to protocol configuration parameters, clock gating is performed on the other protocol controllers, and the clock reset, data, control signals and status signals are coupled to 0 to effect switching and selection of the target protocol controller.
In the serializer transmission direction, when the clock signal is switched, the data selecting unit in the first-stage mapping circuit needs to be replaced by the gate control unit for control.
In some possible implementations, the mapping relationship between the data channel of the serializer and the port of the target protocol controller may include the following cases:
it should be noted that, the second-stage ethernet mapping circuit is located in the second-stage mapping of the mapping circuit, and mainly implements the clock reset, the data, the control and the path switching of the status signals between the ethernet interface of the first-stage mapping circuit and the port of the ethernet protocol controller according to the configuration of the channel mode parameter, where the switching basis is path_mode [3:0], see fig. 4, which is a schematic diagram of a mapping relationship based on the ethernet protocol according to the embodiment of the present application.
As shown in fig. 4, the data channel of the serializer may include 8 lanes, lane0 to Lane7; the ports of the ethernet protocol controller may include 9; the mapping relation based on the Ethernet protocol can contain twelve kinds, and when the path_mode [3:0] is different values, the mapping relation between the data channel of the serializer and the port of the Ethernet protocol controller is different. As an example, assuming that path_mode [3:0] =0000, the data lanes Lane0 to Lane4 of the serializer correspond to the port 2000GAUI-4PCS of the ethernet protocol controller, and the data lanes Lane5 to Lane7 of the serializer correspond to the port 1000GAUI-4PCS of the ethernet protocol controller.
The second-stage SRIO mapping circuit is located in the second-stage mapping of the mapping circuit, and is configured to implement clock reset, data, control and path switching of status signals between the SRIO interface of the first-stage mapping circuit and the port of the SRIO protocol controller according to the configuration of the channel mode parameter, where the switching basis is path_mode [3:0], see fig. 5, which is a schematic diagram of a mapping relationship based on the SRIO protocol according to an embodiment of the present application.
As shown in fig. 5, the data channel of the serializer may include 8 lanes, lane0 to Lane7; the ports of the SRIO protocol controller comprise two groups of SRIO_and SRIO_1, and each group comprises two ports; the mapping relationship based on the SRIO protocol may include four types. When path_mode [3:0] is different, different mapping relations between the data channel of the serializer and the port of the SRIO protocol controller are indicated. As an example, assuming path_mode [3:0] =0011, the data lanes Lane0 and Lane1 of the serializer correspond to port0 of the SRIO protocol controller; the data channels Lane2 and Lane3 of the serializer correspond to port12 of the SRIO protocol controller; the data channels Lane4 and Lane5 of the serializer correspond to port6 of the SRIO protocol controller; the serializer data channels Lane6 and Lane7 correspond to port18 of the SRIO protocol controller.
The second-stage PCIE mapping circuit is positioned at the second-stage mapping of the mapping circuit and is used for realizing the function of switching the paths of data and control signals between PCIE interfaces and ports of the PCIE protocol controller, the signals involved in switching are mostly control or status signals except data receiving and data sending, and the control flow and the data flow have no corresponding relation of time sequence handshake. The second-stage PCIE mapping circuit is positioned between ports of the PCIE interface and the PCIE protocol controller, and mainly realizes clock reset, data, control and path switching of state signals between the ports of the PIPE interface and the PCIE protocol controller according to configuration of channel mode parameters, wherein the switching basis is path_mode [3:0]. Referring to fig. 6, the diagram is a schematic diagram of a mapping relationship based on PCIE protocol according to an embodiment of the present application.
As shown in fig. 6, the data channels of the PCIE interface may include 16 data channels and may be divided into two groups, where each group includes data channels Lane0 to Lane7, and the two groups respectively correspond to two adjacent serializers; the ports of the PCIE protocol controller may include two groups, each group including 4 ports, the two groups corresponding to two serializers, respectively; the mapping relationship based on PCIE protocol may include 6 kinds. As an example, assuming that path_mode [3:0] =0000, the data lanes Lane0 to Lane7 corresponding to the two serializers each correspond to the port X16 PCIE Controller.
Based on the exchange chip provided in the foregoing embodiment, referring to fig. 7, the diagram is a flowchart of a control method of the exchange chip provided in the embodiment of the present application. As shown in fig. 7, the switching chip provided in the embodiment of the present application may include a serializer, a mapping circuit and a protocol controller group; wherein, the first end and the second end of the mapping circuit are respectively connected with the mapping circuit and the protocol controller group; the protocol controller group includes at least two protocol controllers.
The control method may include:
s701: receiving mapping parameters; the mapping parameters are obtained by the serializer.
S702: determining a mapping relation between the serializer and the target protocol controller based on the mapping parameter; the target protocol controller is a protocol controller of the at least two protocol controllers.
As one example, the mapping circuit includes a primary mapping circuit and a secondary mapping circuit; the first end and the second end of the primary mapping circuit are respectively connected with the serializer and the secondary mapping circuit; the first end and the second end of the second-level mapping circuit are respectively connected with the first-level mapping circuit and the protocol controller group; the mapping parameters comprise protocol configuration parameters and channel mode parameters;
the step S702 includes:
a1: and determining a target protocol controller from the protocol controller group according to the protocol configuration parameters in the mapping parameters.
A2: and determining the mapping relation between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters.
As an example, the A1 specifically includes:
analyzing the protocol configuration parameters in the mapping parameters to obtain a primary analysis result;
and determining a target protocol controller based on the primary analysis result.
As an example, the A2 specifically includes:
analyzing the channel mode parameters in the mapping parameters to obtain a secondary analysis result;
and determining the mapping relation between the data transmission channel of the serializer and the port of the target protocol controller based on the secondary analysis result.
As an example, when the protocol controller group includes a fibre channel FC protocol controller, and the mapping parameter indicates a parameter with the FC protocol controller; the mapping circuit comprises a first-stage mapping circuit;
the step S702 includes:
analyzing the mapping parameters to obtain a first-level analysis result; and determining an interface of the FC protocol controller based on the primary analysis result.
As an example, when the protocol controller group includes a high-speed serial computer expansion bus standard PCIE protocol controller, and the mapping parameter indicates a parameter with the PCIE protocol controller; the mapping parameters comprise protocol configuration parameters and channel mode parameters; the mapping circuit comprises a first-level mapping circuit and a second-level mapping circuit;
the step S702 includes:
analyzing the protocol configuration parameters in the mapping parameters to obtain a primary analysis result;
determining a PCIE interface based on the primary analysis result; the PCIE interface is an interface of the PCIE controller;
analyzing the channel configuration parameters in the mapping parameters to obtain a secondary mapping result;
and determining the mapping relation between the PCIE interface and the ports of the PCIE controller based on the secondary mapping result.
The control method of the exchange chip provided by the embodiment of the application has the same beneficial effects as the exchange chip provided by the embodiment, so that the description is omitted.
The embodiment of the application also provides corresponding equipment and a computer storage medium, which are used for realizing the scheme provided by the embodiment of the application.
The device comprises a memory and a processor, wherein the memory is used for storing instructions or codes, and the processor is used for executing the instructions or codes so that the device can execute the control method of the exchange chip according to any embodiment of the application.
The computer storage medium stores codes, and when the codes are executed, the equipment for executing the codes realizes the control method of the exchange chip according to any embodiment of the application.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. The above described device embodiments are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements illustrated as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of them can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The "first" and "second" in the names of "first", "second" (where present) and the like in the embodiments of the present application are used for name identification only, and do not represent the first and second in sequence.
From the above description of embodiments, it will be apparent to those skilled in the art that all or part of the steps of the above described example methods may be implemented in software plus general hardware platforms. Based on such understanding, the technical solution of the present application may be embodied in the form of a software product, which may be stored in a storage medium, such as a read-only memory (ROM)/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to perform the method according to the embodiments or some parts of the embodiments of the present application.
The foregoing is only one specific embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (10)
1. A switching chip, the chip comprising: a serializer, a mapping circuit and a protocol controller group; wherein, the first end and the second end of the mapping circuit are respectively connected with the mapping circuit and the protocol controller group; the protocol controller group comprises at least two protocol controllers;
the serializer is used for sending the mapping parameters to the mapping circuit;
the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is a protocol controller in the at least two protocol controllers; the target protocol controller is determined based on the mapping parameters;
the target protocol controller is configured to communicate with the serializer based on the mapping relationship.
2. The switching chip of claim 1, wherein the mapping circuit comprises a primary mapping circuit and a secondary mapping circuit; the first end and the second end of the primary mapping circuit are respectively connected with the serializer and the secondary mapping circuit; the first end and the second end of the second-level mapping circuit are respectively connected with the first-level mapping circuit and the protocol controller group; the mapping parameters comprise protocol configuration parameters and channel mode parameters;
the first-level mapping circuit is used for receiving the mapping parameters; and is configured to determine a target protocol controller from the protocol controller group according to a protocol configuration parameter in the mapping parameters;
the second-level mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters.
3. The switch chip of claim 2, wherein the primary mapping circuit is specifically configured to parse a protocol configuration parameter in the mapping parameters to obtain a primary parsing result; and is configured to determine a target protocol controller based on the primary resolution result.
4. The switch chip of claim 2, wherein the secondary mapping circuit is specifically configured to parse a channel mode parameter in the mapping parameters to obtain a secondary parsing result; and determining a mapping relationship between the data transmission channel of the serializer and the port of the target protocol controller based on the secondary analysis result.
5. The switch chip of claim 1, wherein when the protocol controller group includes a fibre channel FC protocol controller, and the mapping parameter indicates a parameter with the FC protocol controller; the mapping circuit comprises a first-stage mapping circuit;
the first-level mapping circuit is used for analyzing the mapping parameters to obtain a first-level analysis result; and determining an interface of the FC protocol controller based on the primary analysis result.
6. The switching chip of claim 1, wherein when the protocol controller group includes a high-speed serial computer expansion bus standard PCIE protocol controller, and the mapping parameter indicates a parameter with the PCIE protocol controller; the mapping parameters comprise protocol configuration parameters and channel mode parameters; the mapping circuit comprises a first-level mapping circuit and a second-level mapping circuit;
the first-level mapping circuit is used for receiving the mapping parameters and analyzing protocol configuration parameters in the mapping parameters to obtain a first-level analysis result; and is used for determining a PCIE interface based on the primary parsing result; the PCIE interface is an interface of the PCIE controller;
the secondary mapping circuit is used for analyzing the channel configuration parameters in the mapping parameters to obtain a secondary mapping result; and determining a mapping relationship between the PCIE interface and a port of the PCIE controller based on the second-level mapping result.
7. A switching chip, the chip comprising: n serializers, n mapping circuits, n protocol controller groups and n-1 high-speed serial computer expansion bus standard PCIE protocol controllers; n is an integer greater than or equal to 2; the protocol controller group comprises at least one protocol controller;
wherein, the n serializers and the n mapping circuits have corresponding relations; each serializer of the n serializers is connected with a corresponding mapping circuit; the n mapping circuits have corresponding relations with the n protocol controller groups; each mapping circuit in the n mapping circuits is connected with a corresponding protocol controller group; the n-1 PCIE protocol controllers are connected with two corresponding adjacent mapping circuits;
the serializer is used for sending the mapping parameters to the mapping circuit;
the mapping circuit is used for determining the mapping relation between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is a protocol controller in the at least two protocol controllers or the PCIE protocol controller; the target protocol controller is determined based on the mapping parameters;
the target protocol controller is configured to communicate with the serializer based on the mapping relationship.
8. The control method of the exchange chip is characterized in that the exchange chip comprises a serializer, a mapping circuit and a protocol controller group; wherein, the first end and the second end of the mapping circuit are respectively connected with the mapping circuit and the protocol controller group; the protocol controller group comprises at least two protocol controllers;
the control method comprises the following steps:
receiving mapping parameters; the mapping parameters are obtained through the serializer;
determining a mapping relation between the serializer and the target protocol controller based on the mapping parameter; the target protocol controller is a protocol controller of the at least two protocol controllers.
9. A computer device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, which when executed, implements the control method of the switch chip as claimed in claim 8.
10. A computer-readable storage medium, in which instructions are stored which, when run on a terminal device, cause the terminal device to perform the control method of the switching chip of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311215257.4A CN117176832A (en) | 2023-09-19 | 2023-09-19 | Exchange chip and control method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311215257.4A CN117176832A (en) | 2023-09-19 | 2023-09-19 | Exchange chip and control method |
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| CN117176832A true CN117176832A (en) | 2023-12-05 |
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| CN202311215257.4A Pending CN117176832A (en) | 2023-09-19 | 2023-09-19 | Exchange chip and control method |
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| CN (1) | CN117176832A (en) |
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