CN117176173A - Analog-to-digital converter and terminal equipment - Google Patents

Analog-to-digital converter and terminal equipment Download PDF

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CN117176173A
CN117176173A CN202311196938.0A CN202311196938A CN117176173A CN 117176173 A CN117176173 A CN 117176173A CN 202311196938 A CN202311196938 A CN 202311196938A CN 117176173 A CN117176173 A CN 117176173A
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dac
analog
signal
digital
digital converter
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吕达文
刘晔
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RDA Microelectronics Beijing Co Ltd
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RDA Microelectronics Beijing Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

An analog-to-digital converter and terminal equipment, the analog-to-digital converter includes: the device comprises a data weighted average control circuit, a digital-to-analog converter, a weight acquisition unit, a multiplier and an accumulator, wherein: the input end of the data weighted average control circuit inputs a decoding signal, and the output end of the data weighted average control circuit is coupled with the digital-to-analog converter and is suitable for outputting a control signal; the decoding signal is related to a target analog signal input to the analog-to-digital converter, and bit in the control signal corresponds to DAC units in the digital-to-analog converter DAC one by one; the weight acquisition unit is used for storing weights corresponding to the DAC units one by one; the multiplier is suitable for multiplying the control signal with the weight to obtain digital quantization output correction values corresponding to the DAC units one by one; and the accumulator is suitable for accumulating the digital quantization output correction values corresponding to all DAC units to obtain a target digital signal corresponding to the target analog signal. By adopting the scheme, the signal-to-noise ratio and the accuracy of the analog-to-digital converter can be improved.

Description

Analog-to-digital converter and terminal equipment
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an analog-to-digital converter and a terminal device.
Background
sigma delta analog to digital converter (SD-ADC), which is an ADC employing sigma delta debug techniques, uses oversampling techniques, and uses fewer bits to obtain higher (Signal Noise Ratio, SNR). The SD-ADC comprises a 1-bit SD-ADC and a multi-bit SD-ADC. Compared with a 1-bit SD-ADC, the multi-bit SD-ADC has lower quantization noise, better stability, lower power consumption and insensitivity to clock jitter (jitter), but has poorer linearity than the 1-bit SD-ADC. The reason for the poor linearity of multi-bit SD-ADCs is that there is a mismatch between the multiple digital-to-analog converter (DAC) units.
To improve the linearity of multi-bit SD-ADCs, dynamic element matching (Dynamic Element Matching, DEM) algorithms are commonly used in the prior art, by which mismatch between DAC cells can be eliminated for a long enough time. One commonly employed DEM algorithm is the data weighted average (Data Weight Average, DWA) algorithm, which employs a weighted average over a time period long enough that the probability of each DAC cell occurring is equal, thereby avoiding mismatch between DAC cells.
However, although the DWA algorithm can improve the linearity of the multi-bit SD-ADC, the SNR and accuracy of the multi-bit SD-ADC are reduced.
Disclosure of Invention
It is an object of the present invention to provide a multi-bit SD-ADC having a high SNR and accuracy.
The invention provides an analog-to-digital converter comprising: the device comprises a data weighted average control circuit, a digital-to-analog converter, a weight acquisition unit, a multiplier and an accumulator, wherein: the input end of the data weighted average control circuit is input with a decoding signal, and the output end of the data weighted average control circuit is coupled with the digital-to-analog converter and is suitable for outputting a control signal; the decoding signal is related to a target analog signal input to the analog-to-digital converter, and bits in the control signal are in one-to-one correspondence with DAC units in the digital-to-analog converter DAC; the weight acquisition unit is used for storing weights corresponding to the DAC units one by one; the multiplier is suitable for multiplying the control signal with the weight to obtain digital quantization output correction values corresponding to the DAC units one by one; and the accumulator is suitable for accumulating the digital quantization output correction values corresponding to all DAC units to obtain the target digital signal corresponding to the target analog signal.
And weighting and summing the control signals output by the DWA control circuit by presetting weights corresponding to all DAC units in the DAC to obtain a target digital signal. The weight corresponding to each DAC unit in the DAC can be obtained through a pre-test, and can be matched with the analog-to-digital converter, so that mismatch among the DAC units is avoided as much as possible, and the signal-to-noise ratio and the accuracy of the analog-to-digital converter can be improved.
Optionally, the average value of the weights corresponding to the DAC units one to one is 1, and the weights corresponding to part of the DAC units are not equal.
Optionally, the weights corresponding to the DAC units one by one are determined in the following manner: obtaining a weighting equation corresponding to an ith DAC unit, wherein the ith weighting equation is as follows:based on 2 N -1 weighting equation for DAC cell, determining the weight x for the ith DAC cell i The method comprises the steps of carrying out a first treatment on the surface of the Wherein N is x For the number of times the ith DAC unit is selected by the DWA control circuit in Ns sampling periods, N i The number of times selected by the DWA control circuit for other DAC cells in Ns sampling periods; i is more than or equal to 1 and less than or equal to 2 N -1; n is the number of bits of the analog-to-digital converter.
The weight acquisition unit acquires 2 when acquiring weights corresponding to different DAC units N -1 weighting equation for DAC cell. When the weighting equation corresponding to the ith DAC unit is acquired, the number of times of selecting the ith DAC unit and the number of times of selecting other DAC units are not equal in Ns sampling periods through the DWA control circuit, so that the weight corresponding to each DAC unit can be accurately acquired.
Alternatively, N x Equal to Ns; alternatively, N x Is different from Ns, and N x And N i And not equal.
Optionally, the analog-to-digital converter further includes: the adder is suitable for carrying out subtraction operation on the target analog signal and the feedback signal and outputting an obtained difference signal; the feedback signal is an output signal of the DAC, and the output signal of the DAC is a sum value of output signals of all DAC units; the output signal of the DAC unit is obtained based on the control signal.
Optionally, the analog-to-digital converter further includes: and the filter is suitable for filtering the difference signal and filtering high-frequency components in the difference signal.
Optionally, the analog-to-digital converter further includes: the quantizer is suitable for performing quantization operation on the difference signal subjected to filtering processing to obtain a quantized signal with the length of N bits; the number of bits of the quantizer is N.
Optionally, the analog-to-digital converter further includes: a decoder adapted to decode the quantized signal into the decoded signal; the bit length of the decoding signal is 2 N -1。
Optionally, the analog-to-digital converter comprises a sigma delta analog-to-digital converter.
The invention also provides a terminal device comprising any one of the analog-to-digital converters.
Drawings
FIG. 1 is a schematic diagram of a prior art sigma delta analog to digital converter;
FIG. 2 is a diagram of a prior art application scenario for a classical DWA algorithm;
FIG. 3 is a schematic diagram of a prior art DWA algorithm with DAC cells selected at different sampling periods;
FIG. 4 is a schematic diagram of an analog-to-digital converter according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of selected DAC units within Ns sampling periods in an embodiment of the invention;
fig. 6 is a schematic diagram of a DAC cell selected during another Ns sampling periods in an embodiment of the invention.
Detailed Description
Referring to fig. 1, a schematic diagram of a sigma delta analog-to-digital converter (SD-ADC) is shown. In fig. 1, the SD-ADC includes an adder 101, a low-pass loop filter 102, a Nbit quantizer 103, a decoder 104, a data weighted average (Data Weight Average, DWA) control circuit 105, a digital-to-analog converter (DAC) 106, and the like.
The input terminal of the SD-ADC inputs an analog signal Vin, the analog signal Vin is input to a first input terminal ("+" terminal) of the adder 101, and an analog signal Vfb fed back by the digital-to-analog converter is input to a second input terminal ("-" terminal) of the adder 101. The difference signal Vdff between Vin and Vfb is obtained by subtracting the adder 101. The Vdff signal is passed through a low pass loop filter 102 to filter out the high frequency signal, resulting in a Vfltr signal that includes only the low frequency component. After the Vfltr signal is quantized by the Nbit quantizer 103, a digital signal Dout [ N-1:0] of Nbit is obtained.
The Nbit quantizer 103 is essentially a low-precision ADC. Taking n=4 as an example, the 4bit quantizer 103 can provide a signal-to-noise ratio (Signal Noise Ratio, SNR) of 25 dB. In the whole loop, an SNR of more than 100dB can be obtained within a certain bandwidth.
To improve linearity, an average weighted DAC cell (cell) is used. DAC106 may include 2 N -1 DAC cell. For example, n=4, and the number of DAC cells is 15. The length of the decoder 104 is 2 N -1, output length 2 N -1-bit thermometer coding, corresponding to 2 N -1 DAC cell. Will 2 N The outputs of the 1 DAC cells are summed to obtain the feedback voltage signal Vfb.
In some SD-ADCs, decoder 104 outputs 2 N -1bit can directly control 2 N -1 DAC cell. However, since the occurrence probability of each DAC cell is different, there is a mismatch (mismatch) between DAC cells, resulting in a significant deterioration of the total harmonic distortion (total Harmonic Distortion, THD) performance of the SD-ADC.
To further improve linearity and reduce harmonics, in other SD-ADCs, a DWA control circuit 105 is provided, the DWA control circuit 105 controlling the selection of DAC cells in a barrel shift (barrelshift) manner. As shown in fig. 2, an application scenario diagram of a conventional DWA algorithm is given.
In fig. 2, taking a 4bit quantizer as an example, the DAC includes 15 DAC units, the 15 DAC units are connected end to form a barrel shape, and according to the difference of output data of the 4bit quantizer, several corresponding DAC units are selected for each sampling period T. The output sequence of the 4bit quantizer is 4, 5, 4 from the first sample period T to the 5 th sample period 5T in a clockwise direction.
Referring to fig. 3, a schematic diagram of a DAC cell selected at different sampling periods for a DWA algorithm is shown. In fig. 3, 15 DAC cells are represented laterally and different sampling periods are represented longitudinally. In the 1 st sampling period, selecting DAC units 1-4; in the 2 nd sampling period, selecting DAC units 5-8; in the 3 rd sampling period, selecting DAC units 9-13; in the 4 th sampling period, DAC units 14 to 15 and DAC units 1 to 2 are selected.
In fig. 3, 28 sampling periods are recorded, and the number of occurrences of each DAC cell (i.e., the number selected) is 8, i.e., the probability of occurrence of each DAC cell is equal. Although the value of the output data Dout [3:0] is different in each quantization period, each DAC cell is traversed for a sufficiently long period of time and the probability of occurrence of each DAC cell is equal. Thus, mismatch between DAC cells is eliminated by the DWA algorithm and no significant harmonics occur.
However, although the use of the DWA algorithm reduces harmonics, the components of the harmonics are dispersed as background noise. That is, existing DWA algorithms raise the background noise while reducing harmonics. The SNR of SD-ADC decreases due to the increase in the noise floor, resulting in poor accuracy.
In the embodiment of the invention, the control signals output by the DWA control circuit are weighted and summed to obtain the target digital signal by presetting weights corresponding to each DAC unit in the DAC. The weight corresponding to each DAC unit in the DAC can be obtained through a pre-test, and can be matched with the analog-to-digital converter, so that mismatch among the DAC units is avoided as much as possible, and the signal-to-noise ratio and the accuracy of the analog-to-digital converter can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
An embodiment of the present invention provides an analog-to-digital converter, referring to fig. 4.
In an embodiment of the present invention, the analog-to-digital converter may include a DWA control circuit 405, a DAC406, a weight acquisition unit 407, a multiplier 408, and an accumulator 409.
In an implementation, an input of the DWA control circuit 405 may input a decoding signal, and an output of the DWA control circuit 405 may be coupled to a digital-to-analog converter and adapted to output a control signal; the decode signal may be associated with a target analog signal input to the analog-to-digital converter, the number of bits in the control signal may be equal to the number of DAC cells in DAC406, and the bits in the control signal are in one-to-one correspondence with the DAC cells.
In an implementation, the weight acquisition unit 407 may store weights corresponding to the DAC units one by one. The number of weights stored in the weight acquisition unit 407 may be equal to the number of DAC units, and there is a one-to-one correspondence of each DAC unit.
For example, the number of DAC units is 7, and DAC units 1 to 7 are sequentially arranged. The weight acquisition unit 407 stores 7 weights, and sequentially weights 1 to 7. The weight corresponding to DAC unit 1 is weight 1, the weight corresponding to DAC unit 2 is weight 2, and so on, the weight corresponding to DAC unit 7 is weight 7. The control signal includes 7 bits, the first bit is input to the DAC unit 1, the second bit is input to the DAC unit 2, and so on, the 7 th bit is input to the DAC unit 7.
That is, the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all equal, and equal to 2 N -1, n is the number of bits of the analog-to-digital converter.
For example, the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all 7, with the number of bits n=3 of the analog converter.
For another example, the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all 15 if the number of bits in the analog converter is n=4.
In particular implementations, multiplier 408 may multiply the control signal with weights to obtain digital quantized output correction values that are in one-to-one correspondence with the DAC units.
In particular, the bit value corresponding to the first DAC unit (i.eThe value of the first bit in the control signal) is multiplied by the weight corresponding to the first DAC unit to obtain a digital quantization output correction value corresponding to the first DAC unit; multiplying the bit value corresponding to the second DAC unit (namely the value of the second bit in the control signal) by the weight corresponding to the second DAC unit to obtain a digital quantization output correction value corresponding to the second DAC unit; and so on, can obtain the 2 nd N -1 digital quantized output correction value for DAC cell.
2 N The digital quantized output correction values corresponding to 1 DAC units are input to the accumulator 409, and the accumulator 409 outputs 2 N And summing the digital quantization output correction values corresponding to the 1 DAC units to obtain a target digital signal corresponding to the target analog signal.
In a specific implementation, the analog-to-digital converter may further include an adder 401, where a first input end of the adder 401 may input a target analog signal, a second input end of the adder 401 may input a feedback signal, and the adder 401 performs subtraction operation on the target analog signal and the feedback signal to obtain a difference signal. The output of adder 401 outputs a difference signal.
In implementations, the analog-to-digital converter may also include a loop filter 402. An input of the loop filter 402 is coupled to an output of the adder 401, and an output of the loop filter 402 outputs the filtered difference signal. By providing the loop filter 402, high frequency components in the difference signal are filtered out.
It is understood that the high frequency component in the difference signal may refer to a frequency component having a frequency higher than a preset frequency threshold. The specific frequency threshold may be set according to different application scenarios.
In some embodiments, loop filter 402 may be a low pass loop filter 402.
In a specific implementation, the analog-to-digital converter may further comprise a Nbit quantizer 403. An input of the Nbit quantizer 403 is coupled to an output of the filter 402, and an output of the Nbit quantizer 403 outputs a quantized signal of length N bits.
In implementations, the analog-to-digital converter may also include a decoder 404. TranslationAn input of the encoder 404 is coupled to an output of the Nbit quantizer 403 and an output of the decoder 404 is coupled to an input of the DWA. Decoding the quantized signal of Nbit by decoder 404 to obtain a length 2 N -a 1-bit decoded signal.
In the embodiment of the present invention, the analog-to-digital converter may be an SD-ADC.
The following describes the operation flow of the SD-ADC provided in the above embodiment of the present invention.
In a specific implementation, the input terminal of the SD-ADC inputs the target analog signal Vin, the target analog signal Vin is input to the first input terminal ("+" terminal) of the adder, and the feedback signal Vfb output by the digital-to-analog converter (DAC) is input to the second input terminal ("-" terminal) of the adder. The difference signal Vdff between Vin and Vfb is obtained by the subtraction of the adder. The difference signal Vdff is passed through a low-pass loop filter to filter out the high frequency component, resulting in a Vfltr signal comprising only the low frequency component. After being quantized by an Nbit quantizer, the Vfltr signal obtains a digital signal Dout [ N-1:0] of Nbit]. The Nbit digital signal is input into a decoder to obtain 2 N -1bit thermometer code and input to DWA control circuit.
Taking n=4 as an example, the Vfltr signal is quantized by a 4-bit quantizer to obtain a 4-bit digital signal. The 4bit data signal passes through the decoder to obtain the 15bit thermometer code, and outputs to the DWA control circuit.
The DWA control circuit controls the selection of DAC cells in a barrel shift (barrelshift) manner. An output of the DWA control circuit is coupled to an input of the DAC. DAC comprises 2 N -1 DAC cell, DAC pair 2 N The outputs of the 1 DAC cells are accumulated to obtain the feedback signal Vfb.
The output of the DWA control circuit is also coupled to a first input of the multiplier, the output of the weight acquisition unit is coupled to a second input of the multiplier, and the output of the multiplier is coupled to the input of the accumulator. The output end of the accumulator outputs Dout [ M:0], and Dout [ M:0] is the target digital signal corresponding to the target analog signal Vin.
In particular implementations, the value of M in Dout [ M:0] may be determined according to particular application requirements. The larger the value of M is, the higher the precision of the obtained SD-ADC is, and the larger the demand on the computing resource is correspondingly. And if the value of M is smaller, the obtained SD-ADC has poorer precision, and correspondingly, the requirement on calculation resources is smaller. Therefore, the precision of the SD-ADC and the demand of the computing resource can be balanced, and the value of M can be determined.
In the embodiment of the present invention, the weight acquiring unit may store weights corresponding to the DAC units in advance. The weights corresponding to the DAC cells may be calculated in advance. When the SD-ADC works, the weights corresponding to all DAC units can be directly obtained from the weight obtaining unit, and the weights corresponding to all DAC units are output to the second input end of the multiplier.
In some embodiments, m=23 is taken. Thus, a 24-bit digital signal corresponding to the input analog signal Vin can be obtained.
Taking a 4bit quantizer as an example, the DAC comprises 15 DAC cells. The weights corresponding to the 15 DAC units are estimated in advance. The weights of the 15 DAC units are multiplied by the data output by the DWA control circuit, and then 15 products are accumulated through an accumulator, so that Dout [23:0] can be obtained.
A specific procedure of the weight acquisition unit 407 acquiring the weight corresponding to each DAC unit will be described below.
For 2 N -1 DAC cell, assuming a sampling period number Ns:
step 1, selecting a first DAC unit, and setting the occurrence frequency of the first DAC unit in Ns sampling periods as Nx; for other 2 N -2 DAC cells traversed according to the classical DWA algorithm described above, the frequency of occurrence being N over Ns sampling periods 1 ；
Step 2, selecting a second DAC unit, and setting the occurrence frequency of the second DAC unit in Ns sampling periods as Nx; for other 2 N -2 DAC cells traversed according to the classical DWA algorithm described above, the frequency of occurrence being N over Ns sampling periods 2 ；
Step 3, selecting a third DAC unit, and setting the occurrence frequency of the third DAC unit in Ns sampling periods as Nx; for other 2 N -2 DAC cells according to the aboveThe classical DWA algorithm traverses with the frequency of occurrence N in the Ns sampling periods 3 ；
And so on;
step 2 N -1, select 2 N -1 DAC cell, setting the frequency of its occurrence in Ns sampling periods to Nx; for other 2 N -2 DAC cells traversed according to the classical DWA algorithm described above, the frequency of occurrence over Ns sampling periods being
Thus, a set of values can be obtained as:
setting 2 N The weights of the-1 DAC units are respectively2 N The average value of the weights of the 1 DAC cell is 1. Since vfb=vin, 2 is as above N The sum of the products of the data obtained in step 1 and their weights is equal. Based on this, the following set of equations can be obtained:
the method comprises the steps of,
through the two equation sets, the method can be calculated asThe method sequentially comprises the following steps:
x 1 ＝(Y-(2 N -1)*N 1 )/(Nx-N 1 )；
x 2 ＝(Y-(2 N -1)*N 2 )/(Nx-N 2 )；
x 3 ＝(Y-(2 N -1)*N 3 )/(Nx-N 3 )；
……；
wherein,
thus, 2 is calculated N -1 weight for DAC cell.
In some embodiments, nx may be equal to Ns. In other embodiments, the value of Nx may be different from Ns, and Nx may be equal toAre not equal.
The calculation process of the weight of each DAC unit described above is exemplified below by taking n=4 as an example.
When n=4, the DAC includes 2 DAC units N -1=15, DAC cell 1 to DAC cell 15 in this order. Let nx=ns, the sampling period number be Ns.
Step 1, selecting a first DAC unit (DAC unit 1), setting the frequency of the DAC unit in Ns sampling periods as Ns (namely, in Ns sampling periods, the first DAC unit appears in each sampling period); for the other 14 DAC units (DAC unit 2-DAC unit 15), the traversal is performed according to the classical DWA algorithm, and the frequency of occurrence in the Ns sampling periods is N 1 ；
Referring to fig. 5, a schematic diagram of the DAC cell selected in step 1 over Ns sampling periods is given. In step 1, DAC unit 1 is selected within Ns sampling periods, DAC units 2 to 15 are traversed according to classical DWA algorithm, and the frequencies appearing within Ns sampling periods are all N 1 。
Step 2, selecting a second DAC unit (DAC unit 2), and setting the frequency of the DAC unit in Ns sampling periods as Ns;for the other 14 DAC units (DAC unit 1, DAC unit 3-DAC unit 15), the traversal is performed according to the classical DWA algorithm, and the frequency of occurrence in the Ns sampling periods is N 2 。
Referring to fig. 6, a schematic diagram of the DAC cell selected in step 2 over Ns sampling periods is given. In step 2, DAC unit 2 is selected within Ns sampling periods, DAC unit 1, DAC unit 3-DAC unit 15 traverse according to classical DWA algorithm, and the frequencies appearing within Ns sampling periods are all N 2 。
Step 3, selecting a third DAC unit (DAC unit 3), and setting the frequency of the DAC unit in the Ns sampling periods as Ns; for the other 14 DAC units (DAC unit 1-DAC unit 2, DAC unit 4-DAC unit 15), the traversal is performed according to the classical DWA algorithm, and the frequency of occurrence in the Ns sampling periods is N 3 ；
……；
Step 15, selecting the 15 th DAC unit (DAC unit 15), setting the frequency of the DAC unit in the Ns sampling periods as Ns; for the other 14 DAC units (DAC unit 1-DAC unit 14), the traversal is performed according to the classical DWA algorithm, and the frequency of occurrence in the Ns sampling periods is N 15 。
Weights of 15 DAC units are set as x respectively 1 、x 2 、……、x 15 The average value of the weights of the 15 DAC cells is 1. The following set of equations is obtained:
and
through the two equation sets, the method can be calculated asThe method sequentially comprises the following steps:
x 1 ＝(Y-15*N 1 )/(Ns-N 1 )；
x 2 ＝(Y-15*N 2 )/(Ns-N 2 )；
x 3 ＝(Y-15*N 3 0/(Ns-N 3 )；
……；
x 15 ＝(Y-15*N 15 )/(Ns-N 15 )；
wherein,
in a specific implementation, the weight obtaining unit 407 may be configured to store only the weights corresponding to the DAC units. Specifically, the calculation of the weights of the DAC cells may be performed by an external data processing apparatus. For example, the external data processing apparatus calculates the weight of each DAC unit, and sends it to the weight acquisition unit 407 for storage.
In summary, in the embodiment of the present invention, the control signals output by the DWA control circuit are weighted and summed to obtain the target digital signal by presetting weights corresponding to the DAC units in the DAC. The weight corresponding to each DAC unit in the DAC can be obtained through a pre-test, and can be matched with the analog-to-digital converter, so that mismatch among the DAC units is avoided as much as possible, and the signal-to-noise ratio and the accuracy of the analog-to-digital converter can be improved.
The analog-to-digital converter provided by the embodiment of the invention does not change the analog circuit part and does not increase the cost and complexity of the analog circuit part.
The embodiment of the invention also provides a terminal device comprising the analog-to-digital converter provided by any embodiment.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs related hardware, the program may be stored on a computer readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, etc.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. An analog-to-digital converter, comprising: the device comprises a data weighted average control circuit, a digital-to-analog converter, a weight acquisition unit, a multiplier and an accumulator, wherein:
the input end of the data weighted average control circuit is input with a decoding signal, and the output end of the data weighted average control circuit is coupled with the digital-to-analog converter and is suitable for outputting a control signal; the decoding signal is related to a target analog signal input to the analog-to-digital converter, and bits in the control signal are in one-to-one correspondence with DAC units in the digital-to-analog converter DAC;
the weight acquisition unit is used for storing weights corresponding to the DAC units one by one;
the multiplier is suitable for multiplying the control signal with the weight to obtain digital quantization output correction values corresponding to the DAC units one by one;
and the accumulator is suitable for accumulating the digital quantization output correction values corresponding to all DAC units to obtain the target digital signal corresponding to the target analog signal.
2. The analog-to-digital converter of claim 1, wherein the average of the weights corresponding to the DAC cells one-to-one is 1, and the weights corresponding to the DAC cells are not equal.
3. The analog-to-digital converter of claim 2, wherein the weights corresponding one-to-one to the DAC cells are determined by:
obtaining a weighting equation corresponding to an ith DAC unit, wherein the ith weighting equation is as follows:
based on 2 N -1 weighting equation for DAC cell, determining the weight x for the ith DAC cell i The method comprises the steps of carrying out a first treatment on the surface of the Wherein N is x For the number of times the ith DAC unit is selected by the DWA control circuit in Ns sampling periods, N i For it isThe number of times his DAC cell is selected by the DWA control circuit in Ns sampling periods; i is more than or equal to 1 and less than or equal to 2 N -1; n is the number of bits of the analog-to-digital converter.
4. An analog to digital converter as claimed in claim 3, in which N x Equal to Ns; alternatively, N x Is different from Ns, and N x And N i And not equal.
5. An analog to digital converter as claimed in any of claims 1 to 4, further comprising: the adder is suitable for carrying out subtraction operation on the target analog signal and the feedback signal and outputting an obtained difference signal; the feedback signal is an output signal of the DAC, and the output signal of the DAC is a sum value of output signals of all DAC units; the output signal of the DAC unit is obtained based on the control signal.
6. The analog-to-digital converter of claim 5, further comprising: and the filter is suitable for filtering the difference signal and filtering high-frequency components in the difference signal.
7. The analog-to-digital converter of claim 6, further comprising: the quantizer is suitable for performing quantization operation on the difference signal subjected to filtering processing to obtain a quantized signal with the length of N bits; the number of bits of the quantizer is N.
8. The analog-to-digital converter of claim 7, further comprising: a decoder adapted to decode the quantized signal into the decoded signal; the bit length of the decoding signal is 2 N -1。
9. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises a sigma delta analog-to-digital converter.
10. A terminal device comprising an analog-to-digital converter as claimed in any one of claims 1 to 9.
CN202311196938.0A 2023-09-15 2023-09-15 Analog-to-digital converter and terminal equipment Pending CN117176173A (en)

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