CN117176147A - Delay phase-locked circuit and storage device - Google Patents
Delay phase-locked circuit and storage device Download PDFInfo
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Abstract
The application discloses a delay phase-locked circuit and a storage device, wherein the delay phase-locked circuit comprises: the input end of the delay circuit inputs a first clock signal; the input end of the delay adjusting circuit is coupled with the input end of the delay circuit, and the output end of the delay adjusting circuit is coupled with the delay circuit; the delay adjusting circuit generates a corresponding first voltage signal based on the frequency of the first clock signal, compares the first voltage signal with a preset reference voltage signal to obtain a corresponding comparison result signal, controls the delay circuit based on the comparison result signal so that the delay circuit carries out corresponding delay processing on the first clock signal, and outputs a second clock signal which is synchronous with the phase of the first clock signal through an output end of the delay circuit. By the mode, the delay performance of the delay phase-locked circuit for the clock signal in the specific frequency range can be improved, and the working frequency range of the delay phase-locked circuit is widened.
Description
Technical Field
The present application relates to the field of circuit technologies, and in particular, to a delay locked loop circuit and a storage device.
Background
A delay locked loop (Delay locked loop, DLL) is a clock circuit whose main function is to synchronize (edge align) the phase of an output clock signal with the phase of an input reference clock signal by comparing the phase difference of the input reference clock signal and the output clock signal, to synchronize (edge align) the phases of the two by feeding back the delay to delay the output clock by an integer number of cycles of the input reference clock signal, and to lock the edges when they are aligned.
In one application scenario, when a memory device, such as a synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), is in a read mode, in order to ensure that a memory controller (memory controller) can correctly receive data, the data sent by the memory device must have a certain delay with a clock sent by the memory controller, and typically this certain delay needs to ensure that the time from entering the memory device to triggering the data output by the memory controller is an integer number of tcks (reference clock cycles). In a memory device (e.g., SDRAM), the above-described function is implemented by a DLL provided in a DDR (Double Data Rate) circuit, but the DLL does not implement phase synchronization of a clock transmitted by a memory controller and a clock transmitted by the memory device by an integer number of tcks in all frequency ranges.
Disclosure of Invention
The application mainly solves the technical problem of providing a delay phase-locked circuit and a storage device, which can improve the delay performance of the delay phase-locked circuit on clock signals in a specific frequency range and widen the working frequency range of the delay phase-locked circuit.
In order to solve the technical problems, the application adopts a technical scheme that: there is provided a delay locked circuit including: the input end of the delay circuit inputs a first clock signal; the input end of the delay adjusting circuit is coupled with the input end of the delay circuit, and the output end of the delay adjusting circuit is coupled with the delay circuit; the delay adjusting circuit generates a corresponding first voltage signal based on the frequency of the first clock signal, compares the first voltage signal with a preset reference voltage signal to obtain a corresponding comparison result signal, controls the delay circuit based on the comparison result signal so that the delay circuit carries out corresponding delay processing on the first clock signal, and outputs a second clock signal which is synchronous with the phase of the first clock signal through an output end of the delay circuit.
When the frequency value of the first clock signal is lower than the set threshold value, the comparison result signal controls the step length of the delay line in the delay circuit to be larger.
The output end of the delay adjusting circuit is coupled with the power end of the delay circuit, and the delay adjusting circuit also generates a matched second voltage signal based on the comparison result signal and outputs the second voltage signal as the power voltage of the delay circuit; or the delay circuit comprises at least one delay device, the delay device is arranged on at least one delay node of a delay line of the delay circuit, and the delay device is turned on or turned off in response to a comparison result signal.
The delay device is a MOS capacitor, and the MOS capacitor is turned on or turned off in response to the logic level of the comparison result signal.
When the first clock signal is lower than the set threshold value, the comparison result signal controls the MOS capacitor to be turned on, and when the first clock signal is higher than the set threshold value, the comparison result signal controls the MOS capacitor to be turned off.
Wherein the delay adjustment circuit includes: the input end of the frequency detection circuit is coupled with the input end of the delay circuit and is used for generating a corresponding first voltage signal based on the frequency of the first clock signal; the comparison circuit is coupled with the frequency detection circuit and is used for comparing the voltage value of the first voltage signal with at least one preset reference voltage signal to obtain a corresponding comparison result signal.
Wherein the frequency detection circuit includes: the control signal generation circuit is coupled with the input end of the delay circuit and is used for generating a first control signal corresponding to the first clock signal and a second control signal delayed relative to the first control signal; the charge-discharge loop is coupled with the control signal generating circuit and charges and discharges under the control of the second control signal, wherein the charge-discharge loop discharges in a pulse width period when the second control signal is at a high level, and charges in a period when the second control signal is at a low level; and the control voltage generating circuit is coupled with the output end of the charge-discharge loop and the control signal generating circuit, and samples the voltage value of the output end of the charge-discharge loop before discharging in the pulse width period that the first control signal is high level so as to output a first voltage signal, wherein the smaller the frequency of the first clock signal is, the larger the voltage value of the first voltage signal is.
The frequency of the second control signal is the same as that of the first clock signal, and the pulse width of the second control signal with high level is unchanged.
Wherein, wherein the charge-discharge circuit further includes: a power supply; the first end of the first capacitor is coupled with the power supply, and the second end of the first capacitor is grounded; the first end of the first switch is coupled with the first end of the first capacitor, the second end of the first switch is grounded, and the control end of the first switch inputs a second control signal; wherein the control voltage generating circuit further comprises: the first end of the second switch is coupled with the first end of the first capacitor, and the control end of the second switch inputs a first control signal; and the first end of the second capacitor is coupled with the second end of the second switch and is used for outputting a first voltage signal, and the second end of the second capacitor is grounded.
Wherein the control voltage generating circuit further comprises: the first end of the third switch is coupled with the first end of the second capacitor, and the control end of the third switch inputs a second control signal; the first end of the third capacitor is coupled with the second end of the third switch and is used for outputting a first voltage signal, and the second end of the third capacitor is grounded.
Wherein the control signal generating circuit includes: the output end of the first delay unit is coupled with the input end of the delay circuit; the input end of the first inverting unit is coupled with the output end of the first delay unit; the first input end of the AND gate unit is coupled with the input end of the delay circuit, the second input end of the AND gate unit is coupled with the output end of the first inverting unit, and the output end of the AND gate unit outputs a first control signal; the input end of the second delay unit is coupled with the output end of the AND gate unit, and the output end of the second delay unit outputs a second control signal.
The delay adjusting circuit further comprises a low dropout linear voltage regulator, and the low dropout linear voltage regulator is coupled to an output end of the comparing circuit and is used for generating a matched second voltage signal according to a comparison result signal.
Wherein, when the first clock signal is lower than the set threshold value, the second voltage signal output by the low dropout linear voltage regulator is lower than the second voltage signal output by the low dropout linear voltage regulator when the first clock signal is higher than the set threshold value.
Wherein the delay locked circuit further comprises: the first input end of the phase discrimination circuit is coupled with the input end of the delay circuit, and the second input end of the phase discrimination circuit is coupled with the output end of the delay circuit; the input end of the control circuit is coupled with the output end of the phase detection circuit, and the output end of the control circuit is coupled with the delay circuit.
In order to solve the technical problems, the application adopts another technical scheme that: there is provided a memory device comprising a delay locked circuit as described above.
The beneficial effects of the application are as follows: unlike the prior art, the delay lock circuit provided by the application comprises: the input end of the delay circuit inputs a first clock signal; the input end of the delay adjusting circuit is coupled with the input end of the delay circuit, and the output end of the delay adjusting circuit is coupled with the delay circuit; the delay adjusting circuit generates a corresponding first voltage signal based on the frequency of the first clock signal, compares the first voltage signal with a preset reference voltage signal to obtain a corresponding comparison result signal, controls the delay circuit based on the comparison result signal so that the delay circuit carries out corresponding delay processing on the first clock signal, and outputs a second clock signal which is synchronous with the phase of the first clock signal through an output end of the delay circuit. Through the mode, the frequency of the input clock signal is converted into the corresponding voltage signal, and then the corresponding voltage signal is compared with the preset reference voltage signal to judge whether the frequency of the input clock signal meets the specific requirement, and when the frequency meets the specific requirement, the delay performance of the delay circuit is correspondingly adjusted, on one hand, the delay adjustment is triggered only in the specific frequency range through the comparison of the signals, so that the application frequency range of the delay phase-locked circuit is wider, the problem that the delay performance of the delay phase-locked circuit is poor in a part of the frequency range is solved, and on the other hand, when the frequency of the input clock signal is normal, the delay circuit is not adjusted, and the influence on the original circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a schematic diagram of a delay locked loop according to a first embodiment of the present application;
fig. 2 is a schematic diagram of a delay locked loop according to a second embodiment of the present application;
fig. 3A is a schematic diagram of a delay locked loop according to a third embodiment of the present application;
FIG. 3B is a schematic diagram of a delay circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of the relationship between the capacitance of a MOS capacitor and the gate-source voltage;
FIG. 5A is a schematic diagram of a frequency detection circuit according to an embodiment;
FIG. 5B is a schematic diagram of a frequency detection circuit according to another embodiment;
FIG. 6 is a schematic waveform diagram of signals from nodes according to another embodiment;
FIG. 7 is a schematic diagram of a frequency detection circuit according to another embodiment;
FIG. 8 is a schematic waveform diagram of signals from nodes in yet another embodiment;
FIG. 9 is a schematic diagram of a frequency detection circuit in yet another embodiment;
FIG. 10 is a schematic waveform diagram of signals from nodes in yet another embodiment;
fig. 11 is a schematic diagram of a delay locked loop according to a fourth embodiment of the present application;
fig. 12 is a schematic structural diagram of a memory device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a schematic diagram of a delay locked loop circuit according to a first embodiment of the present application, and the delay locked loop circuit 100 includes a delay circuit 10 and a delay adjusting circuit 20.
Wherein the input end of the delay circuit 10 inputs a first clock signal CK in The method comprises the steps of carrying out a first treatment on the surface of the The input end of the delay adjusting circuit 20 is coupled to the input end of the delay circuit 10, and the output end of the delay adjusting circuit 20 is coupled to the delay circuit 10; wherein the delay adjusting circuit 20 is based on the first clock signal CK in Corresponding first voltage signal V is generated by the frequency of (2) 1 First voltage signal V 1 With a preset reference voltage signal V ref The voltage values of the voltage values are compared to obtain corresponding comparison result signals V comp And based on the comparison result signal V comp The delay circuit 10 is controlled such that the delay circuit 10 is controlled to the first clock signal CK in Performs corresponding delay processing, and outputs the first clock signal CK through the output end of the delay circuit 10 in Phase-synchronized second clock signal CK out 。
Optionally, in an application scenario, the present embodiment mainly solves the problem of the first clock signal CK in When the frequency of (2) is low, the delay performance of the delay circuit 10 is poor. Specifically, the first clock signal CK in If the clock cycle Tck of the first clock signal is longer, the delay lock circuit 100 will generate a delay circuit 10 which cannot adjust the second clock signal CK by a plurality of steps out And the first clock signal CK in Edge alignment, i.e. still not possibleLocking problems.
In one embodiment, the first clock signal CK in The smaller the frequency value of (a) is, the generated first voltage signal V 1 The larger the voltage value of (1), the higher the first voltage signal V 1 The voltage value of (2) is greater than the preset reference voltage signal V ref At the voltage level of (1), then consider the first clock signal CK in The frequency value of (2) satisfies the preset low frequency condition, the delay performance of the delay circuit 10 can be correspondingly controlled.
In another embodiment, the first clock signal CK in The larger the frequency value of (a) is, the generated first voltage signal V 1 The larger the voltage value of (1), the higher the first voltage signal V 1 The voltage value of (2) is smaller than the preset reference voltage signal V ref At the voltage level of (1), then consider the first clock signal CK in The frequency value of (2) satisfies the preset low frequency condition, the delay performance of the delay circuit 10 can be correspondingly controlled.
The method for controlling the delay performance of the delay circuit 10 may be by changing the node voltage, node current, component operating parameter, circuit on-off property, etc. of the delay circuit 10, specifically, the first clock signal CK in When the frequency value of (2) is lower than the set threshold, the delay performance of the delay circuit 10 should be adjusted, e.g. the comparison result signal V comp The step size (step) of the delay line (delay) in the control delay circuit 10 becomes large, and conversely, in the first clock signal CK in Should the frequency of the delay circuit 10 not fall below the set threshold, the delay performance of the delay circuit 10 should be adjusted, e.g. the comparison result signal V comp The step size of the delay line in the control delay circuit 10 becomes smaller.
In one embodiment, since the delay circuit 10 is in the first clock signal CK in The smaller the frequency value of (C), the better the performance, and thus, the first clock signal CK in When the frequency value of (2) is lower than the set threshold, the delay performance of the delay circuit 10 should be adjusted, e.g. the comparison result signal V comp The step size of the delay line in the control delay circuit 10 becomes large, and in the first clock signal CK in When the frequency value of (2) is not lower than the set threshold value, delay is not requiredThe delay line of circuit 10 is adjusted.
The following describes the present scheme in detail through two embodiments:
referring to fig. 2, fig. 2 is a schematic diagram of a delay locked loop circuit according to a second embodiment of the present application, and the delay locked loop circuit 200 includes a delay circuit 10 and a delay adjusting circuit 20.
Wherein the input end of the delay circuit 10 inputs a first clock signal CK in The method comprises the steps of carrying out a first treatment on the surface of the The input end of the delay adjusting circuit 20 is coupled to the input end of the delay circuit 10, and the output end of the delay adjusting circuit 20 is coupled to the power end of the delay circuit 10; wherein the delay adjusting circuit 20 is based on the first clock signal CK in Corresponding first voltage signal V is generated by the frequency of (2) 1 First voltage signal V 1 With a preset reference voltage signal V ref The voltage values of the voltage values are compared to obtain corresponding comparison result signals V comp Based on the comparison result signal V comp Generating a matched second voltage signal V 2 And apply the second voltage signal V 2 The power supply voltage is output as the delay circuit 10. It will be appreciated that the larger the supply voltage of the delay circuit 10, the smaller the delay of each gate on the corresponding delay line, and the smaller the step size of the delay line adjustment; the smaller the supply voltage of the delay circuit 10, the larger the delay of each gate on the corresponding delay line, and the larger the step size of the delay line adjustment.
In the present embodiment, the delay adjusting circuit 20 specifically includes a frequency detecting circuit 21, a comparing circuit 22, and a low dropout linear regulator 23.
An input terminal of the frequency detection circuit 21 is coupled to an input terminal of the delay circuit 10 for receiving the first clock signal CK in Corresponding first voltage signal V is generated by the frequency of (2) 1 The method comprises the steps of carrying out a first treatment on the surface of the The comparing circuit 22 is coupled to the frequency detecting circuit 21 for comparing the first voltage signal V 1 And at least one preset reference voltage signal V ref Comparing the voltage values to obtain corresponding comparison result signals V comp The method comprises the steps of carrying out a first treatment on the surface of the The low dropout linear regulator 23 is coupled to the output terminal of the comparing circuit 22 for outputting a comparison result signal V comp Generating a matched second voltage signal V 2 . Wherein the first clock signalNumber CK in The second voltage signal V output by the low dropout linear regulator 23 when the voltage is lower than the set threshold 2 Lower than the first clock signal CK in The second voltage signal V output by the low dropout linear regulator 23 when the threshold is higher than the set threshold 2 。
Alternatively, in the present embodiment, the first clock signal CK in Frequency value of (2) and first voltage signal V 1 The voltage value of (a) is inversely related, i.e. the first clock signal CK in The smaller the frequency value of the first voltage signal V 1 The greater the voltage value of (2). The comparator circuit 22 may employ a hysteresis comparator with a non-inverting input terminal for inputting the reference voltage signal V ref The inverting input end of the hysteresis comparator inputs a first voltage signal V 1 . The use of a hysteresis comparator can avoid that the comparison circuit 22 is due to the first clock signal CK in The problem of jitter (jitter) of the frequency to and fro is solved, in other embodiments the comparison circuit 22 may also be implemented with other types of comparators.
When the hysteresis comparator outputs a logic high level ("1"), V is represented ref >V 1 Description of the first clock signal CK in The low dropout linear regulator 23 may be based on the comparison result signal V of logic high level comp Outputting a larger second voltage signal V 2 As the power supply voltage of the delay circuit 10, the delay circuit 10 is driven by a larger power supply voltage, and the delay of each gate in the delay line (delay) is smaller, and the step size is smaller (or normal).
When the hysteresis comparator outputs a logic low level ("0"), V is represented ref <V 1 Description of the first clock signal CK in The low dropout linear regulator 23 may be based on the comparison result signal V of the logic low level comp Outputting a smaller second voltage signal V 2 As the power supply voltage of the delay circuit 10, the delay circuit 10 is driven by a smaller power supply voltage to lengthen the delay time of each gate on the delay line (delay), so that the step length (step) of each adjustment of the delay circuit 10 becomes larger, even if the first clock signal CK in Frequency value of (2)The cycle Tck is lower and longer, and locking can be realized within a preset number of steps as the step size of each step of adjustment becomes larger.
The comparison for the two cases is as follows:
| CK in | V 1 | V comp | V 2 | delay of | |
| Case 1 | ↑ | ↓(V ref >V 1 ) | Logic high level "1" | ↑ | ↓ |
| Case 2 | ↓ | ↑(V ref <V 1 ) | Logic low level "0" | ↓ | ↑ |
It will be appreciated that in case 1, the second voltage signal V 2 May be the operating voltage of the delay circuit 10 during normal operation, in case 2, the second voltage signal V 2 The step size of the delay line of the delay circuit 10 is increased by reducing the working voltage of the delay circuit 10 during normal operation, which is beneficial to solving the problem that the delay circuit 10 cannot be locked when performing delay processing on a low-frequency clock signal.
Referring to fig. 3A, fig. 3A is a schematic diagram of a delay locked loop circuit according to a third embodiment of the present application, and the delay locked loop circuit 200 includes a delay circuit 10 and a delay adjusting circuit 20.
Wherein the input end of the delay circuit 10 inputs a first clock signal CK in The method comprises the steps of carrying out a first treatment on the surface of the The input end of the delay adjusting circuit 20 is coupled to the input end of the delay circuit 10, and the output end of the delay adjusting circuit 20 is coupled to the delay circuit 10; wherein the delay adjusting circuit 20 is based on the first clock signal CK in Corresponding first voltage signal V is generated by the frequency of (2) 1 First voltage signal V 1 With a preset reference voltage signal V ref The voltage values of the voltage values are compared to obtain corresponding comparison result signals V comp . The delay circuit 10 includes at least one delay device disposed on at least one delay node of the delay line of the delay circuit 10, the delay device being responsive to the comparison result signal V comp Opening or closing. In one embodiment, when the delay devices on each delay node are turned on, the node generates a certain delay, the greater the delay (i.e., step size) generated by each adjustment of the delay line of the delay circuit 10, when the delay devices on the delay node of the delay line are turned off, the node has no delay, and the step size of the delay line of the delay circuit 10 is unchanged.
In the present embodiment, the delay adjusting circuit 20 specifically includes a frequency detecting circuit 21 and a comparing circuit 22.
An input terminal of the frequency detection circuit 21 is coupled to an input terminal of the delay circuit 10 for receiving the first clock signal CK in Corresponding first voltage signal V is generated by the frequency of (2) 1 The method comprises the steps of carrying out a first treatment on the surface of the The comparing circuit 22 is coupled to the frequency detecting circuit 21 for comparing the first voltage signal V 1 And at least one preset reference voltage signal V ref Comparing the voltage values to obtain corresponding comparison result signals V comp 。
Alternatively, in the present embodiment, the first clock signal CK in Frequency value of (2) and first voltage signal V 1 The voltage value of (a) is inversely related, i.e. the first clock signal CK in The smaller the frequency value of the first voltage signal V 1 The greater the voltage value of (2). The comparator circuit 22 may employ a hysteresis comparator with a non-inverting input terminal for inputting the reference voltage signal V ref The inverting input end of the hysteresis comparator inputs a first voltage signal V 1 . The use of a hysteresis comparator can avoid that the comparison circuit 22 is due to the first clock signal CK in The problem of jitter (jitter) of the frequency to and fro is solved, in other embodiments the comparison circuit 22 may also be implemented with other types of comparators.
When the hysteresis comparator outputs a logic high level ("1"), V is represented ref >V 1 Description of the first clock signal CK in The frequency value of (2) is higher than the set threshold value, and the delay device is based on the comparison result signal V comp The node is closed and no delay is present, and the delay line of the delay circuit 10 adjusts the resulting delay (i.e., step size) each step.
When the hysteresis comparator outputs a logic low level ("0"), V is represented ref <V 1 The first clock signal CK in The frequency value of (2) is lower than a set threshold value, and the delay device is based on the comparison result signal V comp On, the node generates a certain delay, and the delay (i.e., step size) generated by each step of adjustment of the delay line of the delay circuit 10 becomes larger.
Fig. 3B is a schematic diagram of a delay circuit 10 according to an embodiment of the present application, wherein the delay circuit 10 includes a delay line (delay), and each step of the delay circuit 10 adjusts the number of gates connected to the delay line by changing the control signals D0, D1 … Dn (only D0, D1 are shown in fig. 3B for simplicity) to adjust the second clock signal CK out With respect to the first clock signal CK in Gradually adjusting eventually to bring the two edges into alignment (i.e., lock). For example, initially the control signal D0 is0, first clock signal CK in The second clock signal CK is outputted as a first delay path formed by the leftmost 2 NAND gates (NAND gates 1 and 2) out The method comprises the steps of carrying out a first treatment on the surface of the If not, the second step changes the control signal D0 to 1, D1 to 0, the first clock signal CK in The second delay path composed of 4 NAND gates (NAND gates 3, 4, 5 and 2) outputs as the second clock signal CK out … … by stepwise changing the control signal to change the delay path until the total delay generated by the delay line lets the second clock signal CK out With respect to the first clock signal CK in Is aligned (i.e., locked) with the edges of the substrate. The schematic diagram of the delay line of the delay circuit 10 of fig. 3B is merely exemplary, and the delay line may be implemented by other gates. It can be seen that the amount of adjustment (i.e., the step size) of the delay line per step delay is related to the delay created by the individual gates, and that the foregoing embodiment of fig. 2 is implemented by adjusting the supply voltage to adjust the delay of the individual gates. Whereas in the embodiment of fig. 3A, a delay device is added at each delay node on each delay path of the delay line, which may be MOS capacitor 1-MOS capacitor n shown in fig. 3B (only MOS capacitors 1 and 2 are shown in fig. 3B for simplicity), the MOS capacitor is responsive to the comparison result signal V comp To adjust the delay of each delay path in the delay line, i.e. the delay (i.e. step size) adjusted by each step of the delay line, in particular the first clock signal CK in When the comparison result is lower than the set threshold value, the comparison result signal V comp Controlling the MOS capacitor of each delay node to be turned on, so that the delay of the first delay path and the delay of the second delay path are correspondingly increased, and the delay (namely the step length) of each step of adjustment of the delay line is increased; first clock signal CK in When the threshold value is higher than the set threshold value, the result signal V is compared comp The MOS capacitance of each delay node is controlled to be turned off such that the delays of both the first delay path and the second delay path are reduced accordingly, thereby reducing the delay (i.e., step size) of each step of the delay line adjustment. The main principle of forming the capacitor by the MOS tube is to use a gate oxide layer between a gate and a channel as an insulating medium, wherein the gate is used as an upper polar plate, and three ends of a source electrode, a drain electrode and a substrate are short-circuited to form a lower polar plate.
Referring to FIG. 4, FIG. 4 is a schematic diagram showing the relationship between the capacitance of the MOS capacitor, which is denoted by C, and the gate-source voltage, which is denoted by V gs And (3) representing.
When the gate-source voltage V gs To a certain extent, exceeds the threshold voltage V th An inversion layer, i.e., channel formation, is caused between the source and drain, such that the gate oxide layer acts as an insulating medium between gate and channel, and a capacitance is formed. The size of the unit area of the capacitor is related to the thickness and dielectric constant of the gate oxide layer.
When the gate-source voltage V gs Is a lower voltage than ground, at which time an N-type channel between the source and drain cannot form, but holes of the P-type substrate accumulate under the gate oxide. In this way, a capacitance is still formed between gate and the substrate, and the insulating medium is still a gate oxide layer, so that the capacitance is comparable to that when a channel is formed.
When the gate-source voltage V gs In a proper position, neither a channel is formed between the source and drain, nor holes of the P-type substrate are accumulated above. It is believed that a space charge region is formed under the gate oxide layer, and this space charge region is a region formed by combining electrons and holes, so that it is uncharged and is an "insulator". Thus, this "insulator" will overlap with the gate oxide, which will result in an equivalent dielectric thickness increase and a consequent decrease in capacitance.
Therefore, when the MOS capacitors 1 to n are used as the delay devices, the result signal V is compared comp At a high level "1", due to the comparison result signal V comp Connecting the source drain and the substrate, and keeping the gate voltage unchanged, thereby obtaining a gate-source voltage V gs Below V th The MOS capacitance "disappears", and the delay node is equivalent to no capacitance and does not provide additional delay, so that the delay (i.e. step size) adjusted by each step of the smaller delay line or the step size of the delay line is considered to be unchanged; comparison result signal V comp When the voltage is high level "0", the signal V is generated due to the comparison result comp Connect source drain and substrate, gate voltage is notBecomes the gate-source voltage V gs Higher than V th MOS capacitors are created which, due to the capacitance, cause the node to create additional delay, thereby increasing the delay (i.e., step size) of each step of the delay line adjustment.
The comparison for the two cases is as follows:
in the above embodiment, the comparison circuit 22 may also employ a plurality of hysteresis comparators for combining by setting the reference voltage signals of a plurality of different gear voltage values. By the above way, the frequency of the first clock signal is converted into the first voltage value V 1 By comparing the circuit 22 with a plurality of reference voltage signals (e.g., V ref1 And V ref2 ) Comparing to generate a multi-bit comparison result signal V comp Can be subsequently based on different comparison result signals V comp Corresponding processing is carried out, e.g. 2 reference voltage signals V ref1 And V ref2 Correspondingly the first clock signal CK in Divided into three frequency ranges of high, medium and low, when CK in Below the low threshold value, the result signal V is compared comp Output is 00, when CK in Above the low threshold and below the high threshold, the result signal V is compared comp Output is 01, when CK in Above a high threshold value, the result signal V is compared comp The output is 11. For example, the embodiment of fig. 2 is applicable to the low dropout linear regulator 23 corresponding to 3 comparison result signals V comp The second voltage signal V2 of 3 gears is output to supply the power supply voltage of 3 gears to the delay circuit 10.
The frequency detection circuit in the above two embodiments is described below.
Referring to fig. 5A, fig. 5A is a schematic diagram of a frequency detection circuit in an embodiment, and the frequency detection circuit 32 includes a control signal generating circuit 211, a charge-discharge circuit 212 and a control voltage generating circuit 213.
Wherein the control signal generating circuit 211 is coupled to the input terminal of the delay circuit 10 for generating and outputting a control signalA clock signal CK in Corresponding first control signal CK P And relative to the first control signal CK P Delayed second control signal CK PD 。
The charge/discharge circuit 212 is coupled to the control signal generating circuit 211 and is configured to receive the second control signal CK PD Charging and discharging under control: in the second control signal CK PD During the pulse width period of high level, the charge-discharge loop discharge 213 discharges in the second control signal CK PD During the low level, the charge-discharge loop 212 is charged.
A control voltage generating circuit 213, the control voltage generating circuit 213 is coupled to the output end of the charge/discharge circuit 212 and the control signal generating circuit 211, and is coupled to the first control signal CK P During the pulse width period of high level, the voltage value of the voltage signal ND1 at the output end of the charge/discharge circuit 212 before discharging is sampled to output a first voltage signal V 1 . Wherein the first clock signal CK in The smaller the frequency of the first voltage signal V 1 The greater the voltage value of (2).
In a further embodiment, the second control signal CK PD Is the frequency of the first clock signal CK in Is the same in frequency; second control signal CK PD The pulse width of the high level is unchanged, so the charge/discharge circuit 212 is connected to the second control signal CK PD The discharge time is fixed within one clock period, and the charge time is controlled by the second control signal CK PD Is of low level, i.e. is determined by the length of the second control signal CK PD Is determined by the period length of the second control signal CK PD The smaller the frequency of (a), the longer the period length, the longer the charging time of the charge-discharge circuit 212, and the higher the voltage of the voltage signal ND1 at the output terminal. Therefore, the voltage value of the voltage signal ND1 at the output end of the charge/discharge circuit 212 can reflect the first clock signal CK in Frequency size of (a) is provided. Since the voltage signal ND1 at the output end of the charge/discharge circuit 212 is saw-toothed with the charge/discharge circuit 212 periodically charging/discharging, the control voltage generating circuit 213 further samples the voltage signal ND1, ND1 is the first control signal CK P Sampling the voltage signal ND1 during the pulse width period of high level, and taking the sampled voltage signal as a first Voltage signal V 1 Output due to the high level pulse of the first control signal CKP being higher than that of the second control signal CK PD The high level pulse of (2) ensures that the sampling time point is before the discharging operation of each period of the charge-discharge loop 212, the sampled voltage signal reflects the voltage value reached by each charging operation and is used as the first voltage signal V 1 Output, thus V 1 The magnitude of (2) reflects the second control signal CK PD Is short (frequency), i.e. reflects the first clock signal CK in Is a frequency of (a) is a frequency of (b).
Referring to fig. 5B, fig. 5B is a schematic diagram of a frequency detection circuit in another embodiment, and the frequency detection circuit 32 includes a control signal generating circuit 211, a charge-discharge circuit 212 and a control voltage generating circuit 213.
Wherein the control signal generating circuit 211 is coupled to the input terminal of the delay circuit 10 for generating the first clock signal CK in Corresponding first control signal CK P And relative to the first control signal CK P Delayed second control signal CK PD 。
The charge/discharge circuit 212 is coupled to the control signal generating circuit 211, and charges/discharges under the control of the second control signal CKPD: in the second control signal CK PD During the pulse width period of high level, the charge/discharge circuit 212 discharges the second control signal CK PD During the low level, the charge-discharge loop 212 is charged.
A control voltage generating circuit 213, the control voltage generating circuit 213 is coupled to the output end of the charge/discharge circuit 212 and the control signal generating circuit 211, and is coupled to the first control signal CK P During the pulse width period of high level, the voltage value of the voltage signal ND1 at the output end of the charge/discharge circuit 212 before discharging is sampled to output a first voltage signal V 1 . Wherein the first clock signal CK in The smaller the frequency of the first voltage signal V 1 The greater the voltage value of (2).
Specifically, in the present embodiment, the charge-discharge circuit 212 further includes a power supply a, a first switch S 1 And a first capacitor C 1 Wherein the first capacitance C 1 A first end of (a) is coupled to the power source A, a first capacitor C 1 Is grounded; first switch S 1 Is coupled to the first capacitor C 1 A first switch S 1 Is grounded to the second end of the first switch S 1 A second control signal CK is input to the control terminal of (1) PD The method comprises the steps of carrying out a first treatment on the surface of the The control voltage generating circuit 213 further comprises a second switch S 2 And a second capacitor C 2 Wherein the second switch S 2 Is coupled to the first capacitor C 1 A first end (i.e., an output end ND1 of the charge/discharge circuit 212), a second switch S 2 A first control signal CK is input to the control end of (1) P The method comprises the steps of carrying out a first treatment on the surface of the Second capacitor C 2 Is coupled to the second switch S 2 And is used for outputting a first voltage signal V 1 Second capacitor C 2 Is grounded.
Next, the circuit operation principle of the present embodiment will be described with reference to fig. 6, and fig. 6 is a schematic waveform diagram of signals of each node in an embodiment. In the present embodiment the first switch S 1 And a second switch S 2 Turned on when the control terminal is at a logic high level "1", and turned off when the control terminal is at a logic low level "0".
In the first control signal CK P A logic high level "1", a second control signal CK PD At a logic low level "0", the second switch S 2 On, first switch S 1 Cut-off, power supply A is connected with first capacitor C 1 And a second capacitor C 2 Charging, first node signal ND 1 Is pulled high, the first voltage signal V 1 Pulled high. In the first control signal CK P A logic high level "0", a second control signal CK PD When the logic low level is 0, the power supply A continues to supply power to the first capacitor C 1 Charging, see, first capacitance C 1 The time of charging is controlled by the second control signal CK PD The length of time for logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD The pulse width of the logic high level "1" is fixed (how to fix the pulse width will be described later), and the first and second control signals CK P And CK (CK) PD The length of time for being a logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD Due to the first and second control signals CK P And CK (CK) PD Are all one of the first clock signal CK in Processing generates, thus having a period equal to that of the first clock signal CK in The same, therefore, the power supply A is connected to the first capacitor C 1 The charging time is set by the first clock signal CK in The period (frequency) of the first clock signal CK in The smaller the frequency of (a), the longer the period, the power supply A will be for the first capacitor C 1 The longer the charging time. In the first control signal CK P A logic low level "0", a second control signal CK PD At a logic high level "1", the second switch S 2 Cut-off, first switch S 1 Conduction, first capacitor C 1 Discharging a second capacitor C 2 Maintain, first node signal ND 1 Is pulled low, the first voltage signal V 1 And (5) maintaining. After a plurality of clock cycles, a first capacitor C 1 Is cyclically charged and discharged, the first node signal ND 1 The voltage of the second capacitor C is in a zigzag shape 2 Is charged a plurality of times, a first voltage signal V 1 Through a second capacitor C 2 And a first capacitor C 1 The charge sharing between them is pulled high, at the first clock signal CK in On the premise of stable frequency, finally reaches a stable voltage value which can reflect the first node signal ND 1 The voltage reached in each charging period can reflect the second control signal CK PD Is shorter than the period of the first clock signal CK in Frequency size of (a) is provided.
Referring to fig. 7, fig. 7 is a schematic diagram of a frequency detection circuit in another embodiment, and the frequency detection circuit 32 includes a control signal generating circuit 211, a charge-discharge circuit 212 and a control voltage generating circuit 213.
Wherein the control signal generating circuit 211 is coupled to the input terminal of the delay circuit 10 for generating the first clock signal CK in Corresponding first control signal CK P And relative to the first control signal CK P Delayed second control signal CK PD 。
The charge/discharge circuit 212 is coupled to the control signal generating circuit 211 and is at the first stageThe charge and discharge under the control of the two control signals CKPd: in the second control signal CK PD During the pulse width period of high level, the charge/discharge circuit 212 discharges the second control signal CK PD During the low level, the charge-discharge loop 212 is charged.
A control voltage generating circuit 213, the control voltage generating circuit 213 is coupled to the output end of the charge/discharge circuit 212 and the control signal generating circuit 211, and is coupled to the first control signal CK P During the pulse width period of high level, the voltage value of the voltage signal ND1 at the output end of the charge/discharge circuit 212 before discharging is sampled to output a first voltage signal V 1 . Wherein the first clock signal CK in The smaller the frequency of the first voltage signal V 1 The greater the voltage value of (2).
Specifically, in the present embodiment, the charge-discharge circuit 212 further includes a power supply a, a first switch S 1 And a first capacitor C 1 Wherein the first capacitance C 1 A first end of (a) is coupled to the power source A, a first capacitor C 1 Is grounded; first switch S 1 Is coupled to the first capacitor C 1 A first switch S 1 Is grounded to the second end of the first switch S 1 A second control signal CK is input to the control terminal of (1) PD The method comprises the steps of carrying out a first treatment on the surface of the The control voltage generating circuit 213 further comprises a second switch S 2 A second capacitor C 2 Third switch S 3 And a third capacitor C 3 Wherein the second switch S 2 Is coupled to the first capacitor C 1 A first end (i.e., an output end ND1 of the charge/discharge circuit 212), a second switch S 2 A first control signal CK is input to the control end of (1) P The method comprises the steps of carrying out a first treatment on the surface of the Second capacitor C 2 Is coupled to the second switch S 2 A second capacitor C 2 Is grounded, a third switch S 3 Is coupled to the second capacitor C 2 A third switch S 3 A second control signal CK is input to the control terminal of (1) PD The method comprises the steps of carrying out a first treatment on the surface of the Third capacitor C 3 Is coupled to the third switch S 3 And is used for outputting a first voltage signal V 1 Third capacitor C 3 Is grounded.
Unlike the above embodiment, this embodiment adds a third switch S 3 And a third capacitor C 3 And the third capacitor C 3 As a first voltage signal V 1 Is provided.
Next, the circuit operation principle of the present embodiment will be described with reference to fig. 8, and fig. 8 is a schematic waveform diagram of signals of each node in another embodiment. In the present embodiment the first switch S 1 Second switch S 2 And a third switch S 3 Turned on when the control terminal is at a logic high level "1", and turned off when the control terminal is at a logic low level "0".
In the first control signal CK P A logic high level "1", a second control signal CK PD At a logic low level "0", the second switch S 2 On, first switch S 1 And a third switch S 3 Cut-off, power supply A is connected with first capacitor C 1 And a second capacitor C 2 Charging, first node signal ND 1 And a second node signal ND 2 Is pulled high. In the first control signal CK P A logic high level "0", a second control signal CK PD When the logic low level is 0, the power supply A continues to supply power to the first capacitor C 1 Charging, see, first capacitance C 1 The time of charging is controlled by the second control signal CK PD The length of time for logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD The pulse width of the logic high level "1" is fixed (how to fix the pulse width will be described later), and the first and second control signals CK P And CK (CK) PD The length of time for being a logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD Due to the first and second control signals CK P And CK (CK) PD Are all one of the first clock signal CK in Processing generates, thus having a period equal to that of the first clock signal CK in The same, therefore, the power supply A is connected to the first capacitor C 1 The charging time is set by the first clock signal CK in The period (frequency) of the first clock signal CK in The smaller the frequency of (a), the longer the period, the power supply A will be for the first capacitor C 1 The longer the charging time. At the position ofFirst control signal CK P A logic low level "0", a second control signal CK PD At a logic high level "1", the second switch S 2 Cut-off, first switch S 1 And a third switch S 3 Conduction, first capacitor C 1 Discharging a second capacitor C 2 Maintain, third capacitor C 3 Is charged with the first node signal ND 1 Is pulled low, the second node signal ND 2 Voltage maintenance of the first voltage signal V 1 Pulled high. After a plurality of clock cycles, a first capacitor C 1 Is cyclically charged and discharged, the first node signal ND 1 The voltage of the second capacitor C is in a zigzag shape 2 Is charged a plurality of times, the second node signal ND 2 Through a second capacitor C 2 And a first capacitor C 1 The charge sharing between the capacitors is pulled high, the third capacitor C 3 Is charged a plurality of times, a first voltage signal V 1 Through a third capacitor C 3 And a second capacitor C 2 The charge sharing between them is pulled up and finally reaches a stable voltage value (at the first clock signal CK in On the premise of stable frequency), the voltage value can reflect the first node signal ND 1 The voltage reached in each charging period can reflect the second control signal CK PD Is shorter than the period of the first clock signal CK in Frequency size of (a) is provided. However, unlike the above embodiment, since the second node signal ND 2 Although being pulled high, the third capacitor C is added on the basis of the embodiment, the third capacitor C still generates saw tooth shape and affects the quality of output voltage 3 As can be seen from the image, the first voltage signal V 1 Compared with the second node signal ND 2 The voltage effect of (a) is better.
Referring to fig. 9, fig. 9 is a schematic diagram of a frequency detection circuit in another embodiment, and the frequency detection circuit 32 includes a control signal generating circuit 211, a charge-discharge circuit 212 and a control voltage generating circuit 213.
Wherein the control signal generating circuit 211 comprises a first AND gate unit A 1 First delay unit D 1 First inverting unit N 1 (NOT gate unit), second ANDDoor unit A 2 A second delay unit D 2 . First AND gate unit A 1 A first clock signal CK is input to the first input terminal of (1) in First AND gate unit A 1 A second input terminal for receiving an enable signal EN (logic high level "1" during operation), a first delay unit D 1 The input end of (a) is coupled to the first AND gate unit A 1 The output terminal of (in some embodiments, the control signal generating circuit 211 may not be provided with the first AND gate unit A 1 First delay unit D 1 Is directly connected to the input terminal of the first clock signal CK in ) The method comprises the steps of carrying out a first treatment on the surface of the First inverting unit N 1 Is coupled to the first delay unit D 1 An output terminal of (a); second AND gate unit A 2 Is coupled to the first delay unit D 1 The second AND gate unit A 2 A second input terminal coupled to the first inverting unit N 1 The output terminal of the second AND gate unit A 2 Outputs a first control signal CK P The method comprises the steps of carrying out a first treatment on the surface of the Second delay unit D 2 Is coupled to the second AND gate unit A 2 An output terminal of a second delay unit D 2 Outputs a second control signal CK PD 。
Specifically, in the present embodiment, the charge-discharge circuit 212 further includes a power supply a, a first switch S 1 And a first capacitor C 1 Wherein the first capacitance C 1 A first end of (a) is coupled to the power source A, a first capacitor C 1 Is grounded; first switch S 1 Is coupled to the first capacitor C 1 A first switch S 1 Is grounded to the second end of the first switch S 1 A second control signal CK is input to the control terminal of (1) PD The method comprises the steps of carrying out a first treatment on the surface of the The control voltage generating circuit 213 further comprises a second switch S 2 A second capacitor C 2 Third switch S 3 And a third capacitor C 3 Wherein the second switch S 2 Is coupled to the first capacitor C 1 A first end (i.e. an output end ND of the charge-discharge circuit 212) 1 ) Second switch S 2 A first control signal CK is input to the control end of (1) P The method comprises the steps of carrying out a first treatment on the surface of the Second capacitor C 2 Is coupled to the second switch S 2 Is a second end of (2)Second capacitor C 2 Is grounded, a third switch S 3 Is coupled to the second capacitor C 2 A third switch S 3 A second control signal CK is input to the control terminal of (1) PD The method comprises the steps of carrying out a first treatment on the surface of the Third capacitor C 3 Is coupled to the third switch S 3 And is used for outputting a first voltage signal V 1 Third capacitor C 3 Is grounded.
Next, the circuit operation principle of the present embodiment will be described with reference to fig. 10, and fig. 10 is a schematic waveform diagram of signals of each node in yet another embodiment. In the present embodiment the first switch S 1 Second switch S 2 And a third switch S 3 Turned on when the control terminal is at a logic high level "1", and turned off when the control terminal is at a logic low level "0".
First clock signal CK in After passing through the first delay unit D 1 And inverter N 1 Processing the obtained reference clock signal CK ref Compared with the first clock signal CK in In contrast, with a certain delay, then to the first clock signal CK in And a reference clock signal CK ref Performing AND logic processing to obtain a first control signal CK P Then to the first control signal CK P Through a second delay unit D 2 To obtain the second control signal CK PD . In this way, the first control signal CK P And a second control signal CK PD Is equal to the first clock signal CK in period length in Identical, and first and second control signals CK P And CK (CK) PD Pulse width for logic high "1" is fixed: are each a first delay unit D 1 And (5) determining.
In the first control signal CK P A logic high level "1", a second control signal CK PD At a logic low level "0", the second switch S 2 On, first switch S 1 And a third switch S 3 Cut-off, power supply A is connected with first capacitor C 1 And a second capacitor C 2 Charging, first node signal ND 1 And a second node signal ND 2 Is pulled high. In the first control signal CK P A logic high level "0", a second control signal CK PD When the logic low level is 0, the power supply A continues to supply power to the first capacitor C 1 Charging, see, first capacitance C 1 The time of charging is controlled by the second control signal CK PD The length of time for logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD The pulse width of "1" is fixed at logic high level, and the first and second control signals CK P And CK (CK) PD The length of time for being a logic low level "0" is determined by the first and second control signals CK P And CK (CK) PD Due to the first and second control signals CK P And CK (CK) PD Are all one of the first clock signal CK in Processing generates, thus having a period equal to that of the first clock signal CK in The same, therefore, the power supply A is connected to the first capacitor C 1 The charging time is set by the first clock signal CK in The period (frequency) of the first clock signal CK in The smaller the frequency of (a), the longer the period, the power supply A will be for the first capacitor C 1 The longer the charging time. In the first control signal CK P A logic low level "0", a second control signal CK PD At a logic high level "1", the second switch S 2 Cut-off, first switch S 1 And a third switch S 3 Conduction, first capacitor C 1 Discharging a second capacitor C 2 Maintain, third capacitor C 3 Is charged with the first node signal ND 1 Is pulled low, the second node signal ND 2 Voltage maintenance of the first voltage signal V 1 Pulled high. After a plurality of clock cycles, a first capacitor C 1 Is cyclically charged and discharged, the first node signal ND 1 The voltage of the second capacitor C is in a zigzag shape 2 Is charged a plurality of times, the second node signal ND 2 Through a second capacitor C 2 And a first capacitor C 1 The charge sharing between the capacitors is pulled high, the third capacitor C 3 Is charged a plurality of times, a first voltage signal V 1 Through a third capacitor C 3 And a first capacitor C 2 The charge sharing between them is pulled up and finally reaches a stable voltage value (at the first clock signal CK in On the premise of stable frequency) of the above-mentioned material, the above-mentioned material isThe voltage value can reflect the first node signal ND 1 The voltage reached in each charging period can reflect the second control signal CK PD Is shorter than the period of the first clock signal CK in Frequency size of (a) is provided. However, unlike the above embodiment, since the second node signal ND 2 Although being pulled high, the third capacitor C is added on the basis of the embodiment, the third capacitor C still generates saw tooth shape and affects the quality of output voltage 3 As can be seen from the image, the first voltage signal V 1 Compared with the second node signal ND 2 The voltage effect of (a) is better.
Referring to fig. 11, fig. 11 is a schematic diagram of a delay locked loop circuit according to a fourth embodiment of the present application, and the delay locked loop circuit 400 includes a delay circuit 10, a delay adjusting circuit 20, a phase detecting circuit 30 and a control circuit 40.
Wherein the input end of the delay circuit 10 inputs a first clock signal CK in The method comprises the steps of carrying out a first treatment on the surface of the The input end of the delay adjusting circuit 20 is coupled to the input end of the delay circuit 10, and the output end of the delay adjusting circuit 20 is coupled to the delay circuit 10; the first input end of the phase detection circuit 30 is coupled to the input end of the delay circuit 10, and the second input end of the phase detection circuit 30 is coupled to the output end of the delay circuit 10; the input end of the control circuit 40 is coupled to the output end of the phase detection circuit 30, and the output end of the control circuit 40 is coupled to the output end of the delay circuit 10. Wherein the phase detection circuit 30 compares the first clock signal CK in And the second clock signal CK out If the two phases are not synchronized (edge misalignment), the control circuit 40 further adjusts the control signals (e.g., the control signals D0-Dn in FIG. 3B) output to the delay line of the delay circuit 10 to change the delay paths of the delay line of the delay circuit 10 (e.g., the gate numbers of the different delay paths in FIG. 3B are different), and finally adjusts the first clock signal CK by a certain number of steps in A second clock signal CK delayed by a specific delay path of the delay line and outputted out And the first clock signal CK in Phase synchronization (edge alignment, i.e., locking).
Wherein the delay adjusting circuit 20 is based on the first clock signal CK in Frequency of (2)Generating a corresponding first voltage signal V 1 First voltage signal V 1 With a preset reference voltage signal V ref The voltage values of the voltage values are compared to obtain corresponding comparison result signals V comp And based on the comparison result signal V comp The delay circuit 10 is controlled such that the delay circuit 10 is controlled to the first clock signal CK in Performs corresponding delay processing, and outputs the first clock signal CK through the output end of the delay circuit 10 in Phase-synchronized second clock signal CK out . In one embodiment, the first clock signal CK in When the frequency value of (2) is lower than the set threshold value, the result signal V is compared comp The step size of the delay line (i.e., the delay adjusted per step described above) in the control delay circuit 10 becomes large. By the above way, by inputting the first clock signal CK in Is converted into a corresponding voltage signal V 1 Then with a preset reference voltage signal V ref Comparing to determine the input first clock signal CK in If the frequency of the delay phase-locked circuit 400 meets the specific requirement, the delay performance of the delay circuit 10 is correspondingly adjusted when the frequency meets the specific requirement, on one hand, the delay adjustment is triggered only in the specific frequency range through signal comparison, so that the application frequency range of the delay phase-locked circuit 400 is wider, the problem that the delay performance of the delay phase-locked circuit is poor in a part of the frequency range is solved, and on the other hand, when the frequency of an input clock signal is normal, the delay circuit is not adjusted, and the influence on the original circuit is reduced.
In other embodiments, a frequency detection circuit is provided that uses an input clock signal to generate two control signals that are relatively delayed and uses the control signals to charge a capacitor for conversion to a corresponding voltage signal.
Referring to fig. 12, fig. 12 is a schematic structural diagram of an embodiment of a memory device according to the present application, where the memory device 500 includes a delay locked circuit 501, and the delay locked circuit 501 is a delay locked circuit according to the above embodiment, and the structure and the working principle of the delay locked circuit are similar, and are not repeated herein. In a further embodiment, the storage device 500 may be a dynamic random access memoryA Memory (DRAM) device, such as a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-Access Memory). The delay lock circuit 501 may be disposed in a Double Data Rate (DDR) circuit of the memory device 500 to realize a clock (i.e. the first clock signal CK) sent by a memory controller (not shown) in ) A clock for transmitting data to the memory device 500 (i.e., the aforementioned second clock signal CK out ) Differing by an integer number of tcks, i.e. both are phase synchronized (edge aligned). In a further embodiment of the present application, even the first clock signal CK in Or by increasing the step size of the delay line in the delay lock circuit 501 to increase the total delay of the delay line after a specific step number adjustment, to make the first clock signal CK in A second clock signal CK delayed by the delay line and outputted out And the first clock signal CK in Phase synchronization (edge alignment), i.e. in the first clock signal CK in The delay locked circuit 501 can also achieve locking in case the frequency of (a) is low. While ensuring high frequency performance of the delay lock circuit 501, the delay lock circuit can simultaneously store a lower first clock signal CK in And normally works under the frequency.
Embodiments of the present application may be stored in a computer readable storage medium when implemented in the form of software functional units and sold or used as a stand alone product. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (15)
1. A delay locked circuit, the delay locked circuit comprising:
the input end of the delay circuit inputs a first clock signal;
the input end of the delay adjusting circuit is coupled with the input end of the delay circuit, and the output end of the delay adjusting circuit is coupled with the delay circuit;
the delay adjusting circuit generates a corresponding first voltage signal based on the frequency of the first clock signal, compares the first voltage signal with a preset reference voltage signal to obtain a corresponding comparison result signal, controls the delay circuit based on the comparison result signal so that the delay circuit carries out corresponding delay processing on the first clock signal, and outputs a second clock signal which is synchronous with the phase of the first clock signal through the output end of the delay circuit.
2. The delay locked circuit of claim 1, wherein,
when the frequency value of the first clock signal is lower than a set threshold value, the comparison result signal controls the step length of the delay line in the delay circuit to be increased.
3. The delay locked circuit of claim 1, wherein,
the output end of the delay adjusting circuit is coupled with the power end of the delay circuit, and the delay adjusting circuit also generates a matched second voltage signal based on the comparison result signal and outputs the second voltage signal as the power voltage of the delay circuit; or (b)
The delay circuit comprises at least one delay device, the delay device is arranged on at least one delay node of a delay line of the delay circuit, and the delay device is started or stopped in response to the comparison result signal.
4. The delay locked circuit of claim 3, wherein,
the delay device is a MOS capacitor, and the MOS capacitor is started or stopped in response to the logic level of the comparison result signal.
5. The delay locked loop of claim 4, wherein,
and when the first clock signal is higher than the set threshold, the comparison result signal controls the MOS capacitor to be turned off.
6. The delay locked circuit of claim 1, wherein,
the delay adjustment circuit includes:
the input end of the frequency detection circuit is coupled with the input end of the delay circuit and is used for generating a corresponding first voltage signal based on the frequency of the first clock signal;
the comparison circuit is coupled with the frequency detection circuit and is used for comparing the voltage value of the first voltage signal with at least one preset reference voltage signal so as to obtain the corresponding comparison result signal.
7. The delay locked loop of claim 6, wherein,
the frequency detection circuit includes:
the control signal generation circuit is coupled with the input end of the delay circuit and is used for generating a first control signal corresponding to the first clock signal and a second control signal delayed relative to the first control signal;
the charge-discharge loop is coupled with the control signal generation circuit and is charged and discharged under the control of the second control signal, wherein the charge-discharge loop discharges in a pulse width period when the second control signal is at a high level, and the charge-discharge loop charges in a period when the second control signal is at a low level; a kind of electronic device with high-pressure air-conditioning system
The control voltage generating circuit is coupled with the output end of the charge-discharge loop and the control signal generating circuit, samples the voltage value of the voltage of the output end of the charge-discharge loop before discharging in the pulse width period that the first control signal is high level so as to output the first voltage signal,
wherein the smaller the frequency of the first clock signal, the larger the voltage value of the first voltage signal.
8. The delay locked loop of claim 7, wherein,
the frequency of the second control signal is the same as that of the first clock signal, and the pulse width of the second control signal with high level is unchanged.
9. The delay locked loop of claim 7, wherein the charge-discharge loop further comprises:
a power supply;
a first capacitor, a first end of which is coupled to the power supply, and a second end of which is grounded; a kind of electronic device with high-pressure air-conditioning system
A first switch, a first end of which is coupled with a first end of the first capacitor, a second end of which is grounded, and a control end of which inputs the second control signal;
Wherein the control voltage generation circuit further comprises:
a first end of the second switch is coupled with a first end of the first capacitor, and a control end of the second switch inputs the first control signal; a kind of electronic device with high-pressure air-conditioning system
The first end of the second capacitor is coupled with the second end of the second switch and is used for outputting the first voltage signal, and the second end of the second capacitor is grounded.
10. The delay locked loop of claim 9, wherein,
the control voltage generation circuit further includes:
a first end of the third switch is coupled with the first end of the second capacitor, and a control end of the third switch inputs the second control signal;
and the first end of the third capacitor is coupled with the second end of the third switch and is used for outputting the first voltage signal, and the second end of the third capacitor is grounded.
11. The delay locked loop of claim 7, wherein,
the control signal generation circuit includes:
the output end of the first delay unit is coupled with the input end of the delay circuit;
the input end of the first inverting unit is coupled with the output end of the first delay unit;
The first input end of the AND gate unit is coupled with the input end of the delay circuit, the second input end of the AND gate unit is coupled with the output end of the first inverting unit, and the output end of the AND gate unit outputs the first control signal;
and the input end of the second delay unit is coupled with the output end of the AND gate unit, and the output end of the second delay unit outputs the second control signal.
12. The delay locked loop of claim 6, wherein,
the delay adjusting circuit further comprises a low dropout linear voltage regulator, and the low dropout linear voltage regulator is coupled to the output end of the comparison circuit and is used for generating a matched second voltage signal according to the comparison result signal.
13. The delay locked circuit of claim 12, wherein,
wherein the second voltage signal output by the low dropout linear regulator when the first clock signal is lower than a set threshold is lower than the second voltage signal output by the low dropout linear regulator when the first clock signal is higher than the set threshold.
14. The delay locked circuit of claim 1, wherein,
The delay locked circuit further includes:
the first input end of the phase discrimination circuit is coupled with the input end of the delay circuit, and the second input end of the phase discrimination circuit is coupled with the output end of the delay circuit;
and the input end of the control circuit is coupled with the output end of the phase detection circuit, and the output end of the control circuit is coupled with the delay circuit.
15. A memory device comprising a delay locked circuit as claimed in any one of claims 1 to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210580694.5A CN117176147A (en) | 2022-05-25 | 2022-05-25 | Delay phase-locked circuit and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210580694.5A CN117176147A (en) | 2022-05-25 | 2022-05-25 | Delay phase-locked circuit and storage device |
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| Publication Number | Publication Date |
|---|---|
| CN117176147A true CN117176147A (en) | 2023-12-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210580694.5A Pending CN117176147A (en) | 2022-05-25 | 2022-05-25 | Delay phase-locked circuit and storage device |
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| CN (1) | CN117176147A (en) |
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