CN117174726A - Semiconductor substrate, preparation method and image sensor - Google Patents
Semiconductor substrate, preparation method and image sensor Download PDFInfo
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- CN117174726A CN117174726A CN202311114955.5A CN202311114955A CN117174726A CN 117174726 A CN117174726 A CN 117174726A CN 202311114955 A CN202311114955 A CN 202311114955A CN 117174726 A CN117174726 A CN 117174726A
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- 239000000758 substrate Substances 0.000 title claims abstract description 177
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 80
- 229920005591 polysilicon Polymers 0.000 claims description 78
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 19
- 238000005498 polishing Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 abstract description 12
- 238000007789 sealing Methods 0.000 abstract description 10
- 238000005247 gettering Methods 0.000 abstract description 5
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 19
- 238000012360 testing method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- 238000012546 transfer Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The application discloses a semiconductor substrate, a preparation method and an image sensor. The semiconductor substrate of the present application includes: a substrate having a first surface; a trapping layer located on a side of the substrate remote from the first surface, the trapping layer being for trapping metal ions from or through the substrate; and the back sealing layer is positioned on one side of the capture layer away from the substrate. The application improves the external gettering capability of the semiconductor substrate by arranging the trapping layer on one side of the substrate of the semiconductor substrate. The semiconductor substrate provided by the application is used as a matrix of the image sensor, so that the dark current and the white pixel number of the image sensor are reduced.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a substrate, an image sensor and a preparation method of the substrate and the image sensor.
Background
The semiconductor substrate is a basic material for manufacturing semiconductor devices, and the silicon substrate has good electrical properties, thermal stability and processability, and is a commonly used semiconductor substrate material. The quality of the silicon substrate is critical to the performance and fabrication of the semiconductor device.
Disclosure of Invention
The application aims to provide a semiconductor substrate, a preparation method and an image sensor, which can solve the technical problems.
An embodiment of the present application provides a semiconductor substrate including:
a substrate having a first surface;
a capture layer on a side of the substrate remote from the first surface;
and the back sealing layer is positioned on one side of the capturing layer away from the substrate.
In some embodiments, the trapping layer is configured to trap metal ions, including metal ions in the substrate and metal ions that pass through the first surface into the substrate.
In some embodiments, the capture layer has a thickness of
In some embodiments, the substrate has a resistivity of 0.010ohm-cm to 0.020ohm-cm.
Correspondingly, the embodiment of the application provides a preparation method of a semiconductor substrate, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a first surface;
forming a capture layer on a side of the substrate away from the first surface;
and forming a back sealing layer, wherein the back sealing layer is positioned on one side of the capturing layer away from the substrate.
In some embodiments, the thickness of the capture layer is, in the thickness direction of the substrate
In some embodiments, the step of forming the trapping layer comprises:
forming a second polysilicon layer, wherein the second polysilicon layer is positioned on the first surface; forming a first polysilicon layer, wherein the substrate is provided with a second surface which is away from the first surface, and the second polysilicon layer is positioned on the second surface; removing the second polysilicon layer and reserving the first polysilicon layer; the first polysilicon layer serves as the trapping layer.
In some embodiments, the first polysilicon layer and/or the second polysilicon layer is prepared by: depositing a polysilicon layer on the surface of the substrate by adopting a silicon-containing gas; the consumption of the silicon-containing gas is
In some embodiments, in the step of forming the first polysilicon layer, the substrate is placed in an environment having a temperature in the range of 600 ℃ to 660 ℃; and/or, in the step of forming the second polysilicon layer, the substrate is placed in an environment with a temperature ranging from 600 ℃ to 660 ℃.
In some embodiments, the second polysilicon layer is removed by a chemical mechanical polishing method comprising: and grinding the second polysilicon layer and removing the second polysilicon layer.
In some embodiments, the first substrate is adsorbed to a polishing head having a chamber along a thickness direction of the semiconductor substrate, theThe chamber has a first thickness H 1 μm, the first substrate has a second thickness H 2 μm, satisfy: 0 < H 1 -H 2 ≤20μm。
Accordingly, an embodiment of the present application provides an image sensor, including the above-described semiconductor substrate; alternatively, the image sensor includes a semiconductor substrate prepared by the method for preparing a semiconductor substrate as described above; the semiconductor substrate serves as a base body of the image sensor.
In some embodiments, the semiconductor substrate comprises a P-type substrate.
The application has the beneficial effects that: compared with the prior art, the application provides a semiconductor substrate, a preparation method and an image sensor. The semiconductor substrate of the present application includes: a substrate having a first surface; a trapping layer located on a side of the substrate remote from the first surface, the trapping layer being for trapping metal ions from or through the substrate; and the back sealing layer is positioned on one side of the capture layer away from the substrate. The application improves the external gettering capability of the semiconductor substrate by arranging the trapping layer on one side of the substrate of the semiconductor substrate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a process for fabricating a semiconductor substrate according to an embodiment of the present application;
FIG. 2 is a flow chart of a process for fabricating a semiconductor substrate according to an embodiment of the present application;
FIG. 3 is a flow chart of a process for fabricating a semiconductor substrate according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a semiconductor substrate according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an image sensor according to an embodiment of the present application;
FIG. 6 is a schematic view of a polishing platen and a semiconductor substrate according to an embodiment of the present application;
FIG. 7 is a graph of geometric flatness test results of a semiconductor substrate prepared in accordance with an embodiment of the present application, wherein graph A is a maximum local flatness SFQR test result; the maximum edge flatness ESFQR test results are shown in the diagram B, the maximum local flatness average results are shown in the diagram C, the maximum edge flatness average results are shown in the diagram D, and the maximum local flatness test results with the distribution quantity of 95% are shown in the diagram E;
FIG. 8 is a schematic diagram of an image sensor according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a front-illuminated image sensor according to an embodiment of the present application;
FIG. 10 is a graph showing the dark current test results of a semiconductor substrate applied to an image sensor according to an embodiment of the present application;
FIG. 11 is a graph showing the detection result of white pixels of a semiconductor substrate applied to an image sensor in accordance with an embodiment of the present application;
in the figure, 1-semiconductor substrate, 100-base, 101-first surface, 102-second surface, 110-first substrate, 200-trapping layer, 210-first polysilicon layer, 220-second polysilicon layer, 300-back seal layer; 2-grinding disc, 3-polishing head, 300-chamber, 301-bottom surface.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described in the following in conjunction with the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. In addition, in the description of the present application, the term "comprising" means "including but not limited to". The terms first, second, third and the like are used merely as labels, and do not impose numerical requirements or on the order of construction. Various embodiments of the application may exist in a range of forms; it should be understood that the description in a range format is merely for convenience and brevity and should not be construed as a rigid limitation on the scope of the application; it is therefore to be understood that the range description has specifically disclosed all possible sub-ranges and individual values within that range. For example, it should be considered that a description of a range from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the ranges, such as 1, 2, 3, 4, 5, and 6, wherever applicable. In addition, whenever a numerical range is referred to herein, it is meant to include any reference number (fractional or integer) within the indicated range. In the present application, the X direction is the thickness direction, and the Y direction is the extending direction of the semiconductor substrate.
As shown in fig. 4, an embodiment of the present application provides a semiconductor substrate including: a substrate 100, the substrate 100 having a first surface 101; a trapping layer 200, the trapping layer 200 being located on a side of the substrate 100 remote from the first surface 101, the trapping layer 200 being for trapping metal ions from the substrate 100 or for trapping metal ions passing through the substrate 100; back seal layer 300, back seal layer 300 is located on the side of capture layer 200 remote from substrate 100. The capturing layer 200 is arranged on one side of the substrate 100, so that the external gettering capability of the semiconductor substrate is enhanced, the metal ion pollution is effectively reduced, and the yield of products is improved.
In some embodiments, the thickness of the acquisition layer 200 isSuch as the thickness of the trapping layer 200>Is 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000 or a range of any two values, such as the thickness of the trapping layer 200 is +.>Or (I)>In the present application, since the provision of the trapping layer 200 deteriorates the geometric flatness of the substrate,the thickness of the trapping layer 200 of the present application is +.>Within the scope, the degree of deterioration of the device flatness by the arrangement of the trapping layer 200 can be improved while satisfying the external gettering function of the semiconductor substrate of the present application.
In some embodiments, the substrate 100 is a silicon substrate, and the resistivity of the substrate 100 is between 0.010ohm-cm and 0.020ohm-cm. Such as a range of values of any or any two of the resistivity (ohm-cm) values of 0.01, 0.011, 0.012, 0.013, 0.014, 0.015, 0.016, 0.017, 0.018, 0.019, 0.020 of the substrate 100.
In some embodiments, the resistivity of the base 100 is changed by, for example, ion doping the silicon substrate, which may be ion implantation. Alternatively, doping elements of different concentrations are added to the silicon material during the silicon substrate preparation process for changing the resistivity of the base 100.
In some embodiments, the trapping layer 200 comprises polysilicon as a gettering material for trapping metal ions from the epitaxial layer. When the semiconductor substrate is applied to a device, metal ions of a device layer can be captured, and dark current and the number of white pixels of the device are reduced.
In some embodiments, the back-sealing layer 300 is a silicon oxide layer, and the thickness of the back-sealing layer 300 isThickness of back seal layer 300>Any or a range of any two values of 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000.
In some embodiments, the back-sealing layer 300 includes low temperature silicon oxide (LTO).
In some embodiments, the low temperature silicon oxide deposition temperature is 400 ℃ to 800 ℃, such as the deposition temperature (DEG C) is any value or range of values of any two values of 400, 450, 500, 550, 600, 650, 700, 750, 800. In some embodiments, the back-sealing layer 300 is prepared at a temperature of 600-650 ℃.
In some embodiments, the back seal layer 300 is prepared by the following method: the substrate 100 with the capture layer 200 is subjected to chemical vapor deposition to produce the back-seal layer 300. In some embodiments, the flow rate (Standard Cubic Centimeters per Minute, sccm) of oxygen is in the range of 495-616. In some embodiments, siH 4 The flow rate (Standard Cubic Centimeters per Minute, sccm) of the gas was 45 to 56.
In some embodiments, the present application provides a method for manufacturing a semiconductor substrate, including:
as shown in fig. 1, a substrate 100 is provided, the substrate 100 having a first surface 101;
forming a capturing layer 200, wherein the capturing layer 200 is located on a side of the substrate 100 away from the first surface 101; a back seal layer 300 is formed, the back seal layer 300 being located on the side of the trapping layer 200 remote from the substrate 100.
In some embodiments, the thickness of the capture layer 200 along the thickness direction X of the substrate is
As shown in fig. 2, the step of forming the trapping layer 200 includes:
forming a second polysilicon layer 220, the second polysilicon layer 220 being located on the first surface 101;
forming a first polysilicon layer 210, wherein the substrate 100 has a second surface 102 facing away from the first surface 101, and the second polysilicon layer 220 is located on the second surface 102;
as shown in fig. 3, the second polysilicon layer 220 is removed, leaving the first polysilicon layer 210; the first polysilicon layer 210 serves as the trapping layer 200.
In some embodiments, the first polysilicon layer 210 is prepared by: depositing a first polysilicon layer 210 on the surface of the substrate 100 using a silicon-containing gas; the consumption of the silicon-containing gas isSuch as the consumption of silicon-containing gas>The value of (2) is any value or any two value ranges of 2.0, 2.5, 3.0, 3.5 and 4.0. The application can control the thickness of the first polysilicon layer 210 and the deposition speed of the surface of the substrate 100 of the first polysilicon layer 210 by controlling the consumption of the silicon-containing gas, and can reduce the influence of the preparation of the polysilicon layer on the flatness of the semiconductor substrate 1.
In some embodiments, the second polysilicon layer 220 is prepared by the following method: depositing a second polysilicon layer 220 on the surface of the substrate 100 using a silicon-containing gas; the consumption of the silicon-containing gas isSuch as the consumption of silicon-containing gas>The value of (2) is any value or any two value ranges of 2.0, 2.5, 3.0, 3.5 and 4.0. The application can control the thickness of the second polysilicon layer 220 by controlling the consumption of the silicon-containing gas, and can also control the deposition speed of the surface of the substrate 100 of the second polysilicon layer 220, thereby improving the quality of the prepared semiconductor substrate.
In some embodiments, in the step of forming the first polysilicon layer 210, the substrate 100 is placed in an environment having a temperature ranging from 600 ℃ to 660 ℃.
In some embodiments, in the step of forming the second polysilicon layer 220, the substrate 100 is placed in an environment having a temperature ranging from 600 ℃ to 660 ℃.
In some embodiments, the temperature (c) at which the first polysilicon layer 210 is formed takes on any value or range of values of 600, 610, 620, 630, 6405, 650, 660.
In some embodiments, the temperature (deg.c) at which the second polysilicon layer 220 is formed takes on any value or range of values of 600, 610, 620, 630, 6405, 650, 660.
In some embodiments, the polysilicon layers are formed simultaneously on both sides of the substrate 100, i.e., the first polysilicon layer 210 and the second polysilicon layer 220 are formed simultaneously on both sides of the substrate 100, resulting in the first substrate 110. The first polysilicon layer 210 and the second polysilicon layer 220 are formed at a temperature ranging from 600 to 620 c, or at a temperature ranging from 640 to 660 c.
Thickness of the polysilicon layer to be preparedThe preparation method can be adopted as follows:
in some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared in the following manner: at a first temperature ranging from 600 ℃ to 620 ℃, the silicon-containing gas at a first flow rate ofThe polysilicon layer is prepared under the condition of (1).
In some embodiments, the silicon-containing gas is at a second flow rate in a second temperature range of 640 ℃ to 660 DEG CThe polysilicon layer is prepared under the condition of (1).
When the thickness of the prepared polysilicon layer is larger thanThe preparation method can be adopted as follows:
in some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared in the following manner: at a first temperature ranging from 600 ℃ to 620 ℃, the silicon-containing gas at a third flow rateThe polysilicon layer is prepared under the condition of (1).
In some embodiments, the silicon-containing gas is at a fourth flow rate in the second temperature range of 640 ℃ to 660 DEG CThe polysilicon layer is prepared under the condition of (1).
In some embodiments, the silicon-containing gas comprises SiH 4 。
In some embodiments, the second polysilicon layer 220 is removed by a chemical mechanical polishing method.
As shown in fig. 6, the apparatus for performing the chemical mechanical polishing method includes a polishing platen 2 and a polishing head 3, the polishing head 3 having a chamber 300, and the surface of the semiconductor substrate is adsorbed by a pressurizing bladder through an intermediate gas pipe during the chemical mechanical polishing, i.e., the first substrate 110 is closely attached to the polishing head 3 above by vacuum adsorption, and a transfer pipe sends out a polishing liquid including a etchant and abrasive grains, and the second polysilicon layer 220 is removed by high-speed rotation of the polishing head 3.
In some embodiments, the chamber 300 has a first thickness H along the thickness direction (X direction) of the semiconductor substrate 1 1 μm, the substrate has a second thickness H 2 μm, satisfy: 0 < H 1 -H 2 And is less than or equal to 20 mu m. Such as H 1 -H 2 The value of (2) is any value or any range of two values of 5, 10, 15 and 20. If H is 5 ≡H 1- -H 2 15 or less, or 5 or less H 1 -H 2 Not more than 10, or not more than 10 but not more than H 1 -H 2 ≤15。
In some embodiments, H 1 -H 2 The distance therebetween refers to the distance S μm of the bottom surface 301 of the slinger 3 from the top surface of the first substrate 110. In the present application, the bottom surface or the top surface is described in the opposite direction, and the specific structure of the present application is not limited.
In some embodiments, the distance S of the bottom surface 301 of the projectile 3 from the top surface of the first substrate 110 satisfies: s is more than 0 and less than or equal to 20 mu m. If the value of S is any value or a range consisting of any two values of 5, 10, 15 and 20.
In some embodiments, a first thickness H of chamber 300 1 Has a value of 780 μm to 790 μm, e.g. a first thickness H 1 Is 780, 785, 790 or a range of any two values.
In some embodiments, the first substrate 110Is of the second thickness H 2 Has a value of 765 μm to 785 μm, e.g. a second thickness H 2 The value of (a) is any value or any two value ranges of 765, 770, 775, 780 and 785.
When H of the application 1 -H 2 Above 20 μm, such as a chamber 300 having a height of 800 μm, the first substrate 110 has a thickness of 775 μm, and the polysilicon layer is formed at a thickness ofIn the range of (2) the geometric flatness test is performed on the obtained substrate, the geometric flatness of the substrate is found to be poor, and the influence of the polysilicon layer prepared by the present application on the deterioration of the geometric flatness of the substrate can be improved when the distance between the lower surface of the chamber 300 and the first substrate 110 is reduced.
In some embodiments, the geometric flatness of the semiconductor substrate 1 of the present application may be characterized by a maximum local flatness and a maximum edge flatness.
In some embodiments, the flatness test apparatus is an optical microscope, a Scanning Electron Microscope (SEM), or an Atomic Force Microscope (AFM).
As shown in fig. 5 and 7, an embodiment of the present application provides an Image Sensor (CIS, CMOS Image Sensor), where the Image Sensor includes the above-mentioned semiconductor substrate 1, and the semiconductor substrate 1 is used as a base body of the Image Sensor, where a device layer 400 is disposed in an epitaxial layer of the semiconductor substrate 1.
As shown in fig. 7, in some embodiments, the semiconductor substrate of the present application is a P-type substrate, and the image sensor includes an NMOS transistor structure and a PMOS transistor structure. The image sensor shown in fig. 7 of the present application is only one example, and the semiconductor substrate 1 of the present application may be an N-type substrate, and the image sensor may be a front-illuminated image sensor or a back-illuminated image sensor.
In some embodiments, as shown in fig. 8, the present application provides a schematic structural diagram of a front-illuminated sensor, and the image sensor includes a sensor body, a color filter 500 and a lens 600. The sensor body includes a substrate and a CMOS device structure, i.e., device layer 400, disposed on the substrate.
In some embodiments, the color filter 500 is used to capture light of different colors, and the following types of color filters may be selected: bayer filters, X-Trans filters, and the like.
In some embodiments, lens 600 is used to focus and direct light onto the sensor, and the following types of lenses may be selected: such as plano-convex lenses, biconvex lenses, etc.
In some embodiments, the semiconductor substrate prepared in the above embodiments of the present application is applied to an image sensor, so as to improve the number of white pixels and dark current generated under different operating temperature conditions due to leakage caused by excessive metal ions in the device.
In some embodiments, the average dark current pixel count (pixel) of an image sensor to which the semiconductor substrate 1 of the present application is applied ranges from 16.3 to 16.6.
In some embodiments, the number of white pixels (pixels) of an image sensor to which the semiconductor substrate 1 of the present application is applied ranges from 200 to 250.
Example 1:
a semiconductor substrate: the P-type monocrystalline silicon polished wafer with the diameter of 300mm is selected as the substrate 100, the resistivity is 0.010-0.020 ohm-cm, and the total thickness H before epitaxy 2 775 μm.
Processing substrate 100 using LPCVD furnace table and selecting SiH gas containing silicon 4 The purity of (C) is more than 99.9999 percent, N 2 The purity of (2) was 99.9999999% or more, and a polycrystalline silicon layer was produced by depositing polycrystalline silicon using an LPCVD furnace and processing the same monocrystalline silicon feed material, the production process being shown in Table 1.
The second polysilicon layer 220 is removed: the polishing head 3 has a polishing chamber 300 along the thickness direction X of the substrate, the chamber 300 having a first thickness H 1 780 μm.
Preparing a back seal layer 300: processing substrate 100 using APCVD furnace table and selecting SiH gas containing silicon 4 The purity of (C) is more than 99.9999 percent, O 2 The purity of (C) is more than 99.9999999 percent, N 2 The purity of (C) is 99.999999999% or more, APCVD is usedThe furnace platform carries out low-temperature oxide layer lamination, the temperature interval of deposition is 640-650 ℃, and the same monocrystalline silicon material is selected for processing to prepare the oxide layer back sealing film thicknessA semiconductor substrate as shown in fig. 4 is obtained.
Examples 2 to 12: the preparation method is the same as in example 1, except that the preparation parameters of the polysilicon layer are adjusted as shown in table 1.
Comparative example 1: the trapping layer 200 is not prepared.
TABLE 1 preparation process parameters of semiconductor substrates
The geometric flatness of example 5 (5K), example 7 (4K), example 8 (3K), example 10 (2K), example 11 (1K), comparative example 1 (BSL) was tested, and the test results are shown in table 2 and fig. 7.
TABLE 2 test results of geometric flatness of semiconductor substrates
| Maximum local flatness (SFQR Max/nm) | Maximum edge flatness (ESFQR Max/nm) | |
| Example 5 | 182.583 | 182.684 |
| Example 7 | 154.735 | 128.798 |
| Example 8 | 106.021 | 118.025 |
| Example 10 | 61.277 | 56.463 |
| Example 11 | 43.985 | 35.909 |
| Comparative example 1 | 58.507 | 55.889 |
As can be seen from the results of Table 2 and FIG. 2, the acquisition layer 200 prepared according to the present application has a thickness ofIn the range of (2), the deterioration of the geometric flatness of the semiconductor substrate 1 is improved as compared with comparative example 1 in which the trapping layer 200 is not deposited. In addition, the present application improves the CMP method, and the thickness of the prepared trapping layer 200 is +.>The degree of deterioration of the geometric flatness in the range is suppressed. The thickness of the trapping layer prepared by the application is in the range +.>The maximum local flatness (nm) is in the range of 130nm to 250nm, and the thickness of the capturing layer prepared by the method is in the range of +.>The maximum edge flatness (μm) is in the range of 130nm to 250nm.
It can also be seen from FIG. 2 that the Mean of the maximum local flatness (SFQR Mean/nm) and the Mean of the maximum edge flatness (ESFQR Mean/nm) of the acquisition layer 200 of the present application. The results are consistent with the trend of maximum local flatness and maximum edge flatness, indicating that the preparation of the trapping layer 200 of the present application improves for the case where the semiconductor substrate 1 is degraded in flatness.
Application example:
the semiconductor substrate 1 prepared in example 2 (poly+lto8k+3k), example 5 (poly+lto5k+3k), example 8 (poly+lto3k+3k) and comparative example 1 (POR) was applied to an image sensor (CMOS).
The image sensor is prepared by the following method:
a circuit structure including NMOS and PMOS as shown in fig. 8 is formed on the semiconductor substrate 1 using an ion implantation method.
Preparing a gate: a gate electrode is formed on the semiconductor substrate 1 using polysilicon for controlling the flow of current.
And (3) forming an oxidation layer: silicon dioxide is formed as an oxide layer on the semiconductor substrate 1 for isolating and protecting the circuits.
Metal deposition: and depositing metallic copper on the oxide layer for forming electrodes and connecting wires.
Photolithography and etching: the shape and structure of the circuit is defined on the oxide layer using photolithographic techniques, and then the excess material is removed by etching to form the desired circuit structure.
Dielectric layer formation: a dielectric layer is formed between the metal electrode and the connection line for isolating and protecting the circuit.
And (3) metal filling: and filling metal on the dielectric layer to form the top of the electrode and the connecting wire.
Packaging and testing: after the preparation of the image sensor is completed, packaging and testing are carried out. The sensor body is encapsulated in an encapsulation material, and an electrical performance test and an image quality test are performed.
The testing method comprises the following steps:
dark current (dark current): a dark current image sensor (Dark Current Imaging) is used to detect dark current.
White pixel): dark field test method.
Table 2 test results of the application of the semiconductor substrate prepared according to the present application to front-illuminated image sensor
| Average dark current pixel number (pixel) | White pixel number (pixel) | |
| Example 2 | 16.3～16.6 | 200～250 |
| Example 5 | 16.3～16.6 | 200～250 |
| Example 8 | 16.3～16.6 | 200～250 |
| Comparative example 1 | 16.6～17.0 | 600～900 |
As can be seen from the test data of dark current shown by D-Mean in fig. 10, the test data of white pixel shown by Peak02 in fig. 11, and the data of table 3, the verification result of the semiconductor substrate 1 prepared by the present application in the device shows that the image sensor (greenish blue orange line) having the back polysilicon layer has a significant tendency to improve compared with the semiconductor substrate (red line) not using the back polysilicon layer, the dark current and the white pixel are greatly reduced and the tightening phenomenon is brought close, and it is proved that the electric leakage phenomenon caused by the metal ion pollution generated in the processing process can obtain a better control effect in the semiconductor substrate having the back polysilicon layer prepared by the present application. The application can effectively improve the dark current and white pixels of the CIS product, thereby improving the quality of CIS chip devices.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The above description has been made in detail on a semiconductor substrate, a manufacturing method and an image sensor provided by the embodiments of the present application, and specific examples are applied to illustrate the principles and embodiments of the present application, and the above description of the embodiments is only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (12)
1. A semiconductor substrate, comprising:
-a substrate (100), the substrate (100) having a first surface (101);
-a capturing layer (200), the capturing layer (200) being located on a side of the substrate (100) remote from the first surface (101);
-a back seal layer (300), the back seal layer (300) being located on a side of the capture layer (200) remote from the substrate (100).
2. The semiconductor substrate according to claim 1, wherein the thickness of the trapping layer (200) along the thickness direction (X) of the base (100) is
3. The semiconductor substrate according to claim 1, wherein the base (100) has a resistivity of 0.010ohm-cm to 0.020ohm-cm.
4. A method of manufacturing a semiconductor substrate, comprising:
providing a substrate (100), the substrate (100) having a first surface (101);
-forming a trapping layer (200), the trapping layer (200) being located on a side of the substrate (100) remote from the first surface (101);
a back seal layer (300) is formed, the back seal layer (300) being located on a side of the capture layer (200) remote from the substrate (100).
5. The method of manufacturing a semiconductor substrate according to claim 4, wherein the thickness of the trapping layer (200) is, in the thickness direction (X) of the base (100)
6. The method of manufacturing a semiconductor substrate according to claim 4, wherein the step of forming the trapping layer (200) comprises:
-forming a second polysilicon layer (220), said second polysilicon layer (220) being located at said first surface (101);
forming a first polysilicon layer (210), wherein the substrate (100) is provided with a second surface (102) deviating from the first surface (101), and the second polysilicon layer (220) is positioned on the second surface (102) to obtain a first substrate (110);
-removing the second polysilicon layer (220), leaving the first polysilicon layer (210); the first polysilicon layer (210) acts as the trapping layer (200).
7. The method of manufacturing a semiconductor substrate according to claim 6, characterized in that the first polysilicon layer (210) and/or the second polysilicon layer (220) is manufactured by: depositing polysilicon on the surface of the substrate (100) using a silicon-containing gas; the consumption of the silicon-containing gas is
8. The method of manufacturing a semiconductor substrate according to claim 6, wherein in the step of forming the first polysilicon layer (210), the base (100) is placed in an environment having a temperature range of 600 ℃ to 660 ℃; and/or, in the step of forming the second polysilicon layer (220), the substrate (100) is placed in an environment having a temperature ranging from 600 ℃ to 660 ℃.
9. The method of manufacturing a semiconductor substrate according to claim 6, wherein the second polysilicon layer (220) is removed by a chemical mechanical polishing method comprising: grinding the second polysilicon layer (220) and removing the second polysilicon layer (220).
10. The method of manufacturing a semiconductor substrate according to claim 9, wherein the first substrate (110) is adsorbed to a head (3), the head (3) having a chamber (300), the chamber (300) having a first thickness H along a thickness direction (X) of the semiconductor substrate (1) 1 μm, the first substrate (110) has a second thickness H 2 μm, satisfy: 0 < H 1 -H 2 ≤20μm。
11. An image sensor, characterized in that the image sensor comprises a semiconductor substrate (1) as claimed in any one of claims 1 to 3; alternatively, the image sensor comprises a semiconductor substrate (1) prepared by the method for preparing a semiconductor substrate (1) according to any one of claims 4 to 10;
the semiconductor substrate (1) serves as a base body of the image sensor.
12. The image sensor according to claim 11, characterized in that the semiconductor substrate (1) comprises a P-type substrate.
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