CN117174698A

CN117174698A - Semiconductor structure and forming method thereof

Info

Publication number: CN117174698A
Application number: CN202310970696.XA
Authority: CN
Inventors: 郭富强; 陈信良; 郑新立; 许庭祯
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-08-04
Filing date: 2023-08-03
Publication date: 2023-12-05

Abstract

Embodiments of the present disclosure provide embodiments of methods. The method comprises the following steps: patterning the substrate to form a trench; etching the substrate to modify the trench to have rounded tips; forming a stack comprising conductive layers and dielectric layers in the trench, wherein the conductive layers and dielectric layers alternate with each other within the stack; forming an insulating compression film in the first trench, thereby sealing the void in the trench; and forming conductive plugs respectively connected to the conductive layers. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such a shrink process generally provides benefits by improving production efficiency and reducing associated costs. Such scaling also increases the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are required to achieve these advances. For example, capacitors (as passive devices) are important devices in integrated circuits and are widely used for various purposes, such as in Random Access Memory (RAM), non-volatile memory devices, decoupling capacitors, or RC circuits. As ICs move to advanced technology nodes with smaller component sizes, capacitors are almost inflexible and cannot shrink to smaller sizes due to the capacitor characteristics. The capacitor suffers considerable circuit area losses. In addition, existing methods of fabricating capacitors introduce defects into the capacitors and cause undesirable problems such as stress and induced wafer warpage. It is therefore desirable to provide capacitor structures integrated with other circuit devices and methods of making the same that do not suffer from the drawbacks discussed above.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: patterning the substrate to form a trench; etching the substrate, thereby modifying the trench to have rounded tips; forming a stack comprising conductive layers and dielectric layers in the trench, wherein the conductive layers and dielectric layers alternate with each other within the stack; forming an insulating compression film in the first trench, thereby sealing a void in the trench; and forming conductive plugs respectively connected to the conductive layers.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: patterning the substrate to form deep trenches; etching the substrate, thereby modifying the deep trench; forming a stack including conductive layers and dielectric layers alternately stacked and folded in the trench; and forming an insulating film in the first trench, thereby sealing a void in the deep trench, wherein the deep trench is configured as a plurality of deep trench unit cells, wherein the deep trenches in each of the deep trench unit cells are oriented in the same direction, and wherein the deep trenches in adjacent deep trench unit cells are oriented in different directions.

Still other embodiments of the present application provide a semiconductor structure comprising: a plurality of deep trenches formed on a substrate; a stack of conductive layers and dielectric layers alternately disposed in the plurality of deep trenches; and conductive plugs bonded on the conductive layers, respectively, wherein the deep trenches are configured as a plurality of deep trench unit cells, and wherein the plurality of deep trenches in each of the deep trench unit cells are oriented in the same direction.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of an Integrated Circuit (IC) structure with deep trench capacitors constructed in accordance with some embodiments of the present disclosure;

fig. 2 is a cross-sectional view of an IC structure with deep trench capacitors constructed in accordance with some embodiments of the present disclosure;

fig. 3 is a top view of a deep trench capacitor array constructed in accordance with some embodiments of the present disclosure;

fig. 4A is a schematic diagram of a deep trench capacitor constructed in accordance with some embodiments of the present disclosure;

Fig. 4B is a schematic diagram of a deep trench capacitor constructed in accordance with some embodiments of the present disclosure;

figure 5 is a cross-sectional view of a deep trench capacitor constructed in accordance with some embodiments of the present disclosure;

fig. 6A, 6B, 6C, and 6D are cross-sectional views of a deep trench capacitor constructed at various stages of fabrication in accordance with various embodiments of the present disclosure;

fig. 7A, 7B, 7C, 7D, and 7E are top views of deep trench capacitor arrays constructed in accordance with various embodiments of the present disclosure;

fig. 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, and 8I are cross-sectional views of a deep trench capacitor constructed at various stages of fabrication in accordance with various embodiments of the present disclosure;

fig. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, and 9I are cross-sectional views of a deep trench capacitor constructed at various stages of fabrication in accordance with various embodiments of the present disclosure;

fig. 10A, 10B, 10C, and 10D are cross-sectional views of a deep trench capacitor structure constructed in accordance with various embodiments of the present disclosure at various stages of fabrication;

fig. 11A and 11B are cross-sectional views of deep trench capacitor structures constructed in accordance with various embodiments of the present disclosure;

Figure 12 is a top view of a deep trench capacitor structure constructed in accordance with various embodiments of the present disclosure;

fig. 13A, 13B, 13C, and 13D are top views of a deep trench capacitor structure constructed at various stages of fabrication in accordance with various embodiments of the present disclosure; and

fig. 14A, 14B, 14C, and 14D are top views of a deep trench capacitor structure constructed at various stages of fabrication in accordance with various embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features. Reference numerals and/or characters may be repeated among the various examples described herein. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various disclosed embodiments and/or configurations. Further, specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, in the present disclosure, forming an element on another element that is connected to and/or coupled to another element may include embodiments in which the elements are formed in direct contact, and may also include forming additional elements between the elements such that the elements may not be in direct contact.

Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present disclosure below, forming a component on another component that is connected to and/or coupled to another component may include embodiments in which the components are formed in direct contact, and may also include forming additional components between the components such that the components may not be in direct contact. Further, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate understanding of the relationship of one component of the disclosure to another. Spatially relative terms are intended to encompass different orientations of the device comprising the component. Furthermore, when a value or range of values is described using "about," "approximately," etc., the term is intended to encompass values within a reasonable range including the described value, such as within +/-10% of the described value or other values as would be understood by one of skill in the art. For example, the term "about 5nm" encompasses dimensions in the range from 4.5nm to 5.5 nm.

Embodiments of the present disclosure relate generally to Integrated Circuit (IC) structures and methods of manufacturing the same, and more particularly, to deep trench capacitor devices integrated with other devices to form three-dimensional (3D) IC structures. The IC structure also includes other devices such as Field Effect Transistors (FETs), fin FETs (finfets), and other multi-gate devices. In some examples, the multi-gate device includes a full-gate-all-around (GAA) device.

Fig. 1 is a cross-sectional view of an IC structure 100 constructed in accordance with some embodiments of the disclosure. The IC structure 100 includes a first circuit structure 52 formed on a first substrate 54 and a second circuit structure 56 formed on a second substrate 58. The first circuit structure 52 and the second circuit structure 56 are bonded together by a suitable bonding technique, such as wafer level packaging, wafer chip level packaging, or fan-out wafer level packaging techniques, to form a 3D IC structure. The first circuit structure 52 and the second circuit structure 56 are electrically coupled into the integrated circuit by suitable techniques, such as hybrid bond layers, semiconductor vias (TSVs), other suitable coupling techniques, or combinations thereof.

In particular, the substrate (the first substrate 54 or the second substrate 58) may include a semiconductor substrate such as a silicon substrate. The semiconductor substrate may optionally include a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), or a combination thereof. The substrate (54 or 58) may also include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), germanium-on-insulator (GOI) substrate. Portions of the substrate may be doped, such as doped with a P-type dopant (e.g., boron (B) or Boron Fluoride (BF) ₃ ) Or doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)). The doped portion may also be doped with a combination of p-type and n-type dopants (e.g., to form a p-type well and an adjacent n-type well). The doped portions may be formed directly on the substrate in a p-well structure, in an n-well structure, in a double-well structure, or using a raised structure.

The first substrate 54 and the second substrate 58 each include a front side surface and a back side surface extending in the X-direction and the Y-direction, wherein the normal direction is in the Z-direction. The X direction, Y direction and Z direction are perpendicular to each other. The first circuit structure 52 and the second circuit structure 56 are bonded together by a front side surface of the first substrate 54 to a front side surface of the second substrate 58, a front side surface of the first substrate 54 to a back side surface of the second substrate 58, a hybrid bond layer, an interposer, or other configuration, depending on the individual applications.

The first circuit structure 52 includes various devices 60 formed on the first substrate 54. Device 60 includes FET, finFET, GAA devices, other multi-gate devices, or combinations thereof. The first circuit structure 52 further includes an interconnect structure 62 that couples the device 60 into a first circuit, such as a digital circuit, a memory circuit, an analog circuit, or a combination thereof.

The second circuit structure 56 includes various devices 63 formed on the second substrate 58. Device 63 may include various devices such as high frequency devices, imaging sensor circuits, passive devices (e.g., capacitors and inductors), microelectromechanical system (MEMS) devices, or combinations thereof. The second circuit structure 56 further includes an interconnect structure 66 coupling the device 63 to a second circuit coupled to the first circuit formed on the first substrate 54. In particular, the device 63 formed in the second circuit structure 56 includes a deep trench capacitor (DCT) structure 64, the DCT structure 64 including one or more deep trench capacitors. The deep trench capacitor includes a plurality of layers of conductive material and layers of dielectric material alternately stacked and folded into one or more deep trenches to increase capacitance. The IC structure 100 including the DCT structure 64 and its method of fabrication are described in further detail below.

Fig. 2 is a partial cross-sectional view of a portion or an entirety of an IC structure 100 provided by arranging a chipset using a combination of multi-chip packaging techniques, such as chip on wafer (CoWoS) packaging techniques, system on integrated chip (SoIC) multi-chip packaging techniques, integrated fan-out (InFO) packages, in accordance with aspects of embodiments of the present disclosure. The IC structure 100 (which may be referred to as a 3D IC package and/or a 3D IC module) includes a CoW structure 102 attached to a substrate 104 (e.g., a package substrate), in the depicted embodiment, the substrate 104 includes a package assembly 104A and a package assembly 104B. The CoW structure 102 includes a chipset (e.g., core chip 106-1, core chip 106-2, core chip 106-3, memory chip 108-1, memory chip 108-2, input/output (I/O) chip 110-1, and I/O chip 110-2) that are electrically connected to each other) attached to an interposer 115. The chipset is arranged as at least one chip stack, such as chip stack 120A and chip stack 120B. Chip stack 120A includes core chip 106-2 and core chip 106-3, and chip stack 120B includes I/O chip 110-1 and I/O chip 110-2. In the depicted embodiment, the chips of chip stack 120A and chip stack 120B are directly bonded face-to-face and/or face-to-back to provide a SoIC package of a multi-chip package. In some embodiments, the chip stack of the multi-chip package includes a combination of chip types, such as a core chip with one or more memory chips disposed thereon. For clarity, fig. 2 has been simplified to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the multi-chip package, and in other embodiments of the multi-chip package, some of the components described below may be replaced, modified, or eliminated.

Core chip 106-1, core chip 106-2, and core chip 106-3 are Central Processing Unit (CPU) chips and/or other chips. In some embodiments, core chip 106-1 is a CPU chip that forms at least part of a CPU cluster, and core chip 106-2 and core chip 106-3 are GPU chips. In some embodiments, core chip 106-1, core chip 106-2, core chip 106-3, or a combination thereof represents a stack of CPU dies that may be bonded and/or encapsulated in a manner that provides a CPU package and/or a CPU-based SoIC package. In some embodiments, core chip 106-1, core chip 106-2, core chip 106-3, or a combination thereof represents a stack of dies that may be bonded and/or sealed in a manner that provides a GPU package and/or a SoIC package (e.g., GPU-based SoIC package). In some embodiments, core chip 106-1, core chip 106-2, core chip 106-3, or a combination thereof represents a stack of CPU dies that may be bonded and/or encapsulated in a manner that provides a core package and/or a core-based SoIC package. In some embodiments, core chip 106-1, core chip 106-2, core chip 106-3, or a combination thereof is a SOC.

The memory chips 108-1 and 108-2 are High Bandwidth Memory (HBM) chips, GDDR memory chips, dynamic Random Access Memory (DRAM) chips, static Random Access Memory (SRAM) chips, magnetoresistive Random Access Memory (MRAM) chips, resistive Random Access Memory (RRAM) chips, other suitable memory chips, or combinations thereof. In some embodiments, memory chip 108-1 and memory chip 108-2 are HBM chips that form at least part of a memory device. In some embodiments, memory chip 108-1 and memory chip 108-2 are Graphics Double Data Rate (GDDR) memory chips that form at least part of a memory device. In some embodiments, memory chip 108-1 is an HBM chip and memory chip 108-2 is a GDDR memory chip, or vice versa, that form at least part of a memory device. In some embodiments, memory chip 108-1 and/or memory chip 108-2 represent a stack of memory dies that may be bonded and/or sealed in a manner that provides a memory package and/or a memory-based SoIC package. The memory package may be an HBM package (also referred to as an HBM multi-dimensional dataset) or a GDDR memory package.

Core chip 106-1, core chip 106-2 (and thus chip stack 120A), memory chip 108-1, memory chip 108-2, and I/O chip 110-1 (and thus chip stack 120B) are attached to and/or interconnected to interposer 115. Interposer 115 is attached and/or interconnected to substrate 104. Various bonding mechanisms may be implemented in the multi-chip package, such as conductive bumps 122 (e.g., metal bumps), semiconductor vias (TSVs) 124, bond pads 126, or combinations thereof. For example, conductive bumps 122 physically and/or electrically connect core chip 106-1, core chip 106-2 (and thus chip stack 120A), memory chip 108-1, memory chip 108-2, and I/O chip 110-1 (and thus chip stack 120B) to interposer 115. Conductive bumps 122 and TSVs 124 physically and/or electrically connect interposer 115 to substrate 104. TSVs 124 of interposer 115 are electrically connected to conductive bumps 122 of the chips and/or chip stacks of CoW structure 102 through conductive wiring structures (paths) 128 of interposer 115. Bond pads 126 physically and/or electrically connect core chip 106-2 and core chip 106-3 of chip stack 120A and I/O chip 110-1 and I/O chip 110-2 of chip stack 120B. Likewise, the dielectric bonding layer adjacent to bond pad 126 may physically and/or electrically connect core chip 106-2 of chip stack 120A and core chip 106-3 and/or I/O chips 110-1 and 110-2 of chip stack 120B. In some embodiments, the conductive bumps 122 connecting the chip and/or chip stack to the interposer 115 may be micro-bumps, while the conductive bumps 122 connecting the interposer 115 to the substrate 104 may be controllably collapsed chip connections (referred to as C4 bonds) (e.g., solder bumps and/or solder balls).

In some embodiments, the substrate 104 is a package substrate, such as a coreless substrate or a cored substrate, that may be physically and/or electrically connected to another component by electrical connections 130. The electrical connectors 130 are electrically connected to the conductive bumps 122 of the interposer 115 through conductive wiring structures (paths) 132 of the substrate 104. In some embodiments, package assembly 104A and package assembly 104B are part of a single package substrate. In some embodiments, package assembly 104A and package assembly 104B are different package substrates arranged side-by-side. In some embodiments, the substrate 104 is an interposer. In some embodiments, the substrate 104 is a Printed Circuit Board (PCB).

In some embodiments, the interposer 115 is a semiconductor substrate, such as a silicon wafer (which may be generally referred to as a silicon interposer). In some embodiments, the interposer 115 is a laminate substrate, a core package substrate, a coreless package substrate, or the like. In some embodiments, the interposer 115 may include an organic dielectric material, such as a polymer, which may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer-based materials, or combinations thereof. In some embodiments, redistribution lines (layers) (RDLs) may be formed in the interposer 115, such as in an organic dielectric material of the interposer 115. RDL may form part of conductive wiring structure 128 of interposer 115. In some embodiments, the RDL electrically connects bond pads on one side of interposer 115 (e.g., the top side of interposer 115 to which the chipset is attached) to bond pads on the other side of interposer 115 (e.g., the bottom side of interposer 115 to substrate 104). In some embodiments, the RDL electrically connects bond pads on the top side of interposer 115 that may electrically connect the chips of the chipset. In the disclosed embodiment, one or more deep trench capacitors may be embedded in the interposer 115.

In some embodiments, the multi-chip package may be configured as a 2.5DIC package and/or a 2.5D IC module by rearranging the chip sets such that each chip is bonded and/or attached to interposer 115. In other words, the 2.5D IC module does not include chip stacks such as chip stack 120A and chip stack 120B, and the chips of the chipset are arranged in a single plane. In such an embodiment, core chip 106-3 and I/O chip 110-2 are electrically and/or physically connected to the interposer through conductive bumps 122.

Fig. 3 is a partial top view of a portion or an entirety of an IC structure 100 constructed in accordance with some embodiments of the disclosure. In particular, the IC structure 100 includes a Deep Trench Capacitor (DTC) structure 64, the DTC structure 64 having one or more deep trench capacitors arranged in a two-dimensional array 140 of DTC unit cells 67. In various embodiments, one or more DTC unit cells 67 are connected into one capacitor, depending on the individual application. Deep trench capacitor structures 64 are formed on a substrate 142, such as a semiconductor substrate. The DTC structure 64 and its method of fabrication are further described below in conjunction with other figures.

Fig. 4A is a partial cross-sectional view of a portion or the entirety of an IC structure 100 constructed in accordance with some embodiments of the disclosure. In particular, one deep trench capacitor 65 is shown. The deep trench capacitor 65 includes a stack of a plurality of conductive layers 146 and a plurality of dielectric layers 148 alternately stacked to form a staggered capacitor. Fig. 4B further shows a schematic diagram of the interleaving capacitor 65. The conductive layers 146 are grouped into a first conductive layer 146A and a second conductive layer 146B. The first conductive layer 146A is connected to form a first electrode a, and the second conductive layer 146B is connected to form a second electrode B. The first electrode a and the second conductive layer 146B are staggered. If the number of conductive layers 146 (including 146A and 146B) is N1, then the total capacitance of the crossover capacitor 65 is c=εa/d (N1-1), where ε is the dielectric constant of the dielectric layer 148; a is the area of each conductive layer 146; and d is the distance between adjacent conductive layers or the thickness of one dielectric layer 148. Increasing the dielectric constant of dielectric layer 148 and increasing the area of conductive layer 146 effectively increases the capacitance of staggered capacitor 65, according to the above formula. As noted above, to increase the capacitance of the staggered capacitors 65, one or more high-k dielectric materials are employed to form the dielectric layer 148. To further increase the capacitance of the staggered capacitor 65, the stack of conductive layer 146 and dielectric layer 148 is folded into a deep trench to increase the area of the conductive layer 146 without increasing the package area of the deep trench capacitor 65 on the substrate 142, as will be described further below. The DTC structure 64 may include one or more deep trench capacitors 65. One deep trench capacitor 65 may be distributed in one or more DTC unit cells 67.

Conductive layer 146 includes a metal, metal alloy, silicide, other conductive material, or a combination thereof. In some embodiments, conductive layer 146 comprises titanium nitride (TiN) deposited by Physical Vapor Deposition (PVD), other suitable deposition methods, or combinations thereof. Dielectric layer 148 serves as the dielectric medium for the capacitor and includes a high-k dielectric material, a low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In the disclosed embodiment, the dielectric layer 148 includes a high-k dielectric material, other suitable dielectric material, or a combination thereof. The high-k dielectric material is a dielectric material having a dielectric constant greater than that of thermal silicon oxide. In various embodiments, the high-k dielectric material includes a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, a metal oxynitride. In a further embodiment, the high-k dielectric material comprises metal aluminates, zirconium silicate, zirconium aluminate, hfO ₂ 、ZrO ₂ 、ZrO _x N _y 、HfO _x N _y 、HfSi _x O _y 、ZrSi _x O _y 、HfSi _x O _y N _z 、ZrSi _x O _y N _z 、Al ₂ O ₃ 、TiO ₂ 、Ta ₂ O ₅ 、La ₂ O ₃ 、CeO ₂ 、Bi ₄ Si ₂ O ₁₂ 、WO ₃ 、Y ₂ O ₃ 、LaAlO ₃ 、PbTiO ₃ 、BaTiO ₃ 、SrTiO ₃ 、PbZrO ₃ Other suitable high-k dielectric materials, or combinations thereof. In various examples, the method of forming the high-k dielectric material film includes vapor deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), PVD, atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), other suitable techniques, or combinations thereof. In another example, the high-k dielectric material may be formed by UV-ozone oxidation, which includes sputtering a metal film; through O under UV light irradiation ₂ Oxidizing the metal film in situ.

Fig. 5 is a partial cross-sectional view of a portion or an entirety of an IC structure 100 constructed in accordance with some embodiments of the disclosure. In particular, one DTC unit cell 67 is shown. In the illustrated embodiment, one DTC unit cell 67 is configured as one deep trench capacitor 65. In an alternative embodiment, one DTC unit cell 67 is configured as part of the deep trench capacitor 65. The stack of conductive layer 146 and dielectric layer 148 is folded and inserted into a plurality of deep trenches 150. Thus, the disclosed capacitor is referred to as a Deep Trench Capacitor (DTC) 65. The number of trenches occupied by the capacitor 65 is N2. Increasing N1, N2, or both will increase the capacitance of capacitor 65.

Fig. 6A is a partial cross-sectional view of a portion or the entirety of an IC structure 100 constructed in accordance with some embodiments of the disclosure. In particular, a DTC structure 64 is shown. The stack of conductive layer 146 and dielectric layer 148 is folded and inserted into deep trench 150. In the illustrated embodiment, the DTC structure 64 includes four conductive layers 146 and is formed in three deep trenches 150, in this case n1=4 and n2=3. It should be appreciated that N1 and N2 may be any suitable integer within the scope of embodiments of the present disclosure.

In fig. 6A and other figures below, DTC structure 64 shows only one DTC unit cell, which may be configured as one capacitor or as part of one capacitor, depending on the electrical connection (such as conductive layer 146 and conductive plug 154, which will be described later). The DTC unit cell 67 is defined as a structure including a plurality of deep trenches arranged in a region and oriented longitudinally in the same direction. Deep trenches in adjacent DTC unit cells are not connected, such as those shown in fig. 3. In addition, the conductive layers 146 of the deep trenches 150 in the same DTC unit cell extend continuously and are connected. As noted above, the DTC structure may include a plurality of deep trench capacitors 65, each deep trench capacitor 65 may be distributed in one or more DTC unit cells 67.

In particular, the DTC structure 64 is formed on a substrate 142, such as a semiconductor substrate, and may also include one or more layers of dielectric material 152, such as an interlayer dielectric (ILD) layer deposited on the substrate 142. The layer of dielectric material 152 may comprise silicon oxide, silicon nitride, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Deep trenches 150 are formed in a layer of dielectric material 152.

The stack of conductive layer 146 and dielectric layer 148 is folded and inserted into deep trench 150 and extends further over the trench, such as over dielectric material layer 152. The stack is further patterned such that the DTC structures 64 are defined in localized areas of the DTC unit cells without interfering with adjacent DTC unit cells. In an alternative embodiment where deep trenches in multiple DTC unit cells are configured to form one capacitor, the stack is patterned such that conductive layers 146 in those DTC unit cells are connected.

Conductive plugs 154 are formed in another layer of dielectric material 156 and bonded to respective conductive layers 146 including 146A and 146B. The conductive plugs that engage conductive layer 146A are electrically connected, such as by an interconnect structure, to form first electrode a, and the conductive plugs that engage conductive layer 146B are electrically connected to form second electrode B. Dielectric material layer 156 may comprise silicon oxide, silicon nitride, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. In the disclosed embodiment, the dielectric material layer 156 comprises undoped quartz glass (USG) deposited by CVD, other suitable deposition, or a combination thereof. The conductive plugs 154 include aluminum, copper, tungsten, other suitable metals, metal alloys, or combinations thereof. In the disclosed method, the conductive plugs 154 include a plurality of conductive layers designed to address various issues. Specifically, a layer of dielectric material surrounds the sidewalls of each conductive plug 154 to provide isolation from the intervening conductive layer 146. In some embodiments, dielectric spacers may also be formed on the sidewalls of the conductive plugs 154 to provide various functions including adhesion and preventing interdiffusion. In some embodiments, a barrier layer, such as titanium and titanium nitride or tantalum and tantalum nitride, may be formed on the sidewalls of the conductive plugs 154 to prevent interdiffusion. The conductive plugs 154 can have different configurations, such as being joined on an extension stack on both sides as shown in fig. 6B, on an extension stack on one side as shown in fig. 6C, on an extension stack between two adjacent deep trenches 150 as shown in fig. 6D, or other configurations, such as a subset being joined on an extension stack between deep trenches, and another subset being joined on an extension stack on either side or both sides. DTC structure 64 may include other components, such as one or more dielectric materials formed in different configurations with corresponding compositions, such as one additional dielectric layer formed in deep trench 150.

Fig. 7A-7E are partial top views of portions or whole of an IC structure 100 constructed in accordance with some embodiments of the present disclosure. Specifically, an array 140 of DTC unit cells 67 is shown. As shown in fig. 7A, the deep trenches 150 of the DTC unit cells 67 are configured in such a manner that the deep trenches 150 in adjacent DTC unit cells 67 are oriented in different directions so as to reduce stress. For example, the deep trenches 150 in one DTC unit cell 67 are oriented longitudinally in the X-direction, and the deep trenches 150 in adjacent DTC unit cells 67 are oriented longitudinally in the Y-direction. The conductive plugs 154 are placed in various configurations, as depicted in fig. 6A-6D. In fig. 7A, a conductive plug 154 for each DTC unit cell 67 is formed on the extension stack on one side. In fig. 7B, a conductive plug 154 for each DTC unit cell 67 is formed on the extension stack between adjacent deep trenches 150. In fig. 7C, the conductive plugs 154 for each DTC unit cell 67 are formed either on the extension stack on one side or on the extension stack between adjacent deep trenches 150. In fig. 7D, the conductive plugs 154 for each DTC unit cell 67 are formed on the extension stack between adjacent deep trenches 150, but in different locations. In fig. 7E, the conductive plugs 154 for each DTC unit cell 67 are distributed over the extension stack between adjacent deep trenches 150. In the disclosed embodiment, the diameter of the conductive plugs 154 may be controlled to be less than 100 angstroms, such as about 30 angstroms. Therefore, the gap G between adjacent DTC unit cells 67 is controlled to a small amount, such as 100A.

The formation of DTC structure 64 is further described with reference to fig. 8A-8I and fig. 9A-9I. Fig. 8A-8I are partial cross-sectional views of a portion or an entirety of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure at various stages of manufacture. Fig. 9A-9I are partial cross-sectional views of a portion or an entirety of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure at various stages of manufacture.

Referring to fig. 8A, a layer of dielectric material 152 over the substrate 142 is patterned to form deep trenches. In some embodiments, the substrate 142 is directly patterned to form deep trenches therein. The operations include forming a patterned etch mask 192 by a photolithographic process. In some embodiments, the etch mask 192 is a soft etch mask, such as a patterned photoresist layer. A patterned photoresist layer is formed by a photolithography process. In alternative embodiments, the etch mask 192 is a hard etch mask, such as a silicon oxide or other suitable layer of dielectric material. In a further embodiment, the patterned photoresist layer is formed by a photolithographic process. An etching process is applied to the hard mask to transfer the openings of the patterned photoresist layer to the hard mask. The opening of the etch mask 192 defines a region for the deep trench. After forming the hard mask, the patterned photoresist layer may be removed by wet stripping or plasma ashing.

Referring to fig. 8B, dielectric material layer 152 is patterned by a suitable etching process, such as wet etching, dry etching, or a combination thereof, to form deep trenches 194. In the disclosed embodiments, the etching process includes a dry etching process using an etchant comprising fluorine, chlorine, or a combination thereof, such as silicon tetrafluoride (SiF) ₄ ) Silicon fluorine group SiF _x (x is 1, 2 or 3), silicon tetrachloride (SiCl ₄ ) Silicon chloride group SiCl _x (x is 1, 2 or 3) or a combination thereof. According to some embodiments, the etching process is performed at a temperature in a range between 100 ℃ and 300 ℃. It should be noted that the walls of deep trenches 194 have narrow openings and that patterned dielectric material layer 152 has a residual portion on top of the walls of deep trenches 194, such as shown in dashed circles 196.

Referring to fig. 8C, a second etching process is applied to dielectric material layer 152, thereby modifying the profile of deep trench 194 and forming deep trench 150. In this operation, a second etch mask 198, such as a hard mask through a photolithography process and an etching process or a soft mask through a photolithography process, is formed on the dielectric material layer 152. The etch mask 198 also includes one or more openings, but is different than the openings of the etch mask 192. In the disclosed embodiment, the etch mask 198 includes openings to expose walls of deep trenches in the DTC structure 64 in addition to edge walls of the DTC structure 64. In this case, a second etching process is applied to the exposed walls of the deep trenches in the DTC structure 64 in order to etch and remove the remaining portions of the exposed walls of the deep trenches, thereby modifying the wall tops to be rounded and narrow tips, as shown by the dashed circle 200. The second etching process is similar to the first etching process in fig. 8B in terms of etchant and etching temperature. In further this embodiment, the walls of the deep trench 150 have non-uniform heights with a height difference H. In some embodiments, H is in the range between 100 angstroms and 1000 angstroms, and H ₀ In the range between 0.5 μm and 50 μm.

Referring to fig. 8D, a dielectric liner 202 can be further formed in the deep trench 150 by a suitable method, such as thermal process, CVD, other suitable method, or a combination thereof. In some embodiments, the dielectric liner 202 is an oxide layer, such as undoped quartz glass. The formation of the dielectric liner 202 includes performing a thermal annealing process in a furnace having an oxygen ambient at an elevated annealing temperature. In some embodiments, the deep trench 150 is formed in the substrate 142 comprising silicon, and the forming of the dielectric liner 202 comprises performing a thermal oxidation process in a furnace in an oxygen-containing environment. In some embodiments, the annealing temperature is in a range between 800 ℃ and 1200 ℃. In some embodiments, dielectric liner 202 has a thickness in a range between 10 angstroms and 500 angstroms. In some embodiments, the deep trench 150 is formed in a dielectric layer 152 comprising a dielectric material, and the forming of the dielectric liner 202 comprises performing an annealing process in a furnace in an environment comprising oxygen and silane. In some embodiments, the annealing temperature is in a range between 800 ℃ and 1200 ℃. In some embodiments, dielectric liner 202 has a thickness in a range between 10 angstroms and 500 angstroms.

Referring to fig. 8E, the stack of conductive layer 146 and dielectric layer 148 is deposited sequentially over the layer of dielectric material 152 in the deep trench 150, as described above. In particular, the dielectric layer 148 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material, or a combination thereof. Dielectric layer 148 may be formed by CVD, atomic Layer Deposition (ALD), other suitable deposition methods, or combinations thereof. The conductive layer may comprise a metal (such as copper, aluminum, or tungsten) or a metal alloy (such as an aluminum copper alloy, other metal alloys), other suitable conductive materials, or combinations thereof. Conductive layer 146 may be formed by PVD, plating, CVD, other suitable methods, or combinations thereof.

Still referring to fig. 8E, a compressively stressed dielectric film 204 is formed over the stack in the deep trench 150 so as to form a void (air gap) 206 in the deep trench 150 and seal the void in the deep trench. This can be accomplished by various factors, such as by controlling the deposition rate to be large enough that the dielectric film 204 is deposited in the deep trench 150 and closes quickly on top, leaving a void 206 in the deep trench 150. In the disclosed embodiment, the deposition of the dielectric film 204 is performed at an elevated temperature, so that the dielectric film 204 is constrained by compressive stress when the workpiece is cooled to room temperature. Such deposited dielectric film 204 and DTC structure 64 may effectively reduce substrate warpage problems for two reasons. Because the stack of conductive layer 146 and dielectric layer 148 has a tensile stress to the workpiece, the compressive stress of dielectric film 204 compensates for the tensile stress of the stack, and void 206 formed in DTC structure 64 provides a free space for the workpiece to further relieve any stress, if any.

Dielectric film 204 may be formed by CVD, furnace process, other suitable methods, or combinations thereof. In some embodiments, the dielectric film 204 is formed by CVD. In a further embodiment, the dielectric film 204 includes a nitrogen-free anti-reflective layer (NFARL), siO ₂ Undoped Silica Glass (USG), silicon carbide, other suitable dielectric material, or combinations thereof. Example(s)For example, the dielectric film 204 includes the use of a dielectric film comprising ethyl orthosilicate Si (OC ₂ H ₅ ) ₄ A precursor of (TEOS) is silicon oxide formed by CVD. According to some embodiments, the deposition temperature is in a range between 800 ℃ and 1200 ℃.

In some embodiments, the dielectric film 204 is formed by a furnace process having a process temperature in a range between 800 ℃ and 1200 ℃. In a further embodiment, the dielectric film 204 comprises silicon nitride, siO ₂ Undoped Silica Glass (USG), silicon carbide, polysilicon, other suitable materials, or combinations thereof. For example, dielectric film 204 includes silicon oxide formed in a furnace using a precursor including TEOS.

Referring to fig. 8F, the stack is further patterned to define a stack of conductive layers 146 and dielectric layers 148 for one DTC structure 64, such as being spaced apart from a stack of adjacent DTC structures 64. DTC structure 64 is further shown in fig. 8H and 8I. In some embodiments, H is in the range between 100 angstroms and 1000 angstroms, and H ₀ In the range between 0.5 μm and 50 μm. The void 206 extends vertically about the vertical dimension Hv of the deep trench 150. For example, the void 206 spans vertically a dimension Hv in the range between 0.5 μm and 50 μm. Dielectric film 204 or collective 208 vertically spans a dimension T above void 206 that is greater than 50 angstroms, such as ranging between 50 angstroms and 200 angstroms from void 206 to the top surface of deep trench 150. In some embodiments, the ratio H/H ₀ In the range between 0.02 and 0.002. In some embodiments, the aspect ratio (width/depth) of the deep trench 150 is in the range between 1 and 1000 or between 10 and 100. The width W and wall thickness S of the deep trenches 150 (or the spacing between adjacent deep trenches) define a ratio W/S that is greater than 2, such as in the range between 2 and 20. Fig. 8I also shows the non-uniform height of the deep trenches 150.

The final DTC structure 64 is also shown in fig. 8G, where 208 collectively represents a stack of dielectric layer 148 and conductive layer 146, as well as dielectric film 204. Specifically, the void 206 is formed in the deep trench 150, and the compressively stressed dielectric film seals the void 206 in the deep trench 150. Furthermore, the walls of the deep trenches 150 in the DTC structure 64 have different heights. Other components of the DTC structure 64, such as conductive plugs, will be described further below.

Referring to fig. 9A, a layer of dielectric material 152 over the substrate 142 is patterned to form deep trenches. The operations include forming a patterned etch mask 192 by a photolithographic process. In some embodiments, the etch mask 192 is a soft etch mask, such as a patterned photoresist layer. A patterned photoresist layer is formed by a photolithography process. In alternative embodiments, the etch mask 192 is a hard etch mask, such as a silicon oxide or other suitable layer of dielectric material. In a further embodiment, the patterned photoresist layer is formed by a photolithographic process. An etching process is applied to the hard mask to transfer the openings of the patterned photoresist layer to the hard mask. The opening of the etch mask 192 defines a region for the deep trench. After forming the hard mask, the patterned photoresist layer may be removed by wet stripping or plasma ashing.

Referring to fig. 9B, dielectric material layer 152 is patterned by a suitable etching process, such as wet etching, dry etching, or a combination thereof, to form deep trenches 194. In the disclosed embodiments, the etching process includes a dry etching process using an etchant comprising fluorine, chlorine, or a combination thereof, such as silicon tetrafluoride (SiF) ₄ ) Silicon fluorine group SiF _x (x is 1, 2 or 3), silicon tetrachloride (SiCl ₄ ) Silicon chloride group SiCl _x (x is 1, 2 or 3) or a combination thereof. According to some embodiments, the etching process is performed at a temperature in a range between 100 ℃ and 300 ℃. It should be noted that the walls of deep trenches 194 have narrow openings and that patterned dielectric material layer 152 has a residual portion on top of the walls of deep trenches 194, such as shown in dashed circles 196.

Referring to fig. 9C, a second etching process is applied to dielectric material layer 152 without an etching mask, thereby modifying the profile of deep trench 194 and forming deep trench 150. In this operation, the etching mask is not used. A second etching process is applied only to the exposed walls of the deep trenches in the DTC structure 64 in order to etch and remove the remaining portions of all walls of the deep trenches, modifying the wall tops to be rounded and narrow tipped, as shown by the dashed circle 200. The second etching process is similar to the first etching process in fig. 8B in terms of etchant and etching temperature. In further this embodiment, the walls of the deep trench 150 have a uniform height, as all the walls are similarly modified by the second etching process. In some embodiments, the aspect ratio (width/depth) of the deep trench 150 is in the range between 1 and 1000 or between 10 and 100. The width W and wall thickness S of the deep trenches 150 (or the spacing between adjacent deep trenches) define a ratio W/S that is greater than 2, such as in the range between 2 and 20.

Referring to fig. 9D, another dielectric liner 202 can be further deposited in the deep trench 150 by a suitable method, such as thermal process, CVD, other suitable method, or a combination thereof. In some embodiments, the dielectric liner 202 is an oxide layer, such as undoped quartz glass. The formation of the dielectric liner 202 includes performing an annealing process in a furnace having an oxygen ambient at an elevated annealing temperature. In some embodiments, the formation of the dielectric liner 202 includes performing an annealing process in a furnace in an environment containing oxygen and silane. In some embodiments, the annealing temperature is in a range between 800 ℃ and 1200 ℃. In some embodiments, dielectric liner 202 has a thickness in a range between 100 angstroms and 300 angstroms.

Referring to fig. 9E, a stack of conductive layer 146 and dielectric layer 148 is deposited sequentially over the dielectric material layer 152 in the deep trench 150, as described above. In particular, the dielectric layer 148 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric material, or a combination thereof. The dielectric layer 148 may be formed by CVD, ALD, other suitable deposition methods, or combinations thereof. The conductive layer may comprise a metal (such as copper, aluminum, or tungsten) or a metal alloy (such as an aluminum copper alloy, other metal alloys), other suitable conductive materials, or combinations thereof. Conductive layer 146 may be formed by PVD, plating, CVD, other suitable methods, or combinations thereof.

Still referring to fig. 9E, a compressively stressed dielectric film 204 is formed over the stack in the deep trench 150 so as to form a void (air gap) 206 in the deep trench 150 and seal the void 206 in the deep trench. This can be accomplished by various factors, such as by controlling the deposition rate to be large enough that the dielectric film 204 is deposited in the deep trench 150 and closes quickly on top, leaving a void 206 in the deep trench 150. In the disclosed embodiment, the deposition of the dielectric film 204 is performed at an elevated temperature, so that the dielectric film 204 is constrained by compressive stress when the workpiece is cooled to room temperature. Such deposited dielectric film 204 and DTC structure 64 may effectively reduce substrate warpage problems for two reasons. Because the stack of conductive layer 146 and dielectric layer 148 has a tensile stress to the workpiece, the compressive stress of dielectric film 204 compensates for the tensile stress of the stack, and void 206 formed in DTC structure 64 provides a free space for the workpiece to further relieve any stress, if any.

Dielectric film 204 may be formed by CVD, furnace process, other suitable methods, or combinations thereof. In some embodiments, the dielectric film 204 is formed by CVD. In a further embodiment, the dielectric film 204 includes NFARL, siO ₂ USG, silicon carbide, other suitable dielectric materials, or combinations thereof. For example, the dielectric film 204 includes silicon oxide formed by CVD using a precursor including TEOS. According to some embodiments, the deposition temperature is in a range between 800 ℃ and 1200 ℃.

In some embodiments, the dielectric film 204 is formed by a furnace process having a process temperature in a range between 800 ℃ and 1200 ℃. In a further embodiment, the dielectric film 204 comprises silicon nitride, siO ₂ USG, silicon carbide, polysilicon, other suitable materials, or combinations thereof. For example, dielectric film 204 includes silicon oxide formed in a furnace using a precursor including TEOS.

Referring to fig. 9F, the stack is further patterned to define a stack of conductive layers 146 and dielectric layers 148 for one DTC structure 64, such as being spaced apart from a stack of adjacent DTC structures 64. Another dielectric layer may be further deposited over the patterned stack and dielectric layer 158.

The final DTC structure 64 is also shown in fig. 9G, where 208 collectively represents a stack of dielectric layer 148 and conductive layer 146, and dielectric film 204. Specifically, the void 206 is formed in the deep trench 150, and the compressively stressed dielectric film seals the void 206 in the deep trench 150. Furthermore, the walls of the deep trenches 150 in the DTC structure 64 have the same height.

DTC structure 64 is also shown in fig. 9H and 9I. The tip portion 150T of the wall of the deep trench 150 may comprise different shapes depending on the adjustment and control of the etching process applied to the dielectric material layer 152. In some embodiments, the tip portion 150T of the wall of the deep trench 150 has a trapezoidal shape, such as shown in fig. 9H. In some embodiments, the tip portion 150T of the wall of the deep trench 150 has a sharp tip trapezoid shape, such as shown in fig. 9I.

Other components of the DTC structure 64, such as conductive plugs, will be further described below with reference to fig. 10A-10D and other figures. Fig. 10A-10D are partial cross-sectional views of a portion or an entirety of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure at various stages of manufacture.

Referring to fig. 10A, the DTC structure 64 shown herein may be the DTC structure 64 described in fig. 8A-8G or fig. 9A-9G, according to various embodiments. However, the simplification herein is made to illustrate the formation of conductive plugs of the DTC structure 64 and is not intended to be limiting. A stack of conductive layer 146 and dielectric layer 148 is formed and patterned in deep trench 150. In some embodiments, another dielectric layer 160 may be further deposited over the patterned stack and dielectric layer 204. Dielectric layer 160 may include one or more dielectric materials such as a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

Referring to fig. 10B, a layer of dielectric material 162 is formed over the patterned stack and dielectric film 202. The layer of dielectric material 162 may include one or more dielectric materials, such as USG. The thickness of the dielectric material layer 162 is designed in consideration of the conductive plugs to be formed. In the disclosed embodiment, the thickness of the dielectric material layer 162 is less than 1 micron. The layer of dielectric material 162 is formed by any suitable process, such as deposition by CVD and planarization by CMP. A hard mask 164, which serves as an etch mask to pattern the dielectric material layer 162, may be further formed on the dielectric material layer 162. In some embodiments, the hard mask 164 comprises one or more suitable materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. In the disclosed embodiment, the hard mask 164 includes a silicon oxynitride layer and a silicon oxide layer over the silicon oxynitride layer.

Referring to fig. 10C, the dielectric material layer 162 is patterned by a photolithography process and etched to form deep via holes 166. The via hole 166 is designed to form the conductive plug 154 therein. In disclosed embodiments, the patterning process may include: patterning the hard mask 164 by a photolithography process and etching to form an opening; the dielectric material layer 162 is etched using the patterned hard mask 164 as an etch mask. In particular, because the conductive plugs 154 are bonded to the respective conductive layers 146 at different heights, the via holes 166 are formed to have respective depths, and the respective conductive layers 146 are exposed at the bottom surfaces of the via holes 166. One way to achieve this is to apply a plurality of patterning processes to the dielectric material layer 162 to form via holes 166. For example, if the number of conductive layers 146 is N1 (such as 4 in the illustrated example), then the number of patterning processes is N1 (such as 4 in the illustrated example). This means that the N1 patterning processes each further include one photolithography process and one etching process. After the patterning process, via holes 166 are formed to expose the corresponding conductive layers 146, as shown in fig. 10C.

Referring to fig. 10D, conductive plugs 154 are formed in via holes 166 by a suitable process, such as a process including deposition and CMP. The hard mask 164 may be removed by a CMP or etching process before, after, or during the formation of the conductive plugs 154. It should be noted that each conductive plug 154 is intended to connect to the desired conductive layer 146, but may have a shorting problem with the intervening conductive layer 146. Accordingly, the conductive plugs 154 are designed with a dielectric material around their sidewalls to eliminate shorting problems. The formation of the conductive plugs 154 is designed with multiple layers of conductive material to address other issues such as delamination issues, packing density, and others. The formation of conductive plugs 154 will be described further below.

In some embodiments, a layer of dielectric material that is not present at the bottom of the via hole is formed on the sidewalls of the via hole 166. As can be seen from the above description, the conductive layer 146 is exposed from the bottom surface of the via hole 166 and is intended to be connected to the conductive plug 154. It is contemplated that other conductive layers 146 on top of the conductive layer 146 are also exposed from the sidewalls of the via hole 166, those conductive layers 146 being referred to as intervening conductive layers 146. The dielectric material layer is effective to prevent shorting between the conductive plugs 154 and the interposer 146. The formation of the dielectric material layer includes deposition and anisotropic etching (such as plasma etching) to remove portions of the dielectric material layer deposited on the bottom of the via hole 166. The layer of dielectric material includes one or more dielectric materials such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof. Deposition methods may include ALD, other suitable deposition, or combinations thereof. The layer of dielectric material includes a thickness that is large enough to provide an isolation function and thin enough not to substantially affect the opening size of the via hole 166. In the disclosed embodiment, the thickness of the layer of dielectric material is less than 10A, such as in the range between 5A and 8A.

In a further embodiment, a first metal-containing conductive layer is deposited in the via hole 166, in particular on the sidewalls of the dielectric material layer in the via hole 166. A second metal-containing conductive layer is deposited over the first metal-containing conductive layer within the via hole 166. The first metal-containing conductive layer and the second metal-containing conductive layer are different from each other in composition. The first and second metal-containing conductive layers are designed to provide integration, such as adhesion, of the conductive plugs 154 with the dielectric material layer 162 without using an existing barrier layer. For an existing barrier layer, if it is too thin, the existing barrier layer does not provide good integration and may lead to delamination problems. If it is too thick, the existing barrier layer will reduce the aspect ratio of the via hole and reduce the filling capability, possibly introducing defects of the conductive plug 154 such as voids. In the disclosed embodiments, the first metal-containing conductive layer comprises cobalt, nickel, other suitable metals, or combinations thereof. The first metal-containing conductive layer is deposited by ALD, other suitable deposition, or a combination thereof. The first metal-containing conductive layer may include a thickness greater than 10A, such as in the range between 10A and 15A. In some embodiments, the first metal-containing conductive layer may additionally or alternatively include titanium. The first metal-containing conductive layer serves as a glue layer to provide adhesion of the conductive plugs 154 to the dielectric material layer 162. In the disclosed embodiment, the second metal-containing conductive layer includes an alloy of copper (Cu) and manganese (Mn), referred to as CuMn. The second metal-containing conductive layer is deposited by PVD, CVD, ALD, other suitable deposition, or a combination thereof. The second metal-containing conductive layer may include a thickness greater than 10A, such as in the range between 10A and 20A. In some embodiments, the second metal-containing conductive layer may additionally or alternatively include other suitable conductive materials, such as titanium nitride or tantalum nitride.

A filler metal layer is filled over the second metal-containing conductive layer in the via hole 166 to form the conductive plug 154. The filler metal layer is compositionally different from the first metal-containing conductive layer and the second metal-containing conductive layer. The filler metal layer comprises aluminum (Al), aluminum copper alloy (AlCu), tungsten (W), other suitable metals, or combinations thereof. A filler metal layer is filled over the first and second metal-containing conductive layers within the via hole 166 by a suitable process, such as a thermal flow process. In a thermal flow process, the metal or alloy is heated to an elevated temperature such that the metal or alloy is flowable and deposited in the via hole 166 with enhanced filling capability and efficiency. The elevated temperature depends on the individual metal or alloy. For example, if the filler metal layer is aluminum, the elevated temperature is greater than 350 ℃. In a further example, a metal (such as Al) is deposited by PVD when the workpiece is heated to a reflow temperature, such as a temperature between 350 ℃ and 550 ℃ during PVD deposition. Thereafter, a CMP process may be further applied to remove excess deposited material and planarize the top surface. The conductive plugs may be formed in different configurations, such as those shown in fig. 11A and 11B, fig. 11A and 11B being partial cross-sectional views of portions or whole of DTC structures 64 constructed in accordance with some embodiments of the present disclosure.

Fig. 12 is a partial top view of a portion or the entirety of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure. The DTC structure 64 includes a plurality of DTC unit cells 67 configured as an array. The conductive plugs 154 are formed at gaps between the DTC unit cells 67. In particular, the DTC unit cells 67 have different shapes, such as hexagons. In each DTC unit cell 67, the deep trenches 150 are oriented in the same direction. However, the deep trenches 150 in adjacent DTC unit cells 67 are oriented in different directions. Specifically, the TDC structure 64 includes a first DTC unit cell having a deep trench 150 oriented in a first direction D1, a second DTC unit cell having a deep trench 150 oriented in a first direction D2, a third DTC unit cell having a deep trench 150 oriented in a third direction D3. The three directions D1, D2 and D3 are identical to each other. For example, D1 is in the Y direction, D2 is in a direction 120 degrees from D1, and D3 is in a direction 120 degrees from D1 or D2. In addition, the deep trenches 150 in the DTC unit cells 67 span different lengths, such as side deep trenches being shorter than the center deep trench 150C. The deeper the deep trench in the DTC unit cell 67 is, the shorter the farther it is from the center deep trench. The deep trenches 150 distributed on both sides of the center deep trench in one DTC unit cell 67 are symmetrically distributed. All the deep trenches 150 are arranged to have the same interval between adjacent deep trenches in one DTC unit cell 67.

Fig. 13A-13D are partial cross-sectional views of a portion or the entirety of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure. Fig. 13A shows a DTC structure 64 having a plurality of DTC unit cells 67, each DTC unit cell 67 having a hexagonal shape. Fig. 13B shows one DTC unit cell 67. Fig. 13C and 13D illustrate different configurations of deep trenches 150 in DTC unit cells 67. The orientation of the deep trench 150 in fig. 13C is in the X-direction, while the orientation of the deep trench 150 in fig. 13D is in the Y-direction. In particular, the deep trenches 150 in one DTC unit cell 67 include discontinuous deep trenches 150, such as two deep trenches 150 aligned in the longitudinal direction and spaced apart from each other.

Fig. 14A-14D are partial cross-sectional views of portions or whole of a DTC structure 64 constructed in accordance with some embodiments of the present disclosure. Fig. 14A shows a DTC structure 64 having a plurality of DTC unit cells 67, each DTC unit cell 67 having a parallelogram shape. Fig. 14B shows one DTC unit cell 67. Fig. 14C and 14D illustrate different configurations of deep trenches 150 in DTC unit cells 67. The orientation of the deep trench 150 in fig. 14C is in a direction parallel to the parallelogram long edges, while the orientation of the deep trench 150 in fig. 14D is in a direction parallel to the parallelogram short edges. In particular, the deep trenches 150 in one DTC unit cell 67 include deep trenches 150 that extend continuously and completely across between opposite edges of the DTC unit cell 67.

Embodiments of the present disclosure provide deep trench capacitor structures and methods of fabricating the same. The deep trench capacitor includes a plurality of conductive layers and dielectric layers alternately stacked and connected by conductive plugs to form a staggered capacitor. Furthermore, the stack of conductive and dielectric layers is folded and inserted into one or more deep trenches. The conductive plugs are designed with multiple layers of metals and metal alloys to increase adhesion and reduce the problem of delamination of the fill metal of the conductive plugs. In addition, a compressive stress dielectric film is further deposited in the deep trench in which the void is formed. The compressively stressed dielectric film compensates for the tensile stress of the conductive layer of the stack inserted into the deep trench, and the void further provides a space to relieve the stress. In some embodiments, the deep trenches in the DTC unit cells are designed to have different orientations, different patterns (such as broken deep trenches), and the DTC unit cells are designed to have different shapes, such as hexagons, parallelograms, or other suitable geometries. All of these spatial arrangements together further reduce pressure. Although not intended to be limiting, embodiments of the present disclosure provide benefits to semiconductor processing and semiconductor devices. For example, the disclosed structures and methods collectively reduce stress and prevent warping or other deformation of the workpiece.

In one exemplary aspect, the present disclosure provides an embodiment of a method comprising: patterning the substrate to form a trench; etching the substrate to modify the trench to have rounded tips; forming a stack comprising conductive layers and dielectric layers in the trench, wherein the conductive layers and dielectric layers alternate with each other within the stack; forming an insulating compression film in the first trench, thereby sealing the void in the trench; and forming conductive plugs respectively connected to the conductive layers.

In another exemplary aspect, embodiments of the present disclosure provide embodiments of a method comprising: patterning the substrate to form deep trenches; etching the substrate, thereby modifying the deep trench; forming a stack including conductive layers and dielectric layers alternately stacked and folded in the trench; and forming an insulating film in the first trench, thereby sealing the void in the deep trench. The deep trenches are configured as a plurality of deep trench unit cells. The deep trenches in each of the deep trench unit cells are oriented in the same direction. The deep trenches in adjacent deep trench unit cells are oriented in different directions.

In yet another exemplary aspect, embodiments of the present disclosure provide embodiments of a semiconductor structure, the semiconductor structure comprising: a plurality of deep trenches formed on a substrate; a stack of conductive layers and dielectric layers alternately disposed in the plurality of deep trenches; and conductive plugs respectively bonded on the conductive layers. The deep trenches are configured as a plurality of deep trench unit cells. The plurality of deep trenches in each of the deep trench unit cells are oriented in the same direction.

Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: patterning the substrate to form a trench; etching the substrate, thereby modifying the trench to have rounded tips; forming a stack comprising conductive layers and dielectric layers in the trench, wherein the conductive layers and dielectric layers alternate with each other within the stack; forming an insulating compression film in the first trench, thereby sealing a void in the trench; and forming conductive plugs respectively connected to the conductive layers. In some embodiments, forming an insulating compression film in the trench includes performing an annealing process in an oxygen ambient at an annealing temperature in a range between 800 ℃ and 1200 ℃. In some embodiments, forming an insulating compression film in the trench includes forming a silicon oxide (SiO ₂ ) At least one of a layer, a silicon nitride layer, a polysilicon layer, a silicon carbide layer, and combinations thereof. In some embodiments, forming an insulating compression film in the first trench includes performing a chemical vapor deposition process to form the insulating compression film. In some embodiments, forming an insulating compressive film in the first trench includes forming a nitrogen-free anti-reflective layer (NFARL), silicon oxide (SiO ₂ ) Layer, undoped quartz glass (USG) layer, carbonizationAt least one of a silicon layer and combinations thereof. In some embodiments, patterning a substrate to form a trench includes forming a first hard mask having a first opening on the substrate; and applying a first etching process to the substrate through the first opening of the first hard mask. In some embodiments, etching the substrate comprises: forming a second hard mask having a second opening on the substrate; and applying a second etching process to the substrate through the second opening of the second hard mask, wherein the second opening of the second hard mask is different from the first opening of the first hard mask. In some embodiments, patterning a substrate to form a trench includes patterning the substrate to form the trench configured as a plurality of deep trench unit cells, wherein each of the deep trench unit cells includes a plurality of deep trenches oriented in a same direction. In some embodiments, the plurality of deep trench unit cells comprises: a first deep trench unit cell having a first deep trench longitudinally oriented in a first direction; a second deep trench unit cell having a second deep trench longitudinally oriented in a second direction; a third deep trench unit cell having a third deep trench longitudinally oriented in a third direction; and the first direction, the second direction, and the third direction are different from one another. In some embodiments, the first direction and the second direction are oriented with 120 ° between the first direction and the second direction; the second direction and the third direction are oriented with 120 ° between the second direction and the third direction; and the third direction and the first direction are oriented with 120 ° between the third direction and the first direction. In some embodiments, the plurality of deep trenches in one of the deep trench unit cells includes a first deep trench and a second deep trench aligned with and remote from each other. In some embodiments, each of the plurality of deep trench unit cells occupies a region having a parallelogram or hexagon shape.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: patterning the substrate to form deep trenches; etching the substrate, thereby modifying the deep trench; forming a stack including conductive layers and dielectric layers alternately stacked and folded in the trench; and forming an insulating film in the first trench, thereby sealing a void in the deep trench, wherein the deep trench is configured as a plurality of deep trench unit cells, wherein the deep trenches in each of the deep trench unit cells are oriented in the same direction, and wherein the deep trenches in adjacent deep trench unit cells are oriented in different directions. In some embodiments, the method further comprises forming conductive plugs respectively connected to the conductive layers, wherein patterning the substrate to form trenches comprises forming a first hard mask having first openings on the substrate; applying a first etching process to the substrate through the first opening of the first hard mask; and etching the substrate further comprises forming a second hard mask having a second opening on the substrate, and applying a second etching process to the substrate through the second opening of the second hard mask, wherein the second opening of the second hard mask is different from the first opening of the first hard mask. In some embodiments, the plurality of deep trench unit cells comprises: a first deep trench unit cell having a first deep trench disposed in the first region and longitudinally oriented in a first direction; a second deep trench unit cell having a second deep trench disposed in the second region and longitudinally oriented in a second direction; a third deep trench unit cell having a third deep trench disposed in the second region and longitudinally oriented in a third direction; and the first direction, the second direction, and the third direction are different from one another. In some embodiments, each of the plurality of deep trench unit cells is shaped as one of a parallelogram and a hexagon; and the deep trenches in adjacent deep trench unit cells are not connected. In some embodiments, forming an insulating compression film in the trench includes forming the insulating film of compressive stress by performing an annealing process in an oxygen ambient at an annealing temperature in a range between 800 ℃ and 1200 ℃.

Still further embodiments of the present application provide a semiconductor structure comprising: a plurality of deep trenches formed on a substrate; a stack of conductive layers and dielectric layers alternately disposed in the plurality of deep trenches; and conductive plugs bonded on the conductive layers, respectively, wherein the deep trenches are configured as a plurality of deep trench unit cells, and wherein the plurality of deep trenches in each of the deep trench unit cells are oriented in the same direction. In some embodiments, the plurality of deep trench unit cells comprises: a first deep trench unit cell having a first deep trench disposed in the first region and longitudinally oriented in a first direction; a second deep trench unit cell having a second deep trench disposed in the second region and longitudinally oriented in a second direction; a third deep trench unit cell having a third deep trench disposed in the second region and longitudinally oriented in a third direction; and the first direction, the second direction, and the third direction are different from one another. In some embodiments, the plurality of deep trenches in each of the plurality of deep trench unit cells occupy a region having a parallelogram or hexagonal shape; and the plurality of deep trenches in adjacent deep trench unit cells are unconnected and oriented in different directions.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

patterning the substrate to form a trench;

etching the substrate, thereby modifying the trench to have rounded tips;

forming a stack comprising conductive layers and dielectric layers in the trench, wherein the conductive layers and dielectric layers alternate with each other within the stack;

forming an insulating compression film in the first trench, thereby sealing a void in the trench; and

conductive plugs respectively connected to the conductive layers are formed.

2. The method of claim 1, wherein forming an insulating compression film in the trench comprises performing an annealing process in an oxygen ambient at an annealing temperature in a range between 800 ℃ and 1200 ℃.

3. The method of claim 1, wherein forming an insulating compressive film in the trench comprises forming silicon oxide (SiO ₂ ) At least one of a layer, a silicon nitride layer, a polysilicon layer, a silicon carbide layer, and combinations thereof.

4. The method of claim 1, wherein forming an insulating compressive film in the first trench comprises performing a chemical vapor deposition process to form the insulating compressive film.

5. The method of claim 4, wherein forming an insulating compressive film in the first trench comprises forming a nitrogen-free anti-reflective layer (NFARL), silicon oxide (SiO ₂ ) At least one of a layer, an undoped quartz glass (USG) layer, a silicon carbide layer, and combinations thereof.

6. The method of claim 1, wherein,

patterning a substrate to form a trench includes forming a first hard mask having a first opening on the substrate; and

a first etching process is applied to the substrate through the first opening of the first hard mask.

7. The method of claim 6, wherein etching the substrate comprises:

forming a second hard mask having a second opening on the substrate; and

a second etching process is applied to the substrate through the second opening of the second hard mask, wherein the second opening of the second hard mask is different from the first opening of the first hard mask.

8. The method of claim 1, wherein patterning a substrate to form a trench comprises patterning the substrate to form the trench configured as a plurality of deep trench unit cells, wherein each of the deep trench unit cells comprises a plurality of deep trenches oriented in a same direction.

9. A method of forming a semiconductor structure, comprising:

patterning the substrate to form deep trenches;

etching the substrate, thereby modifying the deep trench;

forming a stack including conductive layers and dielectric layers alternately stacked and folded in the trench; and

an insulating film is formed in the first trench so as to seal a void in the deep trench, wherein the deep trench is configured as a plurality of deep trench unit cells, wherein the deep trenches in each of the deep trench unit cells are oriented in the same direction, and wherein the deep trenches in adjacent deep trench unit cells are oriented in different directions.

10. A semiconductor structure, comprising:

a plurality of deep trenches formed on a substrate;

a stack of conductive layers and dielectric layers alternately disposed in the plurality of deep trenches; and

conductive plugs bonded on the conductive layers, respectively, wherein the deep trenches are configured as a plurality of deep trench unit cells, and wherein the plurality of deep trenches in each of the deep trench unit cells are oriented in the same direction.