CN117174630B - High-efficiency semiconductor wafer conveying device - Google Patents
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Abstract
The invention discloses a high-efficiency semiconductor wafer conveying device, which belongs to the technical field of semiconductor conveying, and comprises a control box body, wherein a conveying frame body is slidably arranged at the lower end of the control box body, a hanging component is arranged at the lower end of the conveying frame body, a protection frame body is further arranged at the lower end of the conveying frame body, the hanging component is positioned in the protection frame body, the control box body comprises a region dividing module, a region selecting module and a control module, and a plurality of cameras are arranged at the bottom end of the protection frame body.
Description
Technical Field
The invention belongs to the technical field of semiconductor conveying, and particularly relates to a high-efficiency semiconductor wafer conveying device.
Background
In the semiconductor industry, the transportation of the semiconductor is a key link, in the prior art, the semiconductor is generally transported in two ways, one is transported by an AGV trolley according to a preset route and the other is transported by a wafer crown block, the wafer crown block is a key device for hanging, moving and processing the semiconductor materials, because the wafer crown block can maintain better stability in the transportation process, most semiconductor enterprises adopt the transportation of the wafer crown block, but the wafer crown block is not directly loaded for transportation, but the wafer cassette is hung for transportation, the wafer cassette is an important container for storing, transporting and protecting the semiconductor wafers, the wafer cassette ensures that the wafer is always in an ultra-clean and ultra-vacuum environment in the transportation process, and the wafer crown block and the artificial intelligent technology are combined to improve the transportation efficiency along with the development of the artificial intelligent technology.
For example, the patent with application publication number CN114955880a discloses a crown block walking safety monitoring system and crown block, including first image acquisition device, second image acquisition device, image recognition device and grabbing structure, acquire crown block travel path and grabbing structure decline route's image, judge whether there is the barrier to block through analyzing the image, guarantee the transportation safety of wafer box, and then improved the conveying efficiency of wafer, although above-mentioned crown block has combined with artificial intelligence technique to improve certain conveying efficiency, still have following defect:
the above patent judges whether there is the obstacle to block through the analysis image, but judge whether there is the obstacle through the analysis image and have been comparatively prior art, and the overhead traveling crane not only has the problem of obstacle in the transportation wafer box in-process, still has the problem of how to place the wafer box, current overhead traveling crane can only remove through the track, then in the in-process of placing the wafer box, the overhead traveling crane removes to appointed place and places the wafer box, therefore the wafer box is placed the process of overlapping in proper order, there is great instability between the wafer box of mutual overlapping, lead to the wafer in the box impaired easily like this.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description summary and in the title of the application, to avoid obscuring the purpose of this section, the description summary and the title of the invention, which should not be used to limit the scope of the invention.
In order to solve the problems, the invention adopts the following technical scheme.
The high-efficiency semiconductor wafer conveying device comprises a control box body, wherein a conveying frame body is arranged at the lower end of the control box body in a sliding manner, a hanging component is arranged at the lower end of the conveying frame body, a protection frame body is further arranged at the lower end of the conveying frame body, the hanging component is positioned in the protection frame body, the control box body comprises a region dividing module, a region selecting module and a control module, a plurality of cameras are arranged at the bottom end of the protection frame body, and the hanging component is used for grabbing a wafer box;
the camera is used for acquiring an image of a wafer box placement area, the image of the wafer box placement area comprises an overhead view and an oblique side view, the overhead view is an overhead view of the wafer box accommodating box, the oblique side view is an image between a surface wafer box and the top end of the side wall of the nearest wafer box accommodating box, and the surface wafer box is a wafer box of which the top end can be completely captured by the camera;
the region dividing module divides the overhead view to obtain N wafer box placement region images, wherein N is a positive integer greater than or equal to 1;
the area selection module is used for determining a target wafer box placement area based on the trained placement area classification model and the inclined side view, wherein the target wafer box placement area is the area for finally placing the wafer box;
and the control module is used for placing the wafer box into the wafer box accommodating box according to the target wafer box placing area.
Preferably, the plurality of cameras are all located the inside of protection framework, and the dispersion of a plurality of cameras sets up in the bottom of protection framework, and protection framework is made by toughened glass.
Preferably, the area dividing module divides the area by taking the area of the wafer cassette as a standard to obtain N wafer cassette placement area images, and the wafer cassette placement area image dividing logic is as follows:
establishing a plane rectangular coordinate system, wherein the plane rectangular coordinate system comprises an X axis and a Y axis, H standard dividing regions are used for tiling the plane rectangular coordinate system, the long side of each standard dividing region is kept parallel to the X axis respectively, and the wide side of each standard dividing region is parallel to the Y axis respectively;
the overhead view is placed in a planar rectangular coordinate system, and the overhead view is divided into N wafer cassette placement area images by H standard division areas.
Preferably, the method for determining the placement area of the target wafer cassette is as follows:
s10: inputting the N wafer cassette placement area images into an empty area generation model, acquiring the number of the empty areas, switching to S20 when the number of the empty areas is greater than 0, switching to S30 when the number of the empty areas is equal to 0, and enabling the empty areas to be wafer cassette placement areas without wafer cassettes;
s20: acquiring all the empty areas, and taking any one of the empty areas as a target wafer box placement area;
s30: preprocessing the oblique side view, obtaining the height difference between the top end of the surface wafer box and the top end of the wafer box accommodating box in each wafer box accommodating area, and determining the target wafer box accommodating area based on a plurality of height differences.
Preferably, the training process of the empty region generating model is as follows: acquiring i groups of data, wherein i is a positive integer greater than 1, the data comprise a plurality of wafer box placement area images and the number of empty areas, the plurality of wafer box placement area images and the number of empty areas are used as sample sets, the sample sets are divided into training sets and test sets, a classifier is constructed, the wafer box placement area images in the training sets are used as input data, the number of empty areas in the training sets are used as output data, the classifier is trained to obtain an initial classifier, the test set is used for testing the initial classifier, and the classifier meeting the preset accuracy is output to be used as an empty area generation model.
Preferably, the logic for determining the target cassette placement area based on the height difference is:
taking the maximum value and the minimum value in the height differences to obtain a maximum difference value, wherein the maximum difference value is obtained by subtracting the minimum value from the maximum value in the height differences;
if the maximum difference value is smaller than or equal to the height difference threshold value, taking any wafer box placement area as a target wafer box placement area;
if the maximum difference is greater than the height difference threshold, marking the wafer box placement area corresponding to the minimum value as a full area, marking the rest wafer box placement areas as blank areas, and taking any blank area as a target wafer box placement area.
Preferably, preprocessing of the oblique side view includes denoising, contrast enhancement, and image segmentation, and the method of acquiring the height difference by the oblique side view is a monocular parallax method.
Preferably, the top end of the transportation frame body is provided with a sliding groove, and the transportation frame body moves along the sliding groove.
Preferably, the suspension assembly comprises a pulley block, a steel wire rope and a grabbing frame, wherein the steel wire rope is wound on the surface of the pulley block, and one end of the steel wire rope is fixedly connected with the grabbing frame.
Preferably, the wafer box and the protection frame body are square, and the cameras are respectively arranged in the middle of each side of the bottom end of the protection frame body.
Compared with the prior art, the invention has the beneficial effects that:
1. the semiconductor wafer conveying device can move along the track and can move perpendicular to the track, so that after the semiconductor wafer conveying device drives the wafer boxes to move to a designated place, the wafer boxes are not placed immediately, a target wafer box placement area is determined through structures such as an area dividing module, an area selecting module, a control module and a camera, the wafer boxes are adjusted according to the target wafer box placement area, and finally the wafer boxes are placed, so that the wafer boxes can be tiled in the wafer box accommodating box, the wafer boxes can be mutually limited, the stability between the wafer boxes is enhanced, the wafer boxes are prevented from being excessively high in superposition, and large instability exists between the wafer boxes which are mutually superposed;
2. since the wafer cassette accommodation box is divided into the overhead views to determine the target wafer cassette accommodation area, the wafer cassette accommodation box can be adapted to wafer cassette accommodation boxes of different specifications.
Drawings
FIG. 1 is a schematic view of a wafer handling device;
FIG. 2 is a cross-sectional elevation view of a wafer handling device;
FIG. 3 is a schematic diagram of a system for controlling a cabinet;
FIG. 4 is an enlarged schematic view of the structure shown at A in FIG. 1;
fig. 5 is a front view of the wafer handling device above the cassette receiving bay;
fig. 6 is a front view of the wafer cassette placed inside the containment box by the wafer transport apparatus;
fig. 7 is a side view of the wafer handling device above the cassette receiving bay;
fig. 8 is a side view of the wafer cassette placed inside the containment box by the wafer transport apparatus;
FIG. 9 is a schematic diagram of a prior art crown block for placing a wafer cassette;
FIG. 10 is a schematic view of a crown block for placing a wafer cassette in accordance with the present invention;
FIG. 11 is an overhead view of the wafer cassette accommodation case;
FIG. 12 is a schematic view of an overhead view in a coordinate system;
fig. 13 is a schematic view of the overhead view divided into wafer cassette placement area images.
The correspondence between the reference numerals and the component names in the drawings is as follows:
10. a control box body; 11. a region dividing module; 12. a region selection module; 13. a control module; 20. a transport frame; 21. a sliding groove; 30. a suspension assembly; 31. pulley block; 32. a wire rope; 33. a grabbing frame; 40. a protective frame; 50. a camera; 60. a wafer cassette; 70. the wafer cassette contains a cassette.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
The embodiment provides a high-efficiency semiconductor wafer conveying device, as shown in fig. 1, 2 and 4, which comprises a control box body 10, wherein a moving groove is formed in the upper end of the control box body 10, a conveying frame body 20 is slidably arranged at the lower end of the control box body 10, a sliding groove 21 is formed in the top end of the conveying frame body 20, the conveying frame body 20 moves along the sliding groove 21, a hanging component 30 is arranged at the lower end of the conveying frame body 20, a protective frame body 40 is further arranged at the lower end of the conveying frame body 20, the hanging component 30 is positioned in the protective frame body 40, the hanging component 30 comprises a pulley block 31, a steel wire rope 32 and a grabbing frame 33, the steel wire rope 32 is wound on the surface of the pulley block 31, and one end of the steel wire rope 32 is fixedly connected with the grabbing frame 33;
in this embodiment, as shown in fig. 5 and 6, the control box 10 may transport the wafer box 60 along the track through the moving slot, the control box 10 drives the transport frame 20, the suspension assembly 30 and the wafer box 60 to move in sequence, the grabbing frame 33 is used for fixing the wafer box 60, it can be understood that the grabbing frame 33 may fix the wafer box 60 according to various modes, for example, an electric chuck is provided on the surface of the grabbing frame 33, the wafer box 60 may be adsorbed and fixed by the electric chuck, the pulley block 31 is not described in detail, when the wafer box 60 needs to be placed in an electric control mode, the pulley block 31 rotates to enable the steel wire rope 32 to be extended, and the grabbing frame 33 and the wafer box 60 are driven to move downwards until the wafer box 60 enters the wafer box accommodating box 70;
as shown in fig. 3, the control box 10 includes a region dividing module 11, a region selecting module 12 and a control module 13, wherein a plurality of cameras 50 are arranged at the bottom end of the protection frame 40, and the cameras 50 are respectively positioned around the protection frame 40;
the camera 50 is located inside the protective frame 40, and is used for acquiring an image of a wafer cassette placement area, wherein the image of the wafer cassette placement area comprises an overhead view and an oblique side view;
specifically, as shown in fig. 5, 6, 7 and 8, the plurality of cameras 50 are disposed at the bottom end of the protective frame 40 in a dispersed manner, when the wafer cassette 60 is driven by the semiconductor wafer conveying device to move to a designated location, the cameras 50 can obtain an image of a placement area of the wafer cassette below, on one hand, the plurality of cameras 50 are disposed in the protective frame 40, and on the other hand, the cameras 50 are not damaged even if encountering an obstacle during the movement of the semiconductor wafer conveying device, the material of the protective frame 40 is preferably tempered glass, and on the other hand, the plurality of cameras 50 are disposed at the bottom end of the protective frame 40, and the wafer cassette 60 is disposed in a middle area inside the protective frame 40, so that the cameras 50 are not blocked by the wafer cassette 60 during the process of obtaining the image of the placement area of the wafer cassette below;
it will be understood that, in the present invention, the camera 50 is preferably a panoramic camera, the image of the placement area of the wafer cassette includes a top view and an oblique side view, in this embodiment, the top view is a top view of the wafer cassette housing box 70, the oblique side view is an image between the surface wafer cassette and the top end of the side wall of the closest wafer cassette housing box 70, as shown in fig. 11, for example, the height of the wafer cassette housing box 70 is twice as high as that of the wafer cassette 60, if the wafer cassette housing box 70 has placed therein two layers of wafer cassettes 60, fig. 11 is a top view of the camera 50, in which case the wafer cassette 60 at the second layer is a surface wafer cassette, in which case D in fig. 11 is a surface wafer cassette, the wafer cassette 60 at the first layer and covered is not a surface wafer cassette, in which case E in fig. 11 is not a surface wafer cassette, in which case 60 is not covered by other wafer cassettes 60, and the top end of the wafer cassette 60 can be completely captured by the camera 50, the wafer cassette 60 is a surface wafer cassette 60;
the region dividing module 11 divides the overhead view to obtain N wafer cassette placement region images, wherein N is a positive integer greater than or equal to 1;
it should be noted that, in the present invention, the specification of the wafer cassette accommodation box 70 is designed based on the specification of the wafer cassette 60, and then the area dividing module 11 uses the area of the wafer cassette 60 as a standard dividing area, and completely divides the overhead view to obtain N wafer cassette placement area images, where specific division logic is:
as shown in fig. 12 and 13, a plane rectangular coordinate system is established, the plane rectangular coordinate system comprises an X axis and a Y axis, H standard division areas are used for tiling the plane rectangular coordinate system, long sides of each standard division area are kept parallel to the X axis respectively, broadsides of each standard division area are parallel to the Y axis respectively, and C in fig. 13 represents the standard division area;
placing the overhead view into a plane rectangular coordinate system, dividing the overhead view into N wafer cassette placement area images through H standard division areas, wherein B in FIG. 12 represents the overhead view, and F in FIG. 13 represents the wafer cassette placement area images;
the region selection module 12 determines a target wafer cassette placement region based on the trained placement region classification model and the oblique side view;
wherein the target cassette placement area is an area in which a cassette (60) is finally placed, and the method of determining the target cassette placement area is as follows:
s10: inputting the N wafer cassette placement area images into an empty area generation model, acquiring the number of the empty areas, switching to S20 when the number of the empty areas is greater than 0, and switching to S30 when the number of the empty areas is equal to 0;
specifically, the empty areas are wafer box placement areas where no wafer box 60 exists, when the number of the empty areas is greater than 0, it is indicated that no wafer box 60 exists in the wafer box placement areas, then the wafer box placement areas where no wafer box 60 exists need to be filled first, when the number of the empty areas is equal to 0, at least one wafer box 60 is stored in each wafer box placement area on the surface, and then N wafer box placement areas need to be tiled;
the training process of the empty region generation model is as follows: acquiring i groups of data, wherein i is a positive integer greater than 1, the data comprises a plurality of wafer box placement area images and the number of empty areas, the plurality of wafer box placement area images and the number of empty areas are used as sample sets, the sample sets are divided into training sets and test sets, a classifier is constructed, the wafer box placement area images in the training sets are used as input data, the number of empty areas in the training sets are used as output data, the classifier is trained to obtain an initial classifier, the initial classifier is tested by using the test sets, and the classifier meeting the preset accuracy is output to be used as an empty area generation model;
s20: acquiring all the empty areas, and taking any one of the empty areas as a target wafer box placement area;
s30: preprocessing the oblique side view, obtaining the height difference between the top end of the surface wafer box and the top end of the wafer box accommodating box 70 in each wafer box placing area, and determining a target wafer box placing area based on a plurality of height differences;
it should be noted that, the processing of the oblique side view includes denoising, contrast enhancement and image segmentation, the height difference between the top end of the surface wafer box and the top end of the wafer box accommodating box 70 is obtained through the oblique side view, which is the prior art, for example, a monocular parallax method, the parallax information of different parts in the image is used to infer the depth, the parallax of the object on the image and the distance thereof are in an inverse proportion relationship, and the common algorithm is a convolutional neural network, so the invention will not be repeated.
Logic for determining the target cassette placement area based on the height difference is:
taking the maximum value and the minimum value in the height differences to obtain a maximum difference value, wherein the maximum difference value is obtained by subtracting the minimum value from the maximum value in the height differences;
if the maximum difference value is smaller than or equal to the height difference threshold value, taking any wafer box placement area as a target wafer box placement area;
if the maximum difference is greater than the height difference threshold, marking the wafer box placement area corresponding to the minimum value as a full area, marking the rest wafer box placement areas as blank areas, and taking any blank area as a target wafer box placement area.
It will be appreciated that, as shown in fig. 9, when the maximum difference is less than or equal to the height difference threshold, it indicates that the wafer cassettes 60 inside the wafer cassette accommodating case 70 are all located in one plane, then any one of the wafer cassette placement areas may be used as the target wafer cassette placement area, as shown in fig. 10, if the maximum difference is greater than the height difference threshold, it indicates that the wafer cassettes 60 inside the wafer cassette accommodating case 70 are not located in one plane, then it is necessary to determine the wafer cassette placement areas with the largest number of the wafer cassettes 60 according to the height difference, mark the wafer cassette placement areas with the largest number of the wafer cassettes 60 as the filling areas, mark the rest of the wafer cassette placement areas as the blank areas, and place the wafer cassettes 60 toward the blank areas in sequence until the number of the wafer cassettes 60 in each wafer cassette placement area is equal.
The control module 13, put the wafer cassette 60 into the wafer cassette accommodation box 70 according to the target wafer cassette placement area;
specifically, the semiconductor wafer conveying device drives the wafer cassette 60 to be stored to a designated location, wherein the designated location is preferably directly above the center of the wafer cassette accommodating box 70, after the target wafer cassette accommodating area is obtained, the control box 10 moves along the track, and the transport frame 20 moves along the control box 10, so as to adjust the position of the wafer cassette 60 until the wafer cassette 60 is directly above the target wafer cassette accommodating area, and the wafer cassette 60 is placed into the wafer cassette accommodating box 70 for storage through the suspension assembly 30.
In this embodiment, the semiconductor wafer conveying device can move along the track and can move perpendicular to the track, so that after the semiconductor wafer conveying device drives the wafer cassettes 60 to move to a designated place, the wafer cassettes 60 are not immediately placed, but the target wafer cassette placement area is determined through the structures of the area dividing module 11, the area selecting module 12, the control module 13, the camera 50 and the like, and then the wafer cassettes 60 are adjusted according to the target wafer cassette placement area, and finally the wafer cassettes 60 are placed, so that the wafer cassettes 60 can be tiled inside the wafer cassette accommodating boxes 70, so that each wafer cassette 60 can be mutually limited, the stability between each wafer cassette 60 is enhanced, the overhigh overlapping of the wafer cassettes 60 is avoided, and the large instability exists between the wafer cassettes 60 overlapped with each other.
Example 2
In this embodiment, a further improvement is made on the basis of embodiment 1, in which the wafer box 60 and the protection frame 40 are square, and the plurality of cameras 50 are disposed in the middle of each side of the bottom end of the protection frame 40;
it should be noted that, the middle parts of the sides at the bottom end of the protection frame body 40 are all provided with the camera 50, so as to facilitate the camera 50 to better acquire the oblique side view, as shown in fig. 10, when the image between the surface wafer box and the top end of the side wall of the nearest wafer box accommodating box 70 needs to be acquired, the camera 50 needs to be acquired through the camera 50 at the opposite side, so that the camera 50 is arranged at the middle parts of the sides at the bottom end of the protection frame body 40, which is more beneficial to acquiring clear and complete images, and the wafer box 60 and the protection frame body 40 are square, because the wafer box accommodating box 70 is designed according to the specification of the wafer box 60, the wafer box accommodating box 70 is also in a regular shape, so that the overhead view of the wafer box accommodating box 70 is conveniently divided, and the storage of the wafer box 60 is more beneficial.
The above formulas are all formulas with dimensionality removed and numerical value calculated, the formulas are formulas with the latest real situation obtained by software simulation by collecting a large amount of data, and preset parameters, weights and threshold selection in the formulas are set by those skilled in the art according to the actual situation.
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present invention are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center over a wired network or a wireless network. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely one, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Finally: the foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The utility model provides a high efficiency semiconductor wafer conveyor, a serial communication port, including control box (10), the lower extreme of control box (10) slides and is provided with transportation support body (20), the lower extreme of transportation support body (20) is provided with suspension assembly (30), the lower extreme of transportation support body (20) still is provided with protection framework (40), suspension assembly (30) are located the inside of protection framework (40), control box (10) include regional division module (11), regional selection module (12) and control module (13), the bottom of protection framework (40) is provided with a plurality of cameras (50), wherein suspension assembly (30) are used for snatching wafer box (60);
the camera (50) is used for acquiring an image of a wafer box placement area, the image of the wafer box placement area comprises an overhead view and an oblique side view, the overhead view is a top view image of the wafer box accommodating box (70), the oblique side view is an image between a surface wafer box and the top end of the side wall of the nearest wafer box accommodating box (70), and the surface wafer box is a wafer box (60) of which the camera (50) can completely capture the top end;
the region dividing module (11) divides the overhead view to obtain N wafer box placement region images, wherein N is a positive integer greater than or equal to 1;
the region selection module (12) determines a target wafer box placement region based on the trained placement region classification model and the oblique side view, wherein the target wafer box placement region is a region in which the wafer box (60) is finally placed;
the control module (13) places the wafer cassette (60) inside the wafer cassette accommodation box (70) according to the target wafer cassette placement area.
2. The high-efficiency semiconductor wafer conveying device according to claim 1, wherein the plurality of cameras (50) are all located inside the protective frame body (40), and the plurality of cameras (50) are arranged at the bottom end of the protective frame body (40) in a dispersed manner, and the protective frame body (40) is made of toughened glass.
3. The high-efficiency semiconductor wafer handling device according to claim 1, wherein the area dividing module (11) divides the area of the wafer cassette (60) into N wafer cassette placement area images, and the wafer cassette placement area image dividing logic is configured to:
establishing a plane rectangular coordinate system, wherein the plane rectangular coordinate system comprises an X axis and a Y axis, H standard dividing regions are used for tiling the plane rectangular coordinate system, the long side of each standard dividing region is kept parallel to the X axis respectively, and the wide side of each standard dividing region is parallel to the Y axis respectively;
the overhead view is placed in a planar rectangular coordinate system, and the overhead view is divided into N wafer cassette placement area images by H standard division areas.
4. The high efficiency semiconductor wafer handling device of claim 2, wherein the method for determining the target cassette placement area comprises:
s10: inputting the N wafer cassette placement area images into an empty area generation model, acquiring the number of the empty areas, switching to S20 when the number of the empty areas is greater than 0, switching to S30 when the number of the empty areas is equal to 0, and enabling the empty areas to be wafer cassette placement areas without wafer cassettes (60);
s20: acquiring all the empty areas, and taking any one of the empty areas as a target wafer box placement area;
s30: preprocessing the oblique side view, obtaining the height difference between the top end of the surface wafer box and the top end of the wafer box accommodating box (70) in each wafer box placing area, and determining the target wafer box placing area based on a plurality of height differences.
5. The apparatus of claim 4, wherein the training process of the empty region generation model is: acquiring i groups of data, wherein i is a positive integer greater than 1, the data comprise a plurality of wafer box placement area images and the number of empty areas, the plurality of wafer box placement area images and the number of empty areas are used as sample sets, the sample sets are divided into training sets and test sets, a classifier is constructed, the wafer box placement area images in the training sets are used as input data, the number of empty areas in the training sets are used as output data, the classifier is trained to obtain an initial classifier, the test set is used for testing the initial classifier, and the classifier meeting the preset accuracy is output to be used as an empty area generation model.
6. The high efficiency semiconductor wafer handling device of claim 4, wherein the logic for determining the target cassette placement area based on the height differential is:
taking the maximum value and the minimum value in the height differences to obtain a maximum difference value, wherein the maximum difference value is obtained by subtracting the minimum value from the maximum value in the height differences;
if the maximum difference value is smaller than or equal to the height difference threshold value, taking any wafer box placement area as a target wafer box placement area;
if the maximum difference is greater than the height difference threshold, marking the wafer box placement area corresponding to the minimum value as a full area, marking the rest wafer box placement areas as blank areas, and taking any blank area as a target wafer box placement area.
7. The apparatus of claim 4, wherein the preprocessing of the oblique side view includes denoising, contrast enhancement, and image segmentation, and the method of obtaining the height difference from the oblique side view is a monocular parallax method.
8. The high-efficiency semiconductor wafer transport apparatus as claimed in claim 1, wherein a slide groove (21) is provided at a top end of the transport frame (20), and the transport frame (20) moves along the slide groove (21).
9. The high-efficiency semiconductor wafer conveying device according to claim 1, wherein the suspension assembly (30) comprises a pulley block (31), a steel wire rope (32) and a grabbing frame (33), the steel wire rope (32) is wound on the surface of the pulley block (31), and one end of the steel wire rope (32) is fixedly connected with the grabbing frame (33).
10. The high-efficiency semiconductor wafer handling device according to claim 2, wherein the wafer cassette (60) and the protective frame (40) are square, and the plurality of cameras (50) are respectively disposed at the middle parts of the sides of the bottom end of the protective frame (40).
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980020300A (en) * | 1996-09-06 | 1998-06-25 | 김광호 | Semiconductor Wafer Cassette Stocker |
| EP1067592A2 (en) * | 1999-07-09 | 2001-01-10 | Applied Materials, Inc. | Compact apparatus and method for storing and loading semiconductor wafer carriers |
| KR20150145957A (en) * | 2014-06-20 | 2015-12-31 | 용현하이텍(주) | Apparatus for supplying wafer |
| KR20190096551A (en) * | 2018-02-09 | 2019-08-20 | 코리아테크노(주) | Wafer transfer device and wafer transfer method |
| CN113257723A (en) * | 2021-07-08 | 2021-08-13 | 北京北方华创微电子装备有限公司 | Semiconductor processing equipment |
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2023
- 2023-11-02 CN CN202311449297.5A patent/CN117174630B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980020300A (en) * | 1996-09-06 | 1998-06-25 | 김광호 | Semiconductor Wafer Cassette Stocker |
| EP1067592A2 (en) * | 1999-07-09 | 2001-01-10 | Applied Materials, Inc. | Compact apparatus and method for storing and loading semiconductor wafer carriers |
| KR20150145957A (en) * | 2014-06-20 | 2015-12-31 | 용현하이텍(주) | Apparatus for supplying wafer |
| KR20190096551A (en) * | 2018-02-09 | 2019-08-20 | 코리아테크노(주) | Wafer transfer device and wafer transfer method |
| CN113257723A (en) * | 2021-07-08 | 2021-08-13 | 北京北方华创微电子装备有限公司 | Semiconductor processing equipment |
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